2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "si_shader.h"
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
38 #define SI_BIG_ENDIAN 0
41 #define ATI_VENDOR_ID 0x1002
43 #define SI_NOT_QUERY 0xffffffff
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_NUM_SMOOTH_AA_SAMPLES 8
51 #define SI_GS_PER_ES 128
52 /* Alignment for optimal CP DMA performance. */
53 #define SI_CPDMA_ALIGNMENT 32
55 /* Pipeline & streamout query controls. */
56 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
57 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
58 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
59 /* Instruction cache. */
60 #define SI_CONTEXT_INV_ICACHE (1 << 3)
61 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
62 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
63 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
64 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
65 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
66 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
67 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
68 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
69 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
70 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
71 * a CB or DB flush. */
72 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
73 /* Framebuffer caches. */
74 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
75 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
76 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
77 /* Engine synchronization. */
78 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
79 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
80 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
81 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
82 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
84 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
85 #define SI_PREFETCH_LS (1 << 1)
86 #define SI_PREFETCH_HS (1 << 2)
87 #define SI_PREFETCH_ES (1 << 3)
88 #define SI_PREFETCH_GS (1 << 4)
89 #define SI_PREFETCH_VS (1 << 5)
90 #define SI_PREFETCH_PS (1 << 6)
92 #define SI_MAX_BORDER_COLORS 4096
93 #define SI_MAX_VIEWPORTS 16
95 #define SI_MAP_BUFFER_ALIGNMENT 64
96 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
98 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
99 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
100 #define SI_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
101 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
102 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
103 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
104 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
108 /* Shader logging options: */
109 DBG_VS
= PIPE_SHADER_VERTEX
,
110 DBG_PS
= PIPE_SHADER_FRAGMENT
,
111 DBG_GS
= PIPE_SHADER_GEOMETRY
,
112 DBG_TCS
= PIPE_SHADER_TESS_CTRL
,
113 DBG_TES
= PIPE_SHADER_TESS_EVAL
,
114 DBG_CS
= PIPE_SHADER_COMPUTE
,
120 /* Shader compiler options the shader cache should be aware of: */
121 DBG_FS_CORRECT_DERIVS_AFTER_KILL
,
126 /* Shader compiler options (with no effect on the shader cache): */
129 DBG_MONOLITHIC_SHADERS
,
132 /* Information logging options: */
138 /* Driver options: */
146 /* 3D engine options: */
166 DBG_TEST_VMFAULT_SDMA
,
167 DBG_TEST_VMFAULT_SHADER
,
171 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
172 #define DBG(name) (1ull << DBG_##name)
176 struct u_suballocator
;
178 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
181 struct r600_resource
{
182 struct threaded_resource b
;
184 /* Winsys objects. */
185 struct pb_buffer
*buf
;
186 uint64_t gpu_address
;
187 /* Memory usage if the buffer placement is optimal. */
191 /* Resource properties. */
193 unsigned bo_alignment
;
194 enum radeon_bo_domain domains
;
195 enum radeon_bo_flag flags
;
196 unsigned bind_history
;
197 int max_forced_staging_uploads
;
199 /* The buffer range which is initialized (with a write transfer,
200 * streamout, DMA, or as a random access target). The rest of
201 * the buffer is considered invalid and can be mapped unsynchronized.
203 * This allows unsychronized mapping of a buffer range which hasn't
204 * been used yet. It's for applications which forget to use
205 * the unsynchronized map flag and expect the driver to figure it out.
207 struct util_range valid_buffer_range
;
209 /* For buffers only. This indicates that a write operation has been
210 * performed by TC L2, but the cache hasn't been flushed.
211 * Any hw block which doesn't use or bypasses TC L2 should check this
212 * flag and flush the cache before using the buffer.
214 * For example, TC L2 must be flushed if a buffer which has been
215 * modified by a shader store instruction is about to be used as
216 * an index buffer. The reason is that VGT DMA index fetching doesn't
221 /* Whether this resource is referenced by bindless handles. */
222 bool texture_handle_allocated
;
223 bool image_handle_allocated
;
225 /* Whether the resource has been exported via resource_get_handle. */
226 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
230 struct threaded_transfer b
;
231 struct r600_resource
*staging
;
236 struct r600_resource buffer
;
238 struct radeon_surf surface
;
240 struct si_texture
*flushed_depth_texture
;
242 /* Colorbuffer compression and fast clear. */
243 uint64_t fmask_offset
;
244 uint64_t cmask_offset
;
245 uint64_t cmask_base_address_reg
;
246 struct r600_resource
*cmask_buffer
;
247 uint64_t dcc_offset
; /* 0 = disabled */
248 unsigned cb_color_info
; /* fast clear enable bit */
249 unsigned color_clear_value
[2];
250 unsigned last_msaa_resolve_target_micro_mode
;
251 unsigned num_level0_transfers
;
253 /* Depth buffer compression and fast clear. */
254 uint64_t htile_offset
;
255 float depth_clear_value
;
256 uint16_t dirty_level_mask
; /* each bit says if that mipmap is compressed */
257 uint16_t stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
258 enum pipe_format db_render_format
:16;
259 uint8_t stencil_clear_value
;
260 bool tc_compatible_htile
:1;
261 bool depth_cleared
:1; /* if it was cleared at least once */
262 bool stencil_cleared
:1; /* if it was cleared at least once */
263 bool upgraded_depth
:1; /* upgraded from unorm to Z32_FLOAT */
265 bool db_compatible
:1;
269 /* We need to track DCC dirtiness, because st/dri usually calls
270 * flush_resource twice per frame (not a bug) and we don't wanna
271 * decompress DCC twice. Also, the dirty tracking must be done even
272 * if DCC isn't used, because it's required by the DCC usage analysis
273 * for a possible future enablement.
275 bool separate_dcc_dirty
:1;
276 /* Statistics gathering for the DCC enablement heuristic. */
277 bool dcc_gather_statistics
:1;
278 /* Counter that should be non-zero if the texture is bound to a
281 unsigned framebuffers_bound
;
282 /* Whether the texture is a displayable back buffer and needs DCC
283 * decompression, which is expensive. Therefore, it's enabled only
284 * if statistics suggest that it will pay off and it's allocated
285 * separately. It can't be bound as a sampler by apps. Limited to
286 * target == 2D and last_level == 0. If enabled, dcc_offset contains
287 * the absolute GPUVM address, not the relative one.
289 struct r600_resource
*dcc_separate_buffer
;
290 /* When DCC is temporarily disabled, the separate buffer is here. */
291 struct r600_resource
*last_dcc_separate_buffer
;
292 /* Estimate of how much this color buffer is written to in units of
293 * full-screen draws: ps_invocations / (width * height)
294 * Shader kills, late Z, and blending with trivial discards make it
295 * inaccurate (we need to count CB updates, not PS invocations).
297 unsigned ps_draw_ratio
;
298 /* The number of clears since the last DCC usage analysis. */
299 unsigned num_slow_clears
;
303 struct pipe_surface base
;
305 /* These can vary with block-compressed textures. */
309 bool color_initialized
:1;
310 bool depth_initialized
:1;
312 /* Misc. color flags. */
313 bool color_is_int8
:1;
314 bool color_is_int10
:1;
315 bool dcc_incompatible
:1;
317 /* Color registers. */
318 unsigned cb_color_info
;
319 unsigned cb_color_view
;
320 unsigned cb_color_attrib
;
321 unsigned cb_color_attrib2
; /* GFX9 and later */
322 unsigned cb_dcc_control
; /* VI and later */
323 unsigned spi_shader_col_format
:8; /* no blending, no alpha-to-coverage. */
324 unsigned spi_shader_col_format_alpha
:8; /* alpha-to-coverage */
325 unsigned spi_shader_col_format_blend
:8; /* blending without alpha. */
326 unsigned spi_shader_col_format_blend_alpha
:8; /* blending with alpha. */
329 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE */
330 uint64_t db_stencil_base
;
331 uint64_t db_htile_data_base
;
332 unsigned db_depth_info
;
334 unsigned db_z_info2
; /* GFX9+ */
335 unsigned db_depth_view
;
336 unsigned db_depth_size
;
337 unsigned db_depth_slice
;
338 unsigned db_stencil_info
;
339 unsigned db_stencil_info2
; /* GFX9+ */
340 unsigned db_htile_surface
;
343 struct si_mmio_counter
{
348 union si_mmio_counters
{
350 /* For global GPU load including SDMA. */
351 struct si_mmio_counter gpu
;
354 struct si_mmio_counter spi
;
355 struct si_mmio_counter gui
;
356 struct si_mmio_counter ta
;
357 struct si_mmio_counter gds
;
358 struct si_mmio_counter vgt
;
359 struct si_mmio_counter ia
;
360 struct si_mmio_counter sx
;
361 struct si_mmio_counter wd
;
362 struct si_mmio_counter bci
;
363 struct si_mmio_counter sc
;
364 struct si_mmio_counter pa
;
365 struct si_mmio_counter db
;
366 struct si_mmio_counter cp
;
367 struct si_mmio_counter cb
;
370 struct si_mmio_counter sdma
;
373 struct si_mmio_counter pfp
;
374 struct si_mmio_counter meq
;
375 struct si_mmio_counter me
;
376 struct si_mmio_counter surf_sync
;
377 struct si_mmio_counter cp_dma
;
378 struct si_mmio_counter scratch_ram
;
383 struct si_memory_object
{
384 struct pipe_memory_object b
;
385 struct pb_buffer
*buf
;
389 /* Saved CS data for debugging features. */
390 struct radeon_saved_cs
{
394 struct radeon_bo_list_item
*bo_list
;
399 struct pipe_screen b
;
400 struct radeon_winsys
*ws
;
401 struct disk_cache
*disk_shader_cache
;
403 struct radeon_info info
;
404 uint64_t debug_flags
;
405 char renderer_string
[183];
407 unsigned gs_table_depth
;
408 unsigned tess_offchip_block_dw_size
;
409 unsigned tess_offchip_ring_size
;
410 unsigned tess_factor_ring_size
;
411 unsigned vgt_hs_offchip_param
;
412 unsigned eqaa_force_coverage_samples
;
413 unsigned eqaa_force_z_samples
;
414 unsigned eqaa_force_color_samples
;
415 bool has_clear_state
;
416 bool has_distributed_tess
;
417 bool has_draw_indirect_multi
;
418 bool has_out_of_order_rast
;
419 bool assume_no_z_fights
;
420 bool commutative_blend_add
;
421 bool clear_db_cache_before_clear
;
422 bool has_msaa_sample_loc_bug
;
423 bool has_ls_vgpr_init_bug
;
426 bool llvm_has_working_vgpr_indexing
;
428 /* Whether shaders are monolithic (1-part) or separate (3-part). */
429 bool use_monolithic_shaders
;
431 bool has_rbplus
; /* if RB+ registers exist */
432 bool rbplus_allowed
; /* if RB+ is allowed */
433 bool dcc_msaa_allowed
;
434 bool cpdma_prefetch_writes_memory
;
436 struct slab_parent_pool pool_transfers
;
438 /* Texture filter settings. */
439 int force_aniso
; /* -1 = disabled */
441 /* Auxiliary context. Mainly used to initialize resources.
442 * It must be locked prior to using and flushed before unlocking. */
443 struct pipe_context
*aux_context
;
444 mtx_t aux_context_lock
;
446 /* This must be in the screen, because UE4 uses one context for
447 * compilation and another one for rendering.
449 unsigned num_compilations
;
450 /* Along with ST_DEBUG=precompile, this should show if applications
451 * are loading shaders on demand. This is a monotonic counter.
453 unsigned num_shaders_created
;
454 unsigned num_shader_cache_hits
;
456 /* GPU load thread. */
457 mtx_t gpu_load_mutex
;
458 thrd_t gpu_load_thread
;
459 union si_mmio_counters mmio_counters
;
460 volatile unsigned gpu_load_stop_thread
; /* bool */
462 /* Performance counters. */
463 struct si_perfcounters
*perfcounters
;
465 /* If pipe_screen wants to recompute and re-emit the framebuffer,
466 * sampler, and image states of all contexts, it should atomically
469 * Each context will compare this with its own last known value of
470 * the counter before drawing and re-emit the states accordingly.
472 unsigned dirty_tex_counter
;
474 /* Atomically increment this counter when an existing texture's
475 * metadata is enabled or disabled in a way that requires changing
476 * contexts' compressed texture binding masks.
478 unsigned compressed_colortex_counter
;
481 /* Context flags to set so that all writes from earlier jobs
482 * in the CP are seen by L2 clients.
486 /* Context flags to set so that all writes from earlier jobs
487 * that end in L2 are seen by CP.
492 mtx_t shader_parts_mutex
;
493 struct si_shader_part
*vs_prologs
;
494 struct si_shader_part
*tcs_epilogs
;
495 struct si_shader_part
*gs_prologs
;
496 struct si_shader_part
*ps_prologs
;
497 struct si_shader_part
*ps_epilogs
;
499 /* Shader cache in memory.
501 * Design & limitations:
502 * - The shader cache is per screen (= per process), never saved to
503 * disk, and skips redundant shader compilations from TGSI to bytecode.
504 * - It can only be used with one-variant-per-shader support, in which
505 * case only the main (typically middle) part of shaders is cached.
506 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
507 * variants of VS and TES are cached, so LS and ES aren't.
508 * - GS and CS aren't cached, but it's certainly possible to cache
511 mtx_t shader_cache_mutex
;
512 struct hash_table
*shader_cache
;
514 /* Shader compiler queue for multithreaded compilation. */
515 struct util_queue shader_compiler_queue
;
516 /* Use at most 3 normal compiler threads on quadcore and better.
517 * Hyperthreaded CPUs report the number of threads, but we want
518 * the number of cores. We only need this many threads for shader-db. */
519 struct ac_llvm_compiler compiler
[24]; /* used by the queue only */
521 struct util_queue shader_compiler_queue_low_priority
;
522 /* Use at most 2 low priority threads on quadcore and better.
523 * We want to minimize the impact on multithreaded Mesa. */
524 struct ac_llvm_compiler compiler_lowp
[10];
527 struct si_blend_color
{
528 struct pipe_blend_color state
;
532 struct si_sampler_view
{
533 struct pipe_sampler_view base
;
534 /* [0..7] = image descriptor
535 * [4..7] = buffer descriptor */
537 uint32_t fmask_state
[8];
538 const struct legacy_surf_level
*base_level_info
;
541 bool is_stencil_sampler
;
543 bool dcc_incompatible
;
546 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
548 struct si_sampler_state
{
553 uint32_t integer_val
[4];
554 uint32_t upgraded_depth_val
[4];
557 struct si_cs_shader_state
{
558 struct si_compute
*program
;
559 struct si_compute
*emitted_program
;
566 struct pipe_sampler_view
*views
[SI_NUM_SAMPLERS
];
567 struct si_sampler_state
*sampler_states
[SI_NUM_SAMPLERS
];
569 /* The i-th bit is set if that element is enabled (non-NULL resource). */
570 unsigned enabled_mask
;
571 uint32_t needs_depth_decompress_mask
;
572 uint32_t needs_color_decompress_mask
;
576 struct pipe_image_view views
[SI_NUM_IMAGES
];
577 uint32_t needs_color_decompress_mask
;
578 unsigned enabled_mask
;
581 struct si_framebuffer
{
582 struct pipe_framebuffer_state state
;
583 unsigned colorbuf_enabled_4bit
;
584 unsigned spi_shader_col_format
;
585 unsigned spi_shader_col_format_alpha
;
586 unsigned spi_shader_col_format_blend
;
587 unsigned spi_shader_col_format_blend_alpha
;
588 ubyte nr_samples
:5; /* at most 16xAA */
589 ubyte log_samples
:3; /* at most 4 = 16xAA */
590 ubyte nr_color_samples
; /* at most 8xAA */
591 ubyte compressed_cb_mask
;
592 ubyte uncompressed_cb_mask
;
594 ubyte color_is_int10
;
598 bool CB_has_shader_readable_metadata
;
599 bool DB_has_shader_readable_metadata
;
602 struct si_signed_scissor
{
611 struct pipe_scissor_state states
[SI_MAX_VIEWPORTS
];
614 struct si_viewports
{
616 unsigned depth_range_dirty_mask
;
617 struct pipe_viewport_state states
[SI_MAX_VIEWPORTS
];
618 struct si_signed_scissor as_scissor
[SI_MAX_VIEWPORTS
];
621 struct si_clip_state
{
622 struct pipe_clip_state state
;
626 struct si_streamout_target
{
627 struct pipe_stream_output_target b
;
629 /* The buffer where BUFFER_FILLED_SIZE is stored. */
630 struct r600_resource
*buf_filled_size
;
631 unsigned buf_filled_size_offset
;
632 bool buf_filled_size_valid
;
634 unsigned stride_in_dw
;
637 struct si_streamout
{
640 unsigned enabled_mask
;
641 unsigned num_targets
;
642 struct si_streamout_target
*targets
[PIPE_MAX_SO_BUFFERS
];
644 unsigned append_bitmask
;
647 /* External state which comes from the vertex shader,
648 * it must be set explicitly when binding a shader. */
649 uint16_t *stride_in_dw
;
650 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
652 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
653 unsigned hw_enabled_mask
;
655 /* The state of VGT_STRMOUT_(CONFIG|EN). */
656 bool streamout_enabled
;
657 bool prims_gen_query_enabled
;
658 int num_prims_gen_queries
;
661 /* A shader state consists of the shader selector, which is a constant state
662 * object shared by multiple contexts and shouldn't be modified, and
663 * the current shader variant selected for this context.
665 struct si_shader_ctx_state
{
666 struct si_shader_selector
*cso
;
667 struct si_shader
*current
;
670 #define SI_NUM_VGT_PARAM_KEY_BITS 12
671 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
673 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
674 * Some fields are set by state-change calls, most are set by draw_vbo.
676 union si_vgt_param_key
{
678 #ifdef PIPE_ARCH_LITTLE_ENDIAN
680 unsigned uses_instancing
:1;
681 unsigned multi_instances_smaller_than_primgroup
:1;
682 unsigned primitive_restart
:1;
683 unsigned count_from_stream_output
:1;
684 unsigned line_stipple_enabled
:1;
685 unsigned uses_tess
:1;
686 unsigned tess_uses_prim_id
:1;
688 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
689 #else /* PIPE_ARCH_BIG_ENDIAN */
690 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
692 unsigned tess_uses_prim_id
:1;
693 unsigned uses_tess
:1;
694 unsigned line_stipple_enabled
:1;
695 unsigned count_from_stream_output
:1;
696 unsigned primitive_restart
:1;
697 unsigned multi_instances_smaller_than_primgroup
:1;
698 unsigned uses_instancing
:1;
705 struct si_texture_handle
709 struct pipe_sampler_view
*view
;
710 struct si_sampler_state sstate
;
713 struct si_image_handle
717 struct pipe_image_view view
;
721 struct pipe_reference reference
;
722 struct si_context
*ctx
;
723 struct radeon_saved_cs gfx
;
724 struct r600_resource
*trace_buf
;
727 unsigned gfx_last_dw
;
733 struct pipe_context b
; /* base class */
735 enum radeon_family family
;
736 enum chip_class chip_class
;
738 struct radeon_winsys
*ws
;
739 struct radeon_winsys_ctx
*ctx
;
740 struct radeon_cmdbuf
*gfx_cs
;
741 struct radeon_cmdbuf
*dma_cs
;
742 struct pipe_fence_handle
*last_gfx_fence
;
743 struct pipe_fence_handle
*last_sdma_fence
;
744 struct r600_resource
*eop_bug_scratch
;
745 struct u_upload_mgr
*cached_gtt_allocator
;
746 struct threaded_context
*tc
;
747 struct u_suballocator
*allocator_zeroed_memory
;
748 struct slab_child_pool pool_transfers
;
749 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
750 struct pipe_device_reset_callback device_reset_callback
;
751 struct u_log_context
*log
;
752 void *query_result_shader
;
753 struct blitter_context
*blitter
;
754 void *custom_dsa_flush
;
755 void *custom_blend_resolve
;
756 void *custom_blend_fmask_decompress
;
757 void *custom_blend_eliminate_fastclear
;
758 void *custom_blend_dcc_decompress
;
760 void *vs_blit_pos_layered
;
762 void *vs_blit_color_layered
;
763 void *vs_blit_texcoord
;
764 struct si_screen
*screen
;
765 struct pipe_debug_callback debug
;
766 struct ac_llvm_compiler compiler
; /* only non-threaded compilation */
767 struct si_shader_ctx_state fixed_func_tcs_shader
;
768 struct r600_resource
*wait_mem_scratch
;
769 unsigned wait_mem_number
;
770 uint16_t prefetch_L2_mask
;
772 bool gfx_flush_in_progress
:1;
773 bool gfx_last_ib_is_busy
:1;
774 bool compute_is_busy
:1;
776 unsigned num_gfx_cs_flushes
;
777 unsigned initial_gfx_cs_size
;
778 unsigned gpu_reset_counter
;
779 unsigned last_dirty_tex_counter
;
780 unsigned last_compressed_colortex_counter
;
781 unsigned last_num_draw_calls
;
782 unsigned flags
; /* flush flags */
783 /* Current unaccounted memory usage. */
787 /* Atoms (direct states). */
788 union si_state_atoms atoms
;
789 unsigned dirty_atoms
; /* mask */
790 /* PM4 states (precomputed immutable states) */
791 unsigned dirty_states
;
792 union si_state queued
;
793 union si_state emitted
;
795 /* Atom declarations. */
796 struct si_framebuffer framebuffer
;
797 unsigned sample_locs_num_samples
;
798 uint16_t sample_mask
;
799 unsigned last_cb_target_mask
;
800 struct si_blend_color blend_color
;
801 struct si_clip_state clip_state
;
802 struct si_shader_data shader_pointers
;
803 struct si_stencil_ref stencil_ref
;
804 struct si_scissors scissors
;
805 struct si_streamout streamout
;
806 struct si_viewports viewports
;
807 unsigned num_window_rectangles
;
808 bool window_rectangles_include
;
809 struct pipe_scissor_state window_rectangles
[4];
811 /* Precomputed states. */
812 struct si_pm4_state
*init_config
;
813 struct si_pm4_state
*init_config_gs_rings
;
814 bool init_config_has_vgt_flush
;
815 struct si_pm4_state
*vgt_shader_config
[4];
818 struct si_shader_ctx_state ps_shader
;
819 struct si_shader_ctx_state gs_shader
;
820 struct si_shader_ctx_state vs_shader
;
821 struct si_shader_ctx_state tcs_shader
;
822 struct si_shader_ctx_state tes_shader
;
823 struct si_cs_shader_state cs_shader_state
;
825 /* shader information */
826 struct si_vertex_elements
*vertex_elements
;
827 unsigned sprite_coord_enable
;
828 unsigned cs_max_waves_per_sh
;
830 bool do_update_shaders
;
832 /* vertex buffer descriptors */
833 uint32_t *vb_descriptors_gpu_list
;
834 struct r600_resource
*vb_descriptors_buffer
;
835 unsigned vb_descriptors_offset
;
837 /* shader descriptors */
838 struct si_descriptors descriptors
[SI_NUM_DESCS
];
839 unsigned descriptors_dirty
;
840 unsigned shader_pointers_dirty
;
841 unsigned shader_needs_decompress_mask
;
842 struct si_buffer_resources rw_buffers
;
843 struct si_buffer_resources const_and_shader_buffers
[SI_NUM_SHADERS
];
844 struct si_samplers samplers
[SI_NUM_SHADERS
];
845 struct si_images images
[SI_NUM_SHADERS
];
847 /* other shader resources */
848 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on CIK */
849 struct pipe_resource
*esgs_ring
;
850 struct pipe_resource
*gsvs_ring
;
851 struct pipe_resource
*tess_rings
;
852 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
853 struct r600_resource
*border_color_buffer
;
854 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
855 unsigned border_color_count
;
856 unsigned num_vs_blit_sgprs
;
857 uint32_t vs_blit_sh_data
[SI_VS_BLIT_SGPRS_POS_TEXCOORD
];
858 uint32_t cs_user_data
[4];
860 /* Vertex and index buffers. */
861 bool vertex_buffers_dirty
;
862 bool vertex_buffer_pointer_dirty
;
863 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
865 /* MSAA config state. */
867 bool ps_uses_fbfetch
;
868 bool smoothing_enabled
;
870 /* DB render state. */
871 unsigned ps_db_shader_control
;
872 unsigned dbcb_copy_sample
;
873 bool dbcb_depth_copy_enabled
:1;
874 bool dbcb_stencil_copy_enabled
:1;
875 bool db_flush_depth_inplace
:1;
876 bool db_flush_stencil_inplace
:1;
877 bool db_depth_clear
:1;
878 bool db_depth_disable_expclear
:1;
879 bool db_stencil_clear
:1;
880 bool db_stencil_disable_expclear
:1;
881 bool occlusion_queries_disabled
:1;
882 bool generate_mipmap_for_depth
:1;
884 /* Emitted draw state. */
885 bool gs_tri_strip_adj_fix
:1;
888 int last_base_vertex
;
889 int last_start_instance
;
891 int last_sh_base_reg
;
892 int last_primitive_restart_en
;
893 int last_restart_index
;
895 int last_multi_vgt_param
;
897 unsigned last_sc_line_stipple
;
898 unsigned current_vs_state
;
899 unsigned last_vs_state
;
900 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
903 struct r600_resource
*scratch_buffer
;
904 unsigned scratch_waves
;
905 unsigned spi_tmpring_size
;
907 struct r600_resource
*compute_scratch_buffer
;
909 /* Emitted derived tessellation state. */
910 /* Local shader (VS), or HS if LS-HS are merged. */
911 struct si_shader
*last_ls
;
912 struct si_shader_selector
*last_tcs
;
913 int last_num_tcs_input_cp
;
914 int last_tes_sh_base
;
915 bool last_tess_uses_primid
;
916 unsigned last_num_patches
;
917 int last_ls_hs_config
;
921 struct si_saved_cs
*current_saved_cs
;
922 uint64_t dmesg_timestamp
;
923 unsigned apitrace_call_number
;
926 bool need_check_render_feedback
;
927 bool decompression_enabled
;
929 bool vs_writes_viewport_index
;
930 bool vs_disables_clipping_viewport
;
932 /* Precomputed IA_MULTI_VGT_PARAM */
933 union si_vgt_param_key ia_multi_vgt_param_key
;
934 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
936 /* Bindless descriptors. */
937 struct si_descriptors bindless_descriptors
;
938 struct util_idalloc bindless_used_slots
;
939 unsigned num_bindless_descriptors
;
940 bool bindless_descriptors_dirty
;
941 bool graphics_bindless_pointer_dirty
;
942 bool compute_bindless_pointer_dirty
;
944 /* Allocated bindless handles */
945 struct hash_table
*tex_handles
;
946 struct hash_table
*img_handles
;
948 /* Resident bindless handles */
949 struct util_dynarray resident_tex_handles
;
950 struct util_dynarray resident_img_handles
;
952 /* Resident bindless handles which need decompression */
953 struct util_dynarray resident_tex_needs_color_decompress
;
954 struct util_dynarray resident_img_needs_color_decompress
;
955 struct util_dynarray resident_tex_needs_depth_decompress
;
958 bool uses_bindless_samplers
;
959 bool uses_bindless_images
;
961 /* MSAA sample locations.
962 * The first index is the sample index.
963 * The second index is the coordinate: X, Y. */
964 float sample_locations_1x
[1][2];
965 float sample_locations_2x
[2][2];
966 float sample_locations_4x
[4][2];
967 float sample_locations_8x
[8][2];
968 float sample_locations_16x
[16][2];
971 unsigned num_draw_calls
;
972 unsigned num_decompress_calls
;
973 unsigned num_mrt_draw_calls
;
974 unsigned num_prim_restart_calls
;
975 unsigned num_spill_draw_calls
;
976 unsigned num_compute_calls
;
977 unsigned num_spill_compute_calls
;
978 unsigned num_dma_calls
;
979 unsigned num_cp_dma_calls
;
980 unsigned num_vs_flushes
;
981 unsigned num_ps_flushes
;
982 unsigned num_cs_flushes
;
983 unsigned num_cb_cache_flushes
;
984 unsigned num_db_cache_flushes
;
985 unsigned num_L2_invalidates
;
986 unsigned num_L2_writebacks
;
987 unsigned num_resident_handles
;
988 uint64_t num_alloc_tex_transfer_bytes
;
989 unsigned last_tex_ps_draw_ratio
; /* for query */
992 /* Maintain the list of active queries for pausing between IBs. */
993 int num_occlusion_queries
;
994 int num_perfect_occlusion_queries
;
995 struct list_head active_queries
;
996 unsigned num_cs_dw_queries_suspend
;
998 /* Render condition. */
999 struct pipe_query
*render_cond
;
1000 unsigned render_cond_mode
;
1001 bool render_cond_invert
;
1002 bool render_cond_force_off
; /* for u_blitter */
1004 /* Statistics gathering for the DCC enablement heuristic. It can't be
1005 * in si_texture because si_texture can be shared by multiple
1006 * contexts. This is for back buffers only. We shouldn't get too many
1009 * X11 DRI3 rotates among a finite set of back buffers. They should
1010 * all fit in this array. If they don't, separate DCC might never be
1011 * enabled by DCC stat gathering.
1014 struct si_texture
*tex
;
1015 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1016 struct pipe_query
*ps_stats
[3];
1017 /* If all slots are used and another slot is needed,
1018 * the least recently used slot is evicted based on this. */
1019 int64_t last_use_timestamp
;
1023 /* Copy one resource to another using async DMA. */
1024 void (*dma_copy
)(struct pipe_context
*ctx
,
1025 struct pipe_resource
*dst
,
1027 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
1028 struct pipe_resource
*src
,
1030 const struct pipe_box
*src_box
);
1032 struct si_tracked_regs tracked_regs
;
1036 void cik_init_sdma_functions(struct si_context
*sctx
);
1039 enum si_blitter_op
/* bitmask */
1041 SI_SAVE_TEXTURES
= 1,
1042 SI_SAVE_FRAMEBUFFER
= 2,
1043 SI_SAVE_FRAGMENT_STATE
= 4,
1044 SI_DISABLE_RENDER_COND
= 8,
1047 void si_blitter_begin(struct si_context
*sctx
, enum si_blitter_op op
);
1048 void si_blitter_end(struct si_context
*sctx
);
1049 void si_init_blit_functions(struct si_context
*sctx
);
1050 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
);
1051 void si_resource_copy_region(struct pipe_context
*ctx
,
1052 struct pipe_resource
*dst
,
1054 unsigned dstx
, unsigned dsty
, unsigned dstz
,
1055 struct pipe_resource
*src
,
1057 const struct pipe_box
*src_box
);
1058 void si_decompress_dcc(struct si_context
*sctx
, struct si_texture
*tex
);
1059 void si_blit_decompress_depth(struct pipe_context
*ctx
,
1060 struct si_texture
*texture
,
1061 struct si_texture
*staging
,
1062 unsigned first_level
, unsigned last_level
,
1063 unsigned first_layer
, unsigned last_layer
,
1064 unsigned first_sample
, unsigned last_sample
);
1067 bool si_rings_is_buffer_referenced(struct si_context
*sctx
,
1068 struct pb_buffer
*buf
,
1069 enum radeon_bo_usage usage
);
1070 void *si_buffer_map_sync_with_rings(struct si_context
*sctx
,
1071 struct r600_resource
*resource
,
1073 void si_init_resource_fields(struct si_screen
*sscreen
,
1074 struct r600_resource
*res
,
1075 uint64_t size
, unsigned alignment
);
1076 bool si_alloc_resource(struct si_screen
*sscreen
,
1077 struct r600_resource
*res
);
1078 struct pipe_resource
*pipe_aligned_buffer_create(struct pipe_screen
*screen
,
1079 unsigned flags
, unsigned usage
,
1080 unsigned size
, unsigned alignment
);
1081 struct r600_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
,
1082 unsigned flags
, unsigned usage
,
1083 unsigned size
, unsigned alignment
);
1084 void si_replace_buffer_storage(struct pipe_context
*ctx
,
1085 struct pipe_resource
*dst
,
1086 struct pipe_resource
*src
);
1087 void si_init_screen_buffer_functions(struct si_screen
*sscreen
);
1088 void si_init_buffer_functions(struct si_context
*sctx
);
1091 enum pipe_format
si_simplify_cb_format(enum pipe_format format
);
1092 bool vi_alpha_is_on_msb(enum pipe_format format
);
1093 void vi_dcc_clear_level(struct si_context
*sctx
,
1094 struct si_texture
*tex
,
1095 unsigned level
, unsigned clear_value
);
1096 void si_init_clear_functions(struct si_context
*sctx
);
1099 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1100 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1101 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1102 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1103 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1104 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1105 SI_CPDMA_SKIP_SYNC_AFTER | \
1106 SI_CPDMA_SKIP_SYNC_BEFORE | \
1107 SI_CPDMA_SKIP_GFX_SYNC | \
1108 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1110 enum si_cache_policy
{
1112 L2_STREAM
, /* same as SLC=1 */
1113 L2_LRU
, /* same as SLC=0 */
1117 SI_COHERENCY_NONE
, /* no cache flushes needed */
1118 SI_COHERENCY_SHADER
,
1119 SI_COHERENCY_CB_META
,
1122 void si_cp_dma_wait_for_idle(struct si_context
*sctx
);
1123 void si_cp_dma_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1124 uint64_t offset
, uint64_t size
, unsigned value
,
1125 enum si_coherency coher
,
1126 enum si_cache_policy cache_policy
);
1127 void si_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1128 uint64_t offset
, uint64_t size
, unsigned value
,
1129 enum si_coherency coher
);
1130 void si_cp_dma_copy_buffer(struct si_context
*sctx
,
1131 struct pipe_resource
*dst
, struct pipe_resource
*src
,
1132 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
1133 unsigned user_flags
, enum si_coherency coher
,
1134 enum si_cache_policy cache_policy
);
1135 void si_copy_buffer(struct si_context
*sctx
,
1136 struct pipe_resource
*dst
, struct pipe_resource
*src
,
1137 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
);
1138 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
1139 uint64_t offset
, unsigned size
);
1140 void cik_emit_prefetch_L2(struct si_context
*sctx
, bool vertex_stage_only
);
1141 void si_init_cp_dma_functions(struct si_context
*sctx
);
1144 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_cmdbuf
*cs
,
1145 struct radeon_saved_cs
*saved
, bool get_buffer_list
);
1146 void si_clear_saved_cs(struct radeon_saved_cs
*saved
);
1147 void si_destroy_saved_cs(struct si_saved_cs
*scs
);
1148 void si_auto_log_cs(void *data
, struct u_log_context
*log
);
1149 void si_log_hw_flush(struct si_context
*sctx
);
1150 void si_log_draw_state(struct si_context
*sctx
, struct u_log_context
*log
);
1151 void si_log_compute_state(struct si_context
*sctx
, struct u_log_context
*log
);
1152 void si_init_debug_functions(struct si_context
*sctx
);
1153 void si_check_vm_faults(struct si_context
*sctx
,
1154 struct radeon_saved_cs
*saved
, enum ring_type ring
);
1155 bool si_replace_shader(unsigned num
, struct ac_shader_binary
*binary
);
1158 void si_init_dma_functions(struct si_context
*sctx
);
1161 void si_dma_emit_timestamp(struct si_context
*sctx
, struct r600_resource
*dst
,
1163 void si_sdma_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1164 uint64_t offset
, uint64_t size
, unsigned clear_value
);
1165 void si_need_dma_space(struct si_context
*ctx
, unsigned num_dw
,
1166 struct r600_resource
*dst
, struct r600_resource
*src
);
1167 void si_flush_dma_cs(struct si_context
*ctx
, unsigned flags
,
1168 struct pipe_fence_handle
**fence
);
1169 void si_screen_clear_buffer(struct si_screen
*sscreen
, struct pipe_resource
*dst
,
1170 uint64_t offset
, uint64_t size
, unsigned value
);
1173 void si_gfx_write_event_eop(struct si_context
*ctx
,
1174 unsigned event
, unsigned event_flags
,
1176 struct r600_resource
*buf
, uint64_t va
,
1177 uint32_t new_fence
, unsigned query_type
);
1178 unsigned si_gfx_write_fence_dwords(struct si_screen
*screen
);
1179 void si_gfx_wait_fence(struct si_context
*ctx
,
1180 uint64_t va
, uint32_t ref
, uint32_t mask
);
1181 void si_init_fence_functions(struct si_context
*ctx
);
1182 void si_init_screen_fence_functions(struct si_screen
*screen
);
1183 struct pipe_fence_handle
*si_create_fence(struct pipe_context
*ctx
,
1184 struct tc_unflushed_batch_token
*tc_token
);
1187 void si_init_screen_get_functions(struct si_screen
*sscreen
);
1190 void si_flush_gfx_cs(struct si_context
*ctx
, unsigned flags
,
1191 struct pipe_fence_handle
**fence
);
1192 void si_begin_new_gfx_cs(struct si_context
*ctx
);
1193 void si_need_gfx_cs_space(struct si_context
*ctx
);
1195 /* r600_gpu_load.c */
1196 void si_gpu_load_kill_thread(struct si_screen
*sscreen
);
1197 uint64_t si_begin_counter(struct si_screen
*sscreen
, unsigned type
);
1198 unsigned si_end_counter(struct si_screen
*sscreen
, unsigned type
,
1202 void si_init_compute_functions(struct si_context
*sctx
);
1204 /* r600_perfcounters.c */
1205 void si_perfcounters_destroy(struct si_screen
*sscreen
);
1207 /* si_perfcounters.c */
1208 void si_init_perfcounters(struct si_screen
*screen
);
1211 bool si_check_device_reset(struct si_context
*sctx
);
1214 void si_init_screen_query_functions(struct si_screen
*sscreen
);
1215 void si_init_query_functions(struct si_context
*sctx
);
1216 void si_suspend_queries(struct si_context
*sctx
);
1217 void si_resume_queries(struct si_context
*sctx
);
1219 /* si_shaderlib_tgsi.c */
1220 void *si_get_blitter_vs(struct si_context
*sctx
, enum blitter_attrib_type type
,
1221 unsigned num_layers
);
1222 void *si_create_fixed_func_tcs(struct si_context
*sctx
);
1223 void *si_create_dma_compute_shader(struct pipe_context
*ctx
,
1224 unsigned num_dwords_per_thread
,
1225 bool dst_stream_cache_policy
, bool is_copy
);
1226 void *si_create_query_result_cs(struct si_context
*sctx
);
1229 void si_test_dma(struct si_screen
*sscreen
);
1231 /* si_test_clearbuffer.c */
1232 void si_test_dma_perf(struct si_screen
*sscreen
);
1235 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
1236 const struct pipe_video_codec
*templ
);
1238 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
1239 const struct pipe_video_buffer
*tmpl
);
1242 void si_update_vs_viewport_state(struct si_context
*ctx
);
1243 void si_init_viewport_functions(struct si_context
*ctx
);
1246 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
1247 struct si_texture
*dst
,
1248 unsigned dst_level
, unsigned dstx
,
1249 unsigned dsty
, unsigned dstz
,
1250 struct si_texture
*src
,
1252 const struct pipe_box
*src_box
);
1253 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
1254 struct si_texture
*tex
);
1255 void si_texture_discard_cmask(struct si_screen
*sscreen
,
1256 struct si_texture
*tex
);
1257 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1258 struct pipe_resource
*texture
,
1259 struct si_texture
**staging
);
1260 void si_print_texture_info(struct si_screen
*sscreen
,
1261 struct si_texture
*tex
, struct u_log_context
*log
);
1262 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1263 const struct pipe_resource
*templ
);
1264 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1265 enum pipe_format format2
);
1266 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1268 enum pipe_format view_format
);
1269 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
1270 struct pipe_resource
*tex
,
1272 enum pipe_format view_format
);
1273 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1274 struct pipe_resource
*texture
,
1275 const struct pipe_surface
*templ
,
1276 unsigned width0
, unsigned height0
,
1277 unsigned width
, unsigned height
);
1278 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
1279 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
1280 struct si_texture
*tex
);
1281 void vi_separate_dcc_start_query(struct si_context
*sctx
,
1282 struct si_texture
*tex
);
1283 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
1284 struct si_texture
*tex
);
1285 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
1286 struct si_texture
*tex
);
1287 bool si_texture_disable_dcc(struct si_context
*sctx
,
1288 struct si_texture
*tex
);
1289 void si_init_screen_texture_functions(struct si_screen
*sscreen
);
1290 void si_init_context_texture_functions(struct si_context
*sctx
);
1297 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
1299 return (struct r600_resource
*)r
;
1303 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
1305 pipe_resource_reference((struct pipe_resource
**)ptr
,
1306 (struct pipe_resource
*)res
);
1310 si_texture_reference(struct si_texture
**ptr
, struct si_texture
*res
)
1312 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->buffer
.b
.b
);
1316 vi_dcc_enabled(struct si_texture
*tex
, unsigned level
)
1318 return tex
->dcc_offset
&& level
< tex
->surface
.num_dcc_levels
;
1321 static inline unsigned
1322 si_tile_mode_index(struct si_texture
*tex
, unsigned level
, bool stencil
)
1325 return tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
1327 return tex
->surface
.u
.legacy
.tiling_index
[level
];
1331 si_context_add_resource_size(struct si_context
*sctx
, struct pipe_resource
*r
)
1334 /* Add memory usage for need_gfx_cs_space */
1335 sctx
->vram
+= r600_resource(r
)->vram_usage
;
1336 sctx
->gtt
+= r600_resource(r
)->gart_usage
;
1341 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
1343 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
1346 static inline unsigned
1347 si_get_atom_bit(struct si_context
*sctx
, struct si_atom
*atom
)
1349 return 1 << (atom
- sctx
->atoms
.array
);
1353 si_set_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
, bool dirty
)
1355 unsigned bit
= si_get_atom_bit(sctx
, atom
);
1358 sctx
->dirty_atoms
|= bit
;
1360 sctx
->dirty_atoms
&= ~bit
;
1364 si_is_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1366 return (sctx
->dirty_atoms
& si_get_atom_bit(sctx
, atom
)) != 0;
1370 si_mark_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1372 si_set_atom_dirty(sctx
, atom
, true);
1375 static inline struct si_shader_ctx_state
*si_get_vs(struct si_context
*sctx
)
1377 if (sctx
->gs_shader
.cso
)
1378 return &sctx
->gs_shader
;
1379 if (sctx
->tes_shader
.cso
)
1380 return &sctx
->tes_shader
;
1382 return &sctx
->vs_shader
;
1385 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
1387 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1389 return vs
->cso
? &vs
->cso
->info
: NULL
;
1392 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
1394 if (sctx
->gs_shader
.cso
)
1395 return sctx
->gs_shader
.cso
->gs_copy_shader
;
1397 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1398 return vs
->current
? vs
->current
: NULL
;
1401 static inline bool si_can_dump_shader(struct si_screen
*sscreen
,
1404 return sscreen
->debug_flags
& (1 << processor
);
1407 static inline bool si_get_strmout_en(struct si_context
*sctx
)
1409 return sctx
->streamout
.streamout_enabled
||
1410 sctx
->streamout
.prims_gen_query_enabled
;
1413 static inline unsigned
1414 si_optimal_tcc_alignment(struct si_context
*sctx
, unsigned upload_size
)
1416 unsigned alignment
, tcc_cache_line_size
;
1418 /* If the upload size is less than the cache line size (e.g. 16, 32),
1419 * the whole thing will fit into a cache line if we align it to its size.
1420 * The idea is that multiple small uploads can share a cache line.
1421 * If the upload size is greater, align it to the cache line size.
1423 alignment
= util_next_power_of_two(upload_size
);
1424 tcc_cache_line_size
= sctx
->screen
->info
.tcc_cache_line_size
;
1425 return MIN2(alignment
, tcc_cache_line_size
);
1429 si_saved_cs_reference(struct si_saved_cs
**dst
, struct si_saved_cs
*src
)
1431 if (pipe_reference(&(*dst
)->reference
, &src
->reference
))
1432 si_destroy_saved_cs(*dst
);
1438 si_make_CB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1439 bool shaders_read_metadata
)
1441 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
|
1442 SI_CONTEXT_INV_VMEM_L1
;
1444 if (sctx
->chip_class
>= GFX9
) {
1445 /* Single-sample color is coherent with shaders on GFX9, but
1446 * L2 metadata must be flushed if shaders read metadata.
1449 if (num_samples
>= 2)
1450 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1451 else if (shaders_read_metadata
)
1452 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1455 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1460 si_make_DB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1461 bool include_stencil
, bool shaders_read_metadata
)
1463 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB
|
1464 SI_CONTEXT_INV_VMEM_L1
;
1466 if (sctx
->chip_class
>= GFX9
) {
1467 /* Single-sample depth (not stencil) is coherent with shaders
1468 * on GFX9, but L2 metadata must be flushed if shaders read
1471 if (num_samples
>= 2 || include_stencil
)
1472 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1473 else if (shaders_read_metadata
)
1474 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1477 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1482 si_can_sample_zs(struct si_texture
*tex
, bool stencil_sampler
)
1484 return (stencil_sampler
&& tex
->can_sample_s
) ||
1485 (!stencil_sampler
&& tex
->can_sample_z
);
1489 si_htile_enabled(struct si_texture
*tex
, unsigned level
)
1491 return tex
->htile_offset
&& level
== 0;
1495 vi_tc_compat_htile_enabled(struct si_texture
*tex
, unsigned level
)
1497 assert(!tex
->tc_compatible_htile
|| tex
->htile_offset
);
1498 return tex
->tc_compatible_htile
&& level
== 0;
1501 static inline unsigned si_get_ps_iter_samples(struct si_context
*sctx
)
1503 if (sctx
->ps_uses_fbfetch
)
1504 return sctx
->framebuffer
.nr_color_samples
;
1506 return MIN2(sctx
->ps_iter_samples
, sctx
->framebuffer
.nr_color_samples
);
1509 static inline unsigned si_get_total_colormask(struct si_context
*sctx
)
1511 if (sctx
->queued
.named
.rasterizer
->rasterizer_discard
)
1514 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1518 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
1519 sctx
->queued
.named
.blend
->cb_target_mask
;
1521 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
1522 colormask
&= ps
->colors_written_4bit
;
1523 else if (!ps
->colors_written_4bit
)
1524 colormask
= 0; /* color0 writes all cbufs, but it's not written */
1529 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1530 (1 << PIPE_PRIM_LINE_LOOP) | \
1531 (1 << PIPE_PRIM_LINE_STRIP) | \
1532 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1533 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1535 static inline bool util_prim_is_lines(unsigned prim
)
1537 return ((1 << prim
) & UTIL_ALL_PRIM_LINE_MODES
) != 0;
1540 static inline bool util_prim_is_points_or_lines(unsigned prim
)
1542 return ((1 << prim
) & (UTIL_ALL_PRIM_LINE_MODES
|
1543 (1 << PIPE_PRIM_POINTS
))) != 0;
1547 * Return true if there is enough memory in VRAM and GTT for the buffers
1550 * \param vram VRAM memory size not added to the buffer list yet
1551 * \param gtt GTT memory size not added to the buffer list yet
1554 radeon_cs_memory_below_limit(struct si_screen
*screen
,
1555 struct radeon_cmdbuf
*cs
,
1556 uint64_t vram
, uint64_t gtt
)
1558 vram
+= cs
->used_vram
;
1559 gtt
+= cs
->used_gart
;
1561 /* Anything that goes above the VRAM size should go to GTT. */
1562 if (vram
> screen
->info
.vram_size
)
1563 gtt
+= vram
- screen
->info
.vram_size
;
1565 /* Now we just need to check if we have enough GTT. */
1566 return gtt
< screen
->info
.gart_size
* 0.7;
1570 * Add a buffer to the buffer list for the given command stream (CS).
1572 * All buffers used by a CS must be added to the list. This tells the kernel
1573 * driver which buffers are used by GPU commands. Other buffers can
1574 * be swapped out (not accessible) during execution.
1576 * The buffer list becomes empty after every context flush and must be
1579 static inline void radeon_add_to_buffer_list(struct si_context
*sctx
,
1580 struct radeon_cmdbuf
*cs
,
1581 struct r600_resource
*rbo
,
1582 enum radeon_bo_usage usage
,
1583 enum radeon_bo_priority priority
)
1586 sctx
->ws
->cs_add_buffer(
1588 (enum radeon_bo_usage
)(usage
| RADEON_USAGE_SYNCHRONIZED
),
1589 rbo
->domains
, priority
);
1593 * Same as above, but also checks memory usage and flushes the context
1596 * When this SHOULD NOT be used:
1598 * - if si_context_add_resource_size has been called for the buffer
1599 * followed by *_need_cs_space for checking the memory usage
1601 * - if si_need_dma_space has been called for the buffer
1603 * - when emitting state packets and draw packets (because preceding packets
1604 * can't be re-emitted at that point)
1606 * - if shader resource "enabled_mask" is not up-to-date or there is
1607 * a different constraint disallowing a context flush
1610 radeon_add_to_gfx_buffer_list_check_mem(struct si_context
*sctx
,
1611 struct r600_resource
*rbo
,
1612 enum radeon_bo_usage usage
,
1613 enum radeon_bo_priority priority
,
1617 !radeon_cs_memory_below_limit(sctx
->screen
, sctx
->gfx_cs
,
1618 sctx
->vram
+ rbo
->vram_usage
,
1619 sctx
->gtt
+ rbo
->gart_usage
))
1620 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1622 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, rbo
, usage
, priority
);
1625 #define PRINT_ERR(fmt, args...) \
1626 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)