src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef SI_PIPE_H
  24 #define SI_PIPE_H
  25
  26 #include "si_shader.h"
  27
  28 #include "util/u_dynarray.h"
  29 #include "util/u_idalloc.h"
  30
  31 #ifdef PIPE_ARCH_BIG_ENDIAN
  32 #define SI_BIG_ENDIAN 1
  33 #else
  34 #define SI_BIG_ENDIAN 0
  35 #endif
  36
  37 #define ATI_VENDOR_ID 0x1002
  38
  39 #define SI_NOT_QUERY            0xffffffff
  40
  41 /* The base vertex and primitive restart can be any number, but we must pick
  42  * one which will mean "unknown" for the purpose of state tracking and
  43  * the number shouldn't be a commonly-used one. */
  44 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  45 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  46 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  47 #define SI_GS_PER_ES 128
  48 /* Alignment for optimal CP DMA performance. */
  49 #define SI_CPDMA_ALIGNMENT      32
  50
  51 /* Pipeline & streamout query controls. */
  52 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
  53 #define SI_CONTEXT_STOP_PIPELINE_STATS  (1 << 1)
  54 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
  55 /* Instruction cache. */
  56 #define SI_CONTEXT_INV_ICACHE           (1 << 3)
  57 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  58 #define SI_CONTEXT_INV_SMEM_L1          (1 << 4)
  59 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  60 #define SI_CONTEXT_INV_VMEM_L1          (1 << 5)
  61 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  62 #define SI_CONTEXT_INV_GLOBAL_L2        (1 << 6)
  63 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  64  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
  65 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2  (1 << 7)
  66 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
  67  * a CB or DB flush. */
  68 #define SI_CONTEXT_INV_L2_METADATA      (1 << 8)
  69 /* Framebuffer caches. */
  70 #define SI_CONTEXT_FLUSH_AND_INV_DB     (1 << 9)
  71 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
  72 #define SI_CONTEXT_FLUSH_AND_INV_CB     (1 << 11)
  73 /* Engine synchronization. */
  74 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (1 << 12)
  75 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (1 << 13)
  76 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (1 << 14)
  77 #define SI_CONTEXT_VGT_FLUSH            (1 << 15)
  78 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (1 << 16)
  79
  80 #define SI_PREFETCH_VBO_DESCRIPTORS     (1 << 0)
  81 #define SI_PREFETCH_LS                  (1 << 1)
  82 #define SI_PREFETCH_HS                  (1 << 2)
  83 #define SI_PREFETCH_ES                  (1 << 3)
  84 #define SI_PREFETCH_GS                  (1 << 4)
  85 #define SI_PREFETCH_VS                  (1 << 5)
  86 #define SI_PREFETCH_PS                  (1 << 6)
  87
  88 #define SI_MAX_BORDER_COLORS    4096
  89 #define SI_MAX_VIEWPORTS        16
  90 #define SIX_BITS                0x3F
  91
  92 struct si_compute;
  93 struct hash_table;
  94 struct u_suballocator;
  95
  96 struct si_screen {
  97         struct pipe_screen              b;
  98         struct radeon_winsys            *ws;
  99         struct disk_cache               *disk_shader_cache;
 100
 101         struct radeon_info              info;
 102         uint64_t                        debug_flags;
 103         char                            renderer_string[100];
 104
 105         unsigned                        gs_table_depth;
 106         unsigned                        tess_offchip_block_dw_size;
 107         bool                            has_clear_state;
 108         bool                            has_distributed_tess;
 109         bool                            has_draw_indirect_multi;
 110         bool                            has_out_of_order_rast;
 111         bool                            assume_no_z_fights;
 112         bool                            commutative_blend_add;
 113         bool                            clear_db_cache_before_clear;
 114         bool                            has_msaa_sample_loc_bug;
 115         bool                            has_ls_vgpr_init_bug;
 116         bool                            dpbb_allowed;
 117         bool                            dfsm_allowed;
 118         bool                            llvm_has_working_vgpr_indexing;
 119
 120         /* Whether shaders are monolithic (1-part) or separate (3-part). */
 121         bool                            use_monolithic_shaders;
 122         bool                            record_llvm_ir;
 123         bool                            has_rbplus;     /* if RB+ registers exist */
 124         bool                            rbplus_allowed; /* if RB+ is allowed */
 125         bool                            dcc_msaa_allowed;
 126         bool                            cpdma_prefetch_writes_memory;
 127
 128         struct slab_parent_pool         pool_transfers;
 129
 130         /* Texture filter settings. */
 131         int                             force_aniso; /* -1 = disabled */
 132
 133         /* Auxiliary context. Mainly used to initialize resources.
 134          * It must be locked prior to using and flushed before unlocking. */
 135         struct pipe_context             *aux_context;
 136         mtx_t                           aux_context_lock;
 137
 138         /* This must be in the screen, because UE4 uses one context for
 139          * compilation and another one for rendering.
 140          */
 141         unsigned                        num_compilations;
 142         /* Along with ST_DEBUG=precompile, this should show if applications
 143          * are loading shaders on demand. This is a monotonic counter.
 144          */
 145         unsigned                        num_shaders_created;
 146         unsigned                        num_shader_cache_hits;
 147
 148         /* GPU load thread. */
 149         mtx_t                           gpu_load_mutex;
 150         thrd_t                          gpu_load_thread;
 151         union r600_mmio_counters        mmio_counters;
 152         volatile unsigned               gpu_load_stop_thread; /* bool */
 153
 154         /* Performance counters. */
 155         struct r600_perfcounters        *perfcounters;
 156
 157         /* If pipe_screen wants to recompute and re-emit the framebuffer,
 158          * sampler, and image states of all contexts, it should atomically
 159          * increment this.
 160          *
 161          * Each context will compare this with its own last known value of
 162          * the counter before drawing and re-emit the states accordingly.
 163          */
 164         unsigned                        dirty_tex_counter;
 165
 166         /* Atomically increment this counter when an existing texture's
 167          * metadata is enabled or disabled in a way that requires changing
 168          * contexts' compressed texture binding masks.
 169          */
 170         unsigned                        compressed_colortex_counter;
 171
 172         struct {
 173                 /* Context flags to set so that all writes from earlier jobs
 174                  * in the CP are seen by L2 clients.
 175                  */
 176                 unsigned cp_to_L2;
 177
 178                 /* Context flags to set so that all writes from earlier jobs
 179                  * that end in L2 are seen by CP.
 180                  */
 181                 unsigned L2_to_cp;
 182         } barrier_flags;
 183
 184         mtx_t                   shader_parts_mutex;
 185         struct si_shader_part           *vs_prologs;
 186         struct si_shader_part           *tcs_epilogs;
 187         struct si_shader_part           *gs_prologs;
 188         struct si_shader_part           *ps_prologs;
 189         struct si_shader_part           *ps_epilogs;
 190
 191         /* Shader cache in memory.
 192          *
 193          * Design & limitations:
 194          * - The shader cache is per screen (= per process), never saved to
 195          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 196          * - It can only be used with one-variant-per-shader support, in which
 197          *   case only the main (typically middle) part of shaders is cached.
 198          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 199          *   variants of VS and TES are cached, so LS and ES aren't.
 200          * - GS and CS aren't cached, but it's certainly possible to cache
 201          *   those as well.
 202          */
 203         mtx_t                   shader_cache_mutex;
 204         struct hash_table               *shader_cache;
 205
 206         /* Shader compiler queue for multithreaded compilation. */
 207         struct util_queue               shader_compiler_queue;
 208         /* Use at most 3 normal compiler threads on quadcore and better.
 209          * Hyperthreaded CPUs report the number of threads, but we want
 210          * the number of cores. */
 211         LLVMTargetMachineRef            tm[3]; /* used by the queue only */
 212
 213         struct util_queue               shader_compiler_queue_low_priority;
 214         /* Use at most 2 low priority threads on quadcore and better.
 215          * We want to minimize the impact on multithreaded Mesa. */
 216         LLVMTargetMachineRef            tm_low_priority[2]; /* at most 2 threads */
 217 };
 218
 219 struct si_blend_color {
 220         struct r600_atom                atom;
 221         struct pipe_blend_color         state;
 222         bool                            any_nonzeros;
 223 };
 224
 225 struct si_sampler_view {
 226         struct pipe_sampler_view        base;
 227         /* [0..7] = image descriptor
 228          * [4..7] = buffer descriptor */
 229         uint32_t                        state[8];
 230         uint32_t                        fmask_state[8];
 231         const struct legacy_surf_level  *base_level_info;
 232         ubyte                           base_level;
 233         ubyte                           block_width;
 234         bool is_stencil_sampler;
 235         bool is_integer;
 236         bool dcc_incompatible;
 237 };
 238
 239 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
 240
 241 struct si_sampler_state {
 242 #ifdef DEBUG
 243         unsigned                        magic;
 244 #endif
 245         uint32_t                        val[4];
 246         uint32_t                        integer_val[4];
 247         uint32_t                        upgraded_depth_val[4];
 248 };
 249
 250 struct si_cs_shader_state {
 251         struct si_compute               *program;
 252         struct si_compute               *emitted_program;
 253         unsigned                        offset;
 254         bool                            initialized;
 255         bool                            uses_scratch;
 256 };
 257
 258 struct si_samplers {
 259         struct pipe_sampler_view        *views[SI_NUM_SAMPLERS];
 260         struct si_sampler_state         *sampler_states[SI_NUM_SAMPLERS];
 261
 262         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 263         unsigned                        enabled_mask;
 264         uint32_t                        needs_depth_decompress_mask;
 265         uint32_t                        needs_color_decompress_mask;
 266 };
 267
 268 struct si_images {
 269         struct pipe_image_view          views[SI_NUM_IMAGES];
 270         uint32_t                        needs_color_decompress_mask;
 271         unsigned                        enabled_mask;
 272 };
 273
 274 struct si_framebuffer {
 275         struct r600_atom                atom;
 276         struct pipe_framebuffer_state   state;
 277         unsigned                        colorbuf_enabled_4bit;
 278         unsigned                        spi_shader_col_format;
 279         unsigned                        spi_shader_col_format_alpha;
 280         unsigned                        spi_shader_col_format_blend;
 281         unsigned                        spi_shader_col_format_blend_alpha;
 282         ubyte                           nr_samples:5; /* at most 16xAA */
 283         ubyte                           log_samples:3; /* at most 4 = 16xAA */
 284         ubyte                           compressed_cb_mask;
 285         ubyte                           color_is_int8;
 286         ubyte                           color_is_int10;
 287         ubyte                           dirty_cbufs;
 288         bool                            dirty_zsbuf;
 289         bool                            any_dst_linear;
 290         bool                            CB_has_shader_readable_metadata;
 291         bool                            DB_has_shader_readable_metadata;
 292 };
 293
 294 struct si_signed_scissor {
 295         int minx;
 296         int miny;
 297         int maxx;
 298         int maxy;
 299 };
 300
 301 struct si_scissors {
 302         struct r600_atom                atom;
 303         unsigned                        dirty_mask;
 304         struct pipe_scissor_state       states[SI_MAX_VIEWPORTS];
 305 };
 306
 307 struct si_viewports {
 308         struct r600_atom                atom;
 309         unsigned                        dirty_mask;
 310         unsigned                        depth_range_dirty_mask;
 311         struct pipe_viewport_state      states[SI_MAX_VIEWPORTS];
 312         struct si_signed_scissor        as_scissor[SI_MAX_VIEWPORTS];
 313 };
 314
 315 struct si_clip_state {
 316         struct r600_atom                atom;
 317         struct pipe_clip_state          state;
 318         bool                            any_nonzeros;
 319 };
 320
 321 struct si_sample_locs {
 322         struct r600_atom        atom;
 323         unsigned                nr_samples;
 324 };
 325
 326 struct si_sample_mask {
 327         struct r600_atom        atom;
 328         uint16_t                sample_mask;
 329 };
 330
 331 struct si_streamout_target {
 332         struct pipe_stream_output_target b;
 333
 334         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 335         struct r600_resource    *buf_filled_size;
 336         unsigned                buf_filled_size_offset;
 337         bool                    buf_filled_size_valid;
 338
 339         unsigned                stride_in_dw;
 340 };
 341
 342 struct si_streamout {
 343         struct r600_atom                begin_atom;
 344         bool                            begin_emitted;
 345
 346         unsigned                        enabled_mask;
 347         unsigned                        num_targets;
 348         struct si_streamout_target      *targets[PIPE_MAX_SO_BUFFERS];
 349
 350         unsigned                        append_bitmask;
 351         bool                            suspended;
 352
 353         /* External state which comes from the vertex shader,
 354          * it must be set explicitly when binding a shader. */
 355         uint16_t                        *stride_in_dw;
 356         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 357
 358         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 359         unsigned                        hw_enabled_mask;
 360
 361         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 362         struct r600_atom                enable_atom;
 363         bool                            streamout_enabled;
 364         bool                            prims_gen_query_enabled;
 365         int                             num_prims_gen_queries;
 366 };
 367
 368 /* A shader state consists of the shader selector, which is a constant state
 369  * object shared by multiple contexts and shouldn't be modified, and
 370  * the current shader variant selected for this context.
 371  */
 372 struct si_shader_ctx_state {
 373         struct si_shader_selector       *cso;
 374         struct si_shader                *current;
 375 };
 376
 377 #define SI_NUM_VGT_PARAM_KEY_BITS 12
 378 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
 379
 380 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
 381  * Some fields are set by state-change calls, most are set by draw_vbo.
 382  */
 383 union si_vgt_param_key {
 384         struct {
 385                 unsigned prim:4;
 386                 unsigned uses_instancing:1;
 387                 unsigned multi_instances_smaller_than_primgroup:1;
 388                 unsigned primitive_restart:1;
 389                 unsigned count_from_stream_output:1;
 390                 unsigned line_stipple_enabled:1;
 391                 unsigned uses_tess:1;
 392                 unsigned tess_uses_prim_id:1;
 393                 unsigned uses_gs:1;
 394                 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
 395         } u;
 396         uint32_t index;
 397 };
 398
 399 struct si_texture_handle
 400 {
 401         unsigned                        desc_slot;
 402         bool                            desc_dirty;
 403         struct pipe_sampler_view        *view;
 404         struct si_sampler_state         sstate;
 405 };
 406
 407 struct si_image_handle
 408 {
 409         unsigned                        desc_slot;
 410         bool                            desc_dirty;
 411         struct pipe_image_view          view;
 412 };
 413
 414 struct si_saved_cs {
 415         struct pipe_reference   reference;
 416         struct si_context       *ctx;
 417         struct radeon_saved_cs  gfx;
 418         struct r600_resource    *trace_buf;
 419         unsigned                trace_id;
 420
 421         unsigned                gfx_last_dw;
 422         bool                    flushed;
 423         int64_t                 time_flush;
 424 };
 425
 426 struct si_context {
 427         struct r600_common_context      b;
 428         struct blitter_context          *blitter;
 429         void                            *custom_dsa_flush;
 430         void                            *custom_blend_resolve;
 431         void                            *custom_blend_fmask_decompress;
 432         void                            *custom_blend_eliminate_fastclear;
 433         void                            *custom_blend_dcc_decompress;
 434         void                            *vs_blit_pos;
 435         void                            *vs_blit_pos_layered;
 436         void                            *vs_blit_color;
 437         void                            *vs_blit_color_layered;
 438         void                            *vs_blit_texcoord;
 439         struct si_screen                *screen;
 440         struct pipe_debug_callback      debug;
 441         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 442         struct si_shader_ctx_state      fixed_func_tcs_shader;
 443         struct r600_resource            *wait_mem_scratch;
 444         unsigned                        wait_mem_number;
 445         uint16_t                        prefetch_L2_mask;
 446
 447         bool                            gfx_flush_in_progress:1;
 448         bool                            compute_is_busy:1;
 449
 450         /* Atoms (direct states). */
 451         union si_state_atoms            atoms;
 452         unsigned                        dirty_atoms; /* mask */
 453         /* PM4 states (precomputed immutable states) */
 454         unsigned                        dirty_states;
 455         union si_state                  queued;
 456         union si_state                  emitted;
 457
 458         /* Atom declarations. */
 459         struct si_framebuffer           framebuffer;
 460         struct si_sample_locs           msaa_sample_locs;
 461         struct r600_atom                db_render_state;
 462         struct r600_atom                dpbb_state;
 463         struct r600_atom                msaa_config;
 464         struct si_sample_mask           sample_mask;
 465         struct r600_atom                cb_render_state;
 466         unsigned                        last_cb_target_mask;
 467         struct si_blend_color           blend_color;
 468         struct r600_atom                clip_regs;
 469         struct si_clip_state            clip_state;
 470         struct si_shader_data           shader_pointers;
 471         struct si_stencil_ref           stencil_ref;
 472         struct r600_atom                spi_map;
 473         struct si_scissors              scissors;
 474         struct si_streamout             streamout;
 475         struct si_viewports             viewports;
 476
 477         /* Precomputed states. */
 478         struct si_pm4_state             *init_config;
 479         struct si_pm4_state             *init_config_gs_rings;
 480         bool                            init_config_has_vgt_flush;
 481         struct si_pm4_state             *vgt_shader_config[4];
 482
 483         /* shaders */
 484         struct si_shader_ctx_state      ps_shader;
 485         struct si_shader_ctx_state      gs_shader;
 486         struct si_shader_ctx_state      vs_shader;
 487         struct si_shader_ctx_state      tcs_shader;
 488         struct si_shader_ctx_state      tes_shader;
 489         struct si_cs_shader_state       cs_shader_state;
 490
 491         /* shader information */
 492         struct si_vertex_elements       *vertex_elements;
 493         unsigned                        sprite_coord_enable;
 494         bool                            flatshade;
 495         bool                            do_update_shaders;
 496
 497         /* shader descriptors */
 498         struct si_descriptors           vertex_buffers;
 499         struct si_descriptors           descriptors[SI_NUM_DESCS];
 500         unsigned                        descriptors_dirty;
 501         unsigned                        shader_pointers_dirty;
 502         unsigned                        shader_needs_decompress_mask;
 503         struct si_buffer_resources      rw_buffers;
 504         struct si_buffer_resources      const_and_shader_buffers[SI_NUM_SHADERS];
 505         struct si_samplers              samplers[SI_NUM_SHADERS];
 506         struct si_images                images[SI_NUM_SHADERS];
 507
 508         /* other shader resources */
 509         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 510         struct pipe_resource            *esgs_ring;
 511         struct pipe_resource            *gsvs_ring;
 512         struct pipe_resource            *tf_ring;
 513         struct pipe_resource            *tess_offchip_ring;
 514         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 515         struct r600_resource            *border_color_buffer;
 516         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 517         unsigned                        border_color_count;
 518         unsigned                        num_vs_blit_sgprs;
 519         uint32_t                        vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
 520
 521         /* Vertex and index buffers. */
 522         bool                            vertex_buffers_dirty;
 523         bool                            vertex_buffer_pointer_dirty;
 524         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 525
 526         /* MSAA config state. */
 527         int                             ps_iter_samples;
 528         bool                            smoothing_enabled;
 529
 530         /* DB render state. */
 531         unsigned                ps_db_shader_control;
 532         unsigned                dbcb_copy_sample;
 533         bool                    dbcb_depth_copy_enabled:1;
 534         bool                    dbcb_stencil_copy_enabled:1;
 535         bool                    db_flush_depth_inplace:1;
 536         bool                    db_flush_stencil_inplace:1;
 537         bool                    db_depth_clear:1;
 538         bool                    db_depth_disable_expclear:1;
 539         bool                    db_stencil_clear:1;
 540         bool                    db_stencil_disable_expclear:1;
 541         bool                    occlusion_queries_disabled:1;
 542         bool                    generate_mipmap_for_depth:1;
 543
 544         /* Emitted draw state. */
 545         bool                    gs_tri_strip_adj_fix:1;
 546         bool                    ls_vgpr_fix:1;
 547         int                     last_index_size;
 548         int                     last_base_vertex;
 549         int                     last_start_instance;
 550         int                     last_drawid;
 551         int                     last_sh_base_reg;
 552         int                     last_primitive_restart_en;
 553         int                     last_restart_index;
 554         int                     last_gs_out_prim;
 555         int                     last_prim;
 556         int                     last_multi_vgt_param;
 557         int                     last_rast_prim;
 558         unsigned                last_sc_line_stipple;
 559         unsigned                current_vs_state;
 560         unsigned                last_vs_state;
 561         enum pipe_prim_type     current_rast_prim; /* primitive type after TES, GS */
 562
 563         /* Scratch buffer */
 564         struct r600_atom        scratch_state;
 565         struct r600_resource    *scratch_buffer;
 566         unsigned                scratch_waves;
 567         unsigned                spi_tmpring_size;
 568
 569         struct r600_resource    *compute_scratch_buffer;
 570
 571         /* Emitted derived tessellation state. */
 572         /* Local shader (VS), or HS if LS-HS are merged. */
 573         struct si_shader        *last_ls;
 574         struct si_shader_selector *last_tcs;
 575         int                     last_num_tcs_input_cp;
 576         int                     last_tes_sh_base;
 577         bool                    last_tess_uses_primid;
 578         unsigned                last_num_patches;
 579
 580         /* Debug state. */
 581         bool                    is_debug;
 582         struct si_saved_cs      *current_saved_cs;
 583         uint64_t                dmesg_timestamp;
 584         unsigned                apitrace_call_number;
 585
 586         /* Other state */
 587         bool need_check_render_feedback;
 588         bool                    decompression_enabled;
 589
 590         bool                    vs_writes_viewport_index;
 591         bool                    vs_disables_clipping_viewport;
 592
 593         /* Precomputed IA_MULTI_VGT_PARAM */
 594         union si_vgt_param_key  ia_multi_vgt_param_key;
 595         unsigned                ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
 596
 597         /* Bindless descriptors. */
 598         struct si_descriptors   bindless_descriptors;
 599         struct util_idalloc     bindless_used_slots;
 600         unsigned                num_bindless_descriptors;
 601         bool                    bindless_descriptors_dirty;
 602         bool                    graphics_bindless_pointer_dirty;
 603         bool                    compute_bindless_pointer_dirty;
 604
 605         /* Allocated bindless handles */
 606         struct hash_table       *tex_handles;
 607         struct hash_table       *img_handles;
 608
 609         /* Resident bindless handles */
 610         struct util_dynarray    resident_tex_handles;
 611         struct util_dynarray    resident_img_handles;
 612
 613         /* Resident bindless handles which need decompression */
 614         struct util_dynarray    resident_tex_needs_color_decompress;
 615         struct util_dynarray    resident_img_needs_color_decompress;
 616         struct util_dynarray    resident_tex_needs_depth_decompress;
 617
 618         /* Bindless state */
 619         bool                    uses_bindless_samplers;
 620         bool                    uses_bindless_images;
 621
 622         /* MSAA sample locations.
 623          * The first index is the sample index.
 624          * The second index is the coordinate: X, Y. */
 625         float                   sample_locations_1x[1][2];
 626         float                   sample_locations_2x[2][2];
 627         float                   sample_locations_4x[4][2];
 628         float                   sample_locations_8x[8][2];
 629         float                   sample_locations_16x[16][2];
 630 };
 631
 632 /* cik_sdma.c */
 633 void cik_init_sdma_functions(struct si_context *sctx);
 634
 635 /* si_blit.c */
 636 enum si_blitter_op /* bitmask */
 637 {
 638         SI_SAVE_TEXTURES      = 1,
 639         SI_SAVE_FRAMEBUFFER   = 2,
 640         SI_SAVE_FRAGMENT_STATE = 4,
 641         SI_DISABLE_RENDER_COND = 8,
 642 };
 643
 644 void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op);
 645 void si_blitter_end(struct pipe_context *ctx);
 646 void si_init_blit_functions(struct si_context *sctx);
 647 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
 648 void si_resource_copy_region(struct pipe_context *ctx,
 649                              struct pipe_resource *dst,
 650                              unsigned dst_level,
 651                              unsigned dstx, unsigned dsty, unsigned dstz,
 652                              struct pipe_resource *src,
 653                              unsigned src_level,
 654                              const struct pipe_box *src_box);
 655
 656 /* si_clear.c */
 657 void vi_dcc_clear_level(struct si_context *sctx,
 658                         struct r600_texture *rtex,
 659                         unsigned level, unsigned clear_value);
 660 void si_init_clear_functions(struct si_context *sctx);
 661
 662 /* si_cp_dma.c */
 663 #define SI_CPDMA_SKIP_CHECK_CS_SPACE    (1 << 0) /* don't call need_cs_space */
 664 #define SI_CPDMA_SKIP_SYNC_AFTER        (1 << 1) /* don't wait for DMA after the copy */
 665 #define SI_CPDMA_SKIP_SYNC_BEFORE       (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
 666 #define SI_CPDMA_SKIP_GFX_SYNC          (1 << 3) /* don't flush caches and don't wait for PS/CS */
 667 #define SI_CPDMA_SKIP_BO_LIST_UPDATE    (1 << 4) /* don't update the BO list */
 668 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
 669                            SI_CPDMA_SKIP_SYNC_AFTER | \
 670                            SI_CPDMA_SKIP_SYNC_BEFORE | \
 671                            SI_CPDMA_SKIP_GFX_SYNC | \
 672                            SI_CPDMA_SKIP_BO_LIST_UPDATE)
 673
 674 enum r600_coherency {
 675         R600_COHERENCY_NONE, /* no cache flushes needed */
 676         R600_COHERENCY_SHADER,
 677         R600_COHERENCY_CB_META,
 678 };
 679
 680 void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
 681                      uint64_t offset, uint64_t size, unsigned value,
 682                      enum r600_coherency coher);
 683 void si_copy_buffer(struct si_context *sctx,
 684                     struct pipe_resource *dst, struct pipe_resource *src,
 685                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 686                     unsigned user_flags);
 687 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 688                               uint64_t offset, unsigned size);
 689 void cik_emit_prefetch_L2(struct si_context *sctx);
 690 void si_init_cp_dma_functions(struct si_context *sctx);
 691
 692 /* si_debug.c */
 693 void si_auto_log_cs(void *data, struct u_log_context *log);
 694 void si_log_hw_flush(struct si_context *sctx);
 695 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
 696 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
 697 void si_init_debug_functions(struct si_context *sctx);
 698 void si_check_vm_faults(struct r600_common_context *ctx,
 699                         struct radeon_saved_cs *saved, enum ring_type ring);
 700 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
 701
 702 /* si_dma.c */
 703 void si_init_dma_functions(struct si_context *sctx);
 704
 705 /* si_fence.c */
 706 void si_init_fence_functions(struct si_context *ctx);
 707 void si_init_screen_fence_functions(struct si_screen *screen);
 708 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
 709                                           struct tc_unflushed_batch_token *tc_token);
 710
 711 /* si_get.c */
 712 const char *si_get_family_name(const struct si_screen *sscreen);
 713 void si_init_screen_get_functions(struct si_screen *sscreen);
 714
 715 /* si_hw_context.c */
 716 void si_destroy_saved_cs(struct si_saved_cs *scs);
 717 void si_context_gfx_flush(void *context, unsigned flags,
 718                           struct pipe_fence_handle **fence);
 719 void si_begin_new_cs(struct si_context *ctx);
 720 void si_need_cs_space(struct si_context *ctx);
 721
 722 /* si_compute.c */
 723 void si_init_compute_functions(struct si_context *sctx);
 724
 725 /* si_perfcounters.c */
 726 void si_init_perfcounters(struct si_screen *screen);
 727
 728 /* si_test_dma.c */
 729 void si_test_dma(struct si_screen *sscreen);
 730
 731 /* si_uvd.c */
 732 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 733                                                const struct pipe_video_codec *templ);
 734
 735 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 736                                                  const struct pipe_video_buffer *tmpl);
 737
 738 /* si_viewport.c */
 739 void si_update_vs_viewport_state(struct si_context *ctx);
 740 void si_init_viewport_functions(struct si_context *ctx);
 741
 742
 743 /*
 744  * common helpers
 745  */
 746
 747 static inline void
 748 si_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 749 {
 750         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 751         struct r600_resource *res = (struct r600_resource *)r;
 752
 753         if (res) {
 754                 /* Add memory usage for need_gfx_cs_space */
 755                 rctx->vram += res->vram_usage;
 756                 rctx->gtt += res->gart_usage;
 757         }
 758 }
 759
 760 static inline void
 761 si_invalidate_draw_sh_constants(struct si_context *sctx)
 762 {
 763         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 764 }
 765
 766 static inline void
 767 si_set_atom_dirty(struct si_context *sctx,
 768                   struct r600_atom *atom, bool dirty)
 769 {
 770         unsigned bit = 1 << atom->id;
 771
 772         if (dirty)
 773                 sctx->dirty_atoms |= bit;
 774         else
 775                 sctx->dirty_atoms &= ~bit;
 776 }
 777
 778 static inline bool
 779 si_is_atom_dirty(struct si_context *sctx,
 780                   struct r600_atom *atom)
 781 {
 782         unsigned bit = 1 << atom->id;
 783
 784         return sctx->dirty_atoms & bit;
 785 }
 786
 787 static inline void
 788 si_mark_atom_dirty(struct si_context *sctx,
 789                    struct r600_atom *atom)
 790 {
 791         si_set_atom_dirty(sctx, atom, true);
 792 }
 793
 794 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
 795 {
 796         if (sctx->gs_shader.cso)
 797                 return &sctx->gs_shader;
 798         if (sctx->tes_shader.cso)
 799                 return &sctx->tes_shader;
 800
 801         return &sctx->vs_shader;
 802 }
 803
 804 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 805 {
 806         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 807
 808         return vs->cso ? &vs->cso->info : NULL;
 809 }
 810
 811 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 812 {
 813         if (sctx->gs_shader.cso)
 814                 return sctx->gs_shader.cso->gs_copy_shader;
 815
 816         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 817         return vs->current ? vs->current : NULL;
 818 }
 819
 820 static inline bool si_can_dump_shader(struct si_screen *sscreen,
 821                                       unsigned processor)
 822 {
 823         return sscreen->debug_flags & (1 << processor);
 824 }
 825
 826 static inline bool si_extra_shader_checks(struct si_screen *sscreen,
 827                                           unsigned processor)
 828 {
 829         return (sscreen->debug_flags & DBG(CHECK_IR)) ||
 830                si_can_dump_shader(sscreen, processor);
 831 }
 832
 833 static inline bool si_get_strmout_en(struct si_context *sctx)
 834 {
 835         return sctx->streamout.streamout_enabled ||
 836                sctx->streamout.prims_gen_query_enabled;
 837 }
 838
 839 static inline unsigned
 840 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
 841 {
 842         unsigned alignment, tcc_cache_line_size;
 843
 844         /* If the upload size is less than the cache line size (e.g. 16, 32),
 845          * the whole thing will fit into a cache line if we align it to its size.
 846          * The idea is that multiple small uploads can share a cache line.
 847          * If the upload size is greater, align it to the cache line size.
 848          */
 849         alignment = util_next_power_of_two(upload_size);
 850         tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
 851         return MIN2(alignment, tcc_cache_line_size);
 852 }
 853
 854 static inline void
 855 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
 856 {
 857         if (pipe_reference(&(*dst)->reference, &src->reference))
 858                 si_destroy_saved_cs(*dst);
 859
 860         *dst = src;
 861 }
 862
 863 static inline void
 864 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 865                            bool shaders_read_metadata)
 866 {
 867         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
 868                          SI_CONTEXT_INV_VMEM_L1;
 869
 870         if (sctx->b.chip_class >= GFX9) {
 871                 /* Single-sample color is coherent with shaders on GFX9, but
 872                  * L2 metadata must be flushed if shaders read metadata.
 873                  * (DCC, CMASK).
 874                  */
 875                 if (num_samples >= 2)
 876                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 877                 else if (shaders_read_metadata)
 878                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 879         } else {
 880                 /* SI-CI-VI */
 881                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 882         }
 883 }
 884
 885 static inline void
 886 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 887                            bool include_stencil, bool shaders_read_metadata)
 888 {
 889         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
 890                          SI_CONTEXT_INV_VMEM_L1;
 891
 892         if (sctx->b.chip_class >= GFX9) {
 893                 /* Single-sample depth (not stencil) is coherent with shaders
 894                  * on GFX9, but L2 metadata must be flushed if shaders read
 895                  * metadata.
 896                  */
 897                 if (num_samples >= 2 || include_stencil)
 898                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 899                 else if (shaders_read_metadata)
 900                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 901         } else {
 902                 /* SI-CI-VI */
 903                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 904         }
 905 }
 906
 907 static inline bool
 908 si_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
 909 {
 910         return (stencil_sampler && tex->can_sample_s) ||
 911                (!stencil_sampler && tex->can_sample_z);
 912 }
 913
 914 static inline bool
 915 si_htile_enabled(struct r600_texture *tex, unsigned level)
 916 {
 917         return tex->htile_offset && level == 0;
 918 }
 919
 920 static inline bool
 921 vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level)
 922 {
 923         assert(!tex->tc_compatible_htile || tex->htile_offset);
 924         return tex->tc_compatible_htile && level == 0;
 925 }
 926
 927 #endif