2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "si_shader.h"
31 #ifdef PIPE_ARCH_BIG_ENDIAN
32 #define SI_BIG_ENDIAN 1
34 #define SI_BIG_ENDIAN 0
37 /* The base vertex and primitive restart can be any number, but we must pick
38 * one which will mean "unknown" for the purpose of state tracking and
39 * the number shouldn't be a commonly-used one. */
40 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
41 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
42 #define SI_NUM_SMOOTH_AA_SAMPLES 8
43 #define SI_GS_PER_ES 128
44 /* Alignment for optimal CP DMA performance. */
45 #define SI_CPDMA_ALIGNMENT 32
47 /* Instruction cache. */
48 #define SI_CONTEXT_INV_ICACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
49 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
50 #define SI_CONTEXT_INV_SMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 1)
51 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
52 #define SI_CONTEXT_INV_VMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 2)
53 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
54 #define SI_CONTEXT_INV_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 3)
55 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
56 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
57 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 4)
59 /* Framebuffer caches. */
60 #define SI_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 7)
61 #define SI_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 8)
62 /* Engine synchronization. */
63 #define SI_CONTEXT_VS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 9)
64 #define SI_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 10)
65 #define SI_CONTEXT_CS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 11)
66 #define SI_CONTEXT_VGT_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 12)
67 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (R600_CONTEXT_PRIVATE_FLAG << 13)
69 #define SI_MAX_BORDER_COLORS 4096
73 struct u_suballocator
;
76 struct r600_common_screen b
;
77 unsigned gs_table_depth
;
78 unsigned tess_offchip_block_dw_size
;
79 bool has_distributed_tess
;
80 bool has_draw_indirect_multi
;
82 bool has_msaa_sample_loc_bug
;
84 /* Whether shaders are monolithic (1-part) or separate (3-part). */
85 bool use_monolithic_shaders
;
88 mtx_t shader_parts_mutex
;
89 struct si_shader_part
*vs_prologs
;
90 struct si_shader_part
*tcs_epilogs
;
91 struct si_shader_part
*gs_prologs
;
92 struct si_shader_part
*ps_prologs
;
93 struct si_shader_part
*ps_epilogs
;
95 /* Shader cache in memory.
97 * Design & limitations:
98 * - The shader cache is per screen (= per process), never saved to
99 * disk, and skips redundant shader compilations from TGSI to bytecode.
100 * - It can only be used with one-variant-per-shader support, in which
101 * case only the main (typically middle) part of shaders is cached.
102 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
103 * variants of VS and TES are cached, so LS and ES aren't.
104 * - GS and CS aren't cached, but it's certainly possible to cache
107 mtx_t shader_cache_mutex
;
108 struct hash_table
*shader_cache
;
110 /* Shader compiler queue for multithreaded compilation. */
111 struct util_queue shader_compiler_queue
;
112 LLVMTargetMachineRef tm
[4]; /* used by the queue only */
115 struct si_blend_color
{
116 struct r600_atom atom
;
117 struct pipe_blend_color state
;
120 struct si_sampler_view
{
121 struct pipe_sampler_view base
;
122 /* [0..7] = image descriptor
123 * [4..7] = buffer descriptor */
125 uint32_t fmask_state
[8];
126 const struct legacy_surf_level
*base_level_info
;
128 unsigned block_width
;
129 bool is_stencil_sampler
;
130 bool dcc_incompatible
;
133 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
135 struct si_sampler_state
{
142 struct si_cs_shader_state
{
143 struct si_compute
*program
;
144 struct si_compute
*emitted_program
;
150 struct si_textures_info
{
151 struct si_sampler_views views
;
152 uint32_t depth_texture_mask
; /* which textures are depth */
153 uint32_t compressed_colortex_mask
;
156 struct si_images_info
{
157 struct pipe_image_view views
[SI_NUM_IMAGES
];
158 uint32_t compressed_colortex_mask
;
159 unsigned enabled_mask
;
162 struct si_framebuffer
{
163 struct r600_atom atom
;
164 struct pipe_framebuffer_state state
;
166 unsigned log_samples
;
167 unsigned compressed_cb_mask
;
168 unsigned colorbuf_enabled_4bit
;
169 unsigned spi_shader_col_format
;
170 unsigned spi_shader_col_format_alpha
;
171 unsigned spi_shader_col_format_blend
;
172 unsigned spi_shader_col_format_blend_alpha
;
173 unsigned color_is_int8
;
174 unsigned color_is_int10
;
175 unsigned dirty_cbufs
;
178 bool do_update_surf_dirtiness
;
181 struct si_clip_state
{
182 struct r600_atom atom
;
183 struct pipe_clip_state state
;
186 struct si_sample_locs
{
187 struct r600_atom atom
;
191 struct si_sample_mask
{
192 struct r600_atom atom
;
193 uint16_t sample_mask
;
196 /* A shader state consists of the shader selector, which is a constant state
197 * object shared by multiple contexts and shouldn't be modified, and
198 * the current shader variant selected for this context.
200 struct si_shader_ctx_state
{
201 struct si_shader_selector
*cso
;
202 struct si_shader
*current
;
205 #define SI_NUM_VGT_PARAM_KEY_BITS 12
206 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
208 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
209 * Some fields are set by state-change calls, most are set by draw_vbo.
211 union si_vgt_param_key
{
214 unsigned uses_instancing
:1;
215 unsigned multi_instances_smaller_than_primgroup
:1;
216 unsigned primitive_restart
:1;
217 unsigned count_from_stream_output
:1;
218 unsigned line_stipple_enabled
:1;
219 unsigned uses_tess
:1;
220 unsigned tess_uses_prim_id
:1;
222 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
228 struct r600_common_context b
;
229 struct blitter_context
*blitter
;
230 void *custom_dsa_flush
;
231 void *custom_blend_resolve
;
232 void *custom_blend_decompress
;
233 void *custom_blend_fastclear
;
234 void *custom_blend_dcc_decompress
;
235 struct si_screen
*screen
;
237 struct radeon_winsys_cs
*ce_ib
;
238 struct radeon_winsys_cs
*ce_preamble_ib
;
239 bool ce_need_synchronization
;
240 struct u_suballocator
*ce_suballocator
;
242 struct si_shader_ctx_state fixed_func_tcs_shader
;
243 LLVMTargetMachineRef tm
; /* only non-threaded compilation */
244 bool gfx_flush_in_progress
;
245 bool compute_is_busy
;
247 /* Atoms (direct states). */
248 union si_state_atoms atoms
;
249 unsigned dirty_atoms
; /* mask */
250 /* PM4 states (precomputed immutable states) */
251 unsigned dirty_states
;
252 union si_state queued
;
253 union si_state emitted
;
255 /* Atom declarations. */
256 struct r600_atom prefetch_L2
;
257 struct si_framebuffer framebuffer
;
258 struct si_sample_locs msaa_sample_locs
;
259 struct r600_atom db_render_state
;
260 struct r600_atom msaa_config
;
261 struct si_sample_mask sample_mask
;
262 struct r600_atom cb_render_state
;
263 unsigned last_cb_target_mask
;
264 struct si_blend_color blend_color
;
265 struct r600_atom clip_regs
;
266 struct si_clip_state clip_state
;
267 struct si_shader_data shader_userdata
;
268 struct si_stencil_ref stencil_ref
;
269 struct r600_atom spi_map
;
271 /* Precomputed states. */
272 struct si_pm4_state
*init_config
;
273 struct si_pm4_state
*init_config_gs_rings
;
274 bool init_config_has_vgt_flush
;
275 struct si_pm4_state
*vgt_shader_config
[4];
278 struct si_shader_ctx_state ps_shader
;
279 struct si_shader_ctx_state gs_shader
;
280 struct si_shader_ctx_state vs_shader
;
281 struct si_shader_ctx_state tcs_shader
;
282 struct si_shader_ctx_state tes_shader
;
283 struct si_cs_shader_state cs_shader_state
;
285 /* shader information */
286 struct si_vertex_element
*vertex_elements
;
287 unsigned sprite_coord_enable
;
289 bool do_update_shaders
;
291 /* shader descriptors */
292 struct si_descriptors vertex_buffers
;
293 struct si_descriptors descriptors
[SI_NUM_DESCS
];
294 unsigned descriptors_dirty
;
295 unsigned shader_pointers_dirty
;
296 unsigned compressed_tex_shader_mask
;
297 struct si_buffer_resources rw_buffers
;
298 struct si_buffer_resources const_buffers
[SI_NUM_SHADERS
];
299 struct si_buffer_resources shader_buffers
[SI_NUM_SHADERS
];
300 struct si_textures_info samplers
[SI_NUM_SHADERS
];
301 struct si_images_info images
[SI_NUM_SHADERS
];
303 /* other shader resources */
304 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on CIK */
305 struct pipe_resource
*esgs_ring
;
306 struct pipe_resource
*gsvs_ring
;
307 struct pipe_resource
*tf_ring
;
308 struct pipe_resource
*tess_offchip_ring
;
309 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
310 struct r600_resource
*border_color_buffer
;
311 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
312 unsigned border_color_count
;
314 /* Vertex and index buffers. */
315 bool vertex_buffers_dirty
;
316 bool vertex_buffer_pointer_dirty
;
317 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
319 /* MSAA config state. */
321 bool smoothing_enabled
;
323 /* DB render state. */
324 bool dbcb_depth_copy_enabled
;
325 bool dbcb_stencil_copy_enabled
;
326 unsigned dbcb_copy_sample
;
327 bool db_flush_depth_inplace
;
328 bool db_flush_stencil_inplace
;
330 bool db_depth_disable_expclear
;
331 bool db_stencil_clear
;
332 bool db_stencil_disable_expclear
;
333 unsigned ps_db_shader_control
;
334 bool occlusion_queries_disabled
;
336 /* Emitted draw state. */
338 int last_base_vertex
;
339 int last_start_instance
;
341 int last_sh_base_reg
;
342 int last_primitive_restart_en
;
343 int last_restart_index
;
344 int last_gs_out_prim
;
346 int last_multi_vgt_param
;
348 unsigned last_sc_line_stipple
;
349 unsigned current_vs_state
;
350 unsigned last_vs_state
;
351 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
352 bool gs_tri_strip_adj_fix
;
355 struct r600_atom scratch_state
;
356 struct r600_resource
*scratch_buffer
;
357 unsigned scratch_waves
;
358 unsigned spi_tmpring_size
;
360 struct r600_resource
*compute_scratch_buffer
;
362 /* Emitted derived tessellation state. */
363 /* Local shader (VS), or HS if LS-HS are merged. */
364 struct si_shader
*last_ls
;
365 struct si_shader_selector
*last_tcs
;
366 int last_num_tcs_input_cp
;
367 int last_tes_sh_base
;
368 unsigned last_num_patches
;
372 struct radeon_saved_cs last_gfx
;
373 struct r600_resource
*last_trace_buf
;
374 struct r600_resource
*trace_buf
;
376 uint64_t dmesg_timestamp
;
377 unsigned apitrace_call_number
;
380 bool need_check_render_feedback
;
382 /* Precomputed IA_MULTI_VGT_PARAM */
383 union si_vgt_param_key ia_multi_vgt_param_key
;
384 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
388 void cik_init_sdma_functions(struct si_context
*sctx
);
391 void si_init_blit_functions(struct si_context
*sctx
);
392 void si_decompress_graphics_textures(struct si_context
*sctx
);
393 void si_decompress_compute_textures(struct si_context
*sctx
);
394 void si_resource_copy_region(struct pipe_context
*ctx
,
395 struct pipe_resource
*dst
,
397 unsigned dstx
, unsigned dsty
, unsigned dstz
,
398 struct pipe_resource
*src
,
400 const struct pipe_box
*src_box
);
403 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
404 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
405 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
406 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
407 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
408 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
409 SI_CPDMA_SKIP_SYNC_AFTER | \
410 SI_CPDMA_SKIP_SYNC_BEFORE | \
411 SI_CPDMA_SKIP_GFX_SYNC | \
412 SI_CPDMA_SKIP_BO_LIST_UPDATE)
414 void si_copy_buffer(struct si_context
*sctx
,
415 struct pipe_resource
*dst
, struct pipe_resource
*src
,
416 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
417 unsigned user_flags
);
418 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
419 uint64_t offset
, unsigned size
);
420 void si_init_cp_dma_functions(struct si_context
*sctx
);
423 void si_init_debug_functions(struct si_context
*sctx
);
424 void si_check_vm_faults(struct r600_common_context
*ctx
,
425 struct radeon_saved_cs
*saved
, enum ring_type ring
);
426 bool si_replace_shader(unsigned num
, struct ac_shader_binary
*binary
);
429 void si_init_dma_functions(struct si_context
*sctx
);
431 /* si_hw_context.c */
432 void si_context_gfx_flush(void *context
, unsigned flags
,
433 struct pipe_fence_handle
**fence
);
434 void si_begin_new_cs(struct si_context
*ctx
);
435 void si_need_cs_space(struct si_context
*ctx
);
438 void si_init_compute_functions(struct si_context
*sctx
);
440 /* si_perfcounters.c */
441 void si_init_perfcounters(struct si_screen
*screen
);
444 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
445 const struct pipe_video_codec
*templ
);
447 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
448 const struct pipe_video_buffer
*tmpl
);
455 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
457 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
461 si_set_atom_dirty(struct si_context
*sctx
,
462 struct r600_atom
*atom
, bool dirty
)
464 unsigned bit
= 1 << atom
->id
;
467 sctx
->dirty_atoms
|= bit
;
469 sctx
->dirty_atoms
&= ~bit
;
473 si_is_atom_dirty(struct si_context
*sctx
,
474 struct r600_atom
*atom
)
476 unsigned bit
= 1 << atom
->id
;
478 return sctx
->dirty_atoms
& bit
;
482 si_mark_atom_dirty(struct si_context
*sctx
,
483 struct r600_atom
*atom
)
485 si_set_atom_dirty(sctx
, atom
, true);
488 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
490 if (sctx
->gs_shader
.cso
)
491 return &sctx
->gs_shader
.cso
->info
;
492 else if (sctx
->tes_shader
.cso
)
493 return &sctx
->tes_shader
.cso
->info
;
494 else if (sctx
->vs_shader
.cso
)
495 return &sctx
->vs_shader
.cso
->info
;
500 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
502 if (sctx
->gs_shader
.current
)
503 return sctx
->gs_shader
.cso
->gs_copy_shader
;
504 else if (sctx
->tes_shader
.current
)
505 return sctx
->tes_shader
.current
;
507 return sctx
->vs_shader
.current
;
510 static inline unsigned
511 si_optimal_tcc_alignment(struct si_context
*sctx
, unsigned upload_size
)
513 unsigned alignment
, tcc_cache_line_size
;
515 /* If the upload size is less than the cache line size (e.g. 16, 32),
516 * the whole thing will fit into a cache line if we align it to its size.
517 * The idea is that multiple small uploads can share a cache line.
518 * If the upload size is greater, align it to the cache line size.
520 alignment
= util_next_power_of_two(upload_size
);
521 tcc_cache_line_size
= sctx
->screen
->b
.info
.tcc_cache_line_size
;
522 return MIN2(alignment
, tcc_cache_line_size
);