src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef SI_PIPE_H
  27 #define SI_PIPE_H
  28
  29 #include "si_shader.h"
  30
  31 #ifdef PIPE_ARCH_BIG_ENDIAN
  32 #define SI_BIG_ENDIAN 1
  33 #else
  34 #define SI_BIG_ENDIAN 0
  35 #endif
  36
  37 /* The base vertex and primitive restart can be any number, but we must pick
  38  * one which will mean "unknown" for the purpose of state tracking and
  39  * the number shouldn't be a commonly-used one. */
  40 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  41 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  42 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  43 #define SI_GS_PER_ES 128
  44
  45 /* Instruction cache. */
  46 #define SI_CONTEXT_INV_ICACHE           (R600_CONTEXT_PRIVATE_FLAG << 0)
  47 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  48 #define SI_CONTEXT_INV_SMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 1)
  49 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  50 #define SI_CONTEXT_INV_VMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 2)
  51 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  52 #define SI_CONTEXT_INV_GLOBAL_L2        (R600_CONTEXT_PRIVATE_FLAG << 3)
  53 /* Framebuffer caches. */
  54 #define SI_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
  55 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
  56 #define SI_CONTEXT_FLUSH_AND_INV_DB     (R600_CONTEXT_PRIVATE_FLAG << 6)
  57 #define SI_CONTEXT_FLUSH_AND_INV_CB     (R600_CONTEXT_PRIVATE_FLAG << 7)
  58 /* Engine synchronization. */
  59 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 8)
  60 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 9)
  61 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 10)
  62 #define SI_CONTEXT_VGT_FLUSH            (R600_CONTEXT_PRIVATE_FLAG << 11)
  63 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (R600_CONTEXT_PRIVATE_FLAG << 12)
  64
  65 #define SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER (SI_CONTEXT_FLUSH_AND_INV_CB | \
  66                                               SI_CONTEXT_FLUSH_AND_INV_CB_META | \
  67                                               SI_CONTEXT_FLUSH_AND_INV_DB | \
  68                                               SI_CONTEXT_FLUSH_AND_INV_DB_META)
  69
  70 #define SI_ENCODE_TRACE_POINT(id)       (0xcafe0000 | ((id) & 0xffff))
  71 #define SI_IS_TRACE_POINT(x)            (((x) & 0xcafe0000) == 0xcafe0000)
  72 #define SI_GET_TRACE_POINT_ID(x)        ((x) & 0xffff)
  73
  74 #define SI_MAX_BORDER_COLORS    4096
  75
  76 struct si_compute;
  77 struct hash_table;
  78 struct u_suballocator;
  79
  80 struct si_screen {
  81         struct r600_common_screen       b;
  82         unsigned                        gs_table_depth;
  83         unsigned                        tess_offchip_block_dw_size;
  84         bool                            has_distributed_tess;
  85         bool                            has_draw_indirect_multi;
  86
  87         /* Whether shaders are monolithic (1-part) or separate (3-part). */
  88         bool                            use_monolithic_shaders;
  89         bool                            record_llvm_ir;
  90
  91         pipe_mutex                      shader_parts_mutex;
  92         struct si_shader_part           *vs_prologs;
  93         struct si_shader_part           *vs_epilogs;
  94         struct si_shader_part           *tcs_epilogs;
  95         struct si_shader_part           *ps_prologs;
  96         struct si_shader_part           *ps_epilogs;
  97
  98         /* Shader cache in memory.
  99          *
 100          * Design & limitations:
 101          * - The shader cache is per screen (= per process), never saved to
 102          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 103          * - It can only be used with one-variant-per-shader support, in which
 104          *   case only the main (typically middle) part of shaders is cached.
 105          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 106          *   variants of VS and TES are cached, so LS and ES aren't.
 107          * - GS and CS aren't cached, but it's certainly possible to cache
 108          *   those as well.
 109          */
 110         pipe_mutex                      shader_cache_mutex;
 111         struct hash_table               *shader_cache;
 112
 113         /* Shader compiler queue for multithreaded compilation. */
 114         struct util_queue               shader_compiler_queue;
 115         LLVMTargetMachineRef            tm[4]; /* used by the queue only */
 116 };
 117
 118 struct si_blend_color {
 119         struct r600_atom                atom;
 120         struct pipe_blend_color         state;
 121 };
 122
 123 struct si_sampler_view {
 124         struct pipe_sampler_view        base;
 125         /* [0..7] = image descriptor
 126          * [4..7] = buffer descriptor */
 127         uint32_t                        state[8];
 128         uint32_t                        fmask_state[8];
 129         const struct radeon_surf_level  *base_level_info;
 130         unsigned                        base_level;
 131         unsigned                        block_width;
 132         bool is_stencil_sampler;
 133 };
 134
 135 struct si_sampler_state {
 136         uint32_t                        val[4];
 137 };
 138
 139 struct si_cs_shader_state {
 140         struct si_compute               *program;
 141         struct si_compute               *emitted_program;
 142         unsigned                        offset;
 143         bool                            initialized;
 144         bool                            uses_scratch;
 145 };
 146
 147 struct si_textures_info {
 148         struct si_sampler_views         views;
 149         uint32_t                        depth_texture_mask; /* which textures are depth */
 150         uint32_t                        compressed_colortex_mask;
 151 };
 152
 153 struct si_images_info {
 154         struct pipe_image_view          views[SI_NUM_IMAGES];
 155         uint32_t                        compressed_colortex_mask;
 156         unsigned                        enabled_mask;
 157 };
 158
 159 struct si_framebuffer {
 160         struct r600_atom                atom;
 161         struct pipe_framebuffer_state   state;
 162         unsigned                        nr_samples;
 163         unsigned                        log_samples;
 164         unsigned                        cb0_is_integer;
 165         unsigned                        compressed_cb_mask;
 166         unsigned                        spi_shader_col_format;
 167         unsigned                        spi_shader_col_format_alpha;
 168         unsigned                        spi_shader_col_format_blend;
 169         unsigned                        spi_shader_col_format_blend_alpha;
 170         unsigned                        color_is_int8; /* bitmask */
 171         unsigned                        dirty_cbufs;
 172         bool                            dirty_zsbuf;
 173         bool                            any_dst_linear;
 174 };
 175
 176 struct si_clip_state {
 177         struct r600_atom                atom;
 178         struct pipe_clip_state          state;
 179 };
 180
 181 struct si_sample_locs {
 182         struct r600_atom        atom;
 183         unsigned                nr_samples;
 184 };
 185
 186 struct si_sample_mask {
 187         struct r600_atom        atom;
 188         uint16_t                sample_mask;
 189 };
 190
 191 /* A shader state consists of the shader selector, which is a constant state
 192  * object shared by multiple contexts and shouldn't be modified, and
 193  * the current shader variant selected for this context.
 194  */
 195 struct si_shader_ctx_state {
 196         struct si_shader_selector       *cso;
 197         struct si_shader                *current;
 198 };
 199
 200 struct si_context {
 201         struct r600_common_context      b;
 202         struct blitter_context          *blitter;
 203         void                            *custom_dsa_flush;
 204         void                            *custom_blend_resolve;
 205         void                            *custom_blend_decompress;
 206         void                            *custom_blend_fastclear;
 207         void                            *custom_blend_dcc_decompress;
 208         struct si_screen                *screen;
 209
 210         struct radeon_winsys_cs         *ce_ib;
 211         struct radeon_winsys_cs         *ce_preamble_ib;
 212         bool                            ce_need_synchronization;
 213         struct u_suballocator           *ce_suballocator;
 214
 215         struct si_shader_ctx_state      fixed_func_tcs_shader;
 216         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 217         bool                            gfx_flush_in_progress;
 218         bool                            compute_is_busy;
 219
 220         /* Atoms (direct states). */
 221         union si_state_atoms            atoms;
 222         unsigned                        dirty_atoms; /* mask */
 223         /* PM4 states (precomputed immutable states) */
 224         union si_state                  queued;
 225         union si_state                  emitted;
 226
 227         /* Atom declarations. */
 228         struct si_framebuffer           framebuffer;
 229         struct si_sample_locs           msaa_sample_locs;
 230         struct r600_atom                db_render_state;
 231         struct r600_atom                msaa_config;
 232         struct si_sample_mask           sample_mask;
 233         struct r600_atom                cb_render_state;
 234         struct si_blend_color           blend_color;
 235         struct r600_atom                clip_regs;
 236         struct si_clip_state            clip_state;
 237         struct si_shader_data           shader_userdata;
 238         struct si_stencil_ref           stencil_ref;
 239         struct r600_atom                spi_map;
 240
 241         /* Precomputed states. */
 242         struct si_pm4_state             *init_config;
 243         struct si_pm4_state             *init_config_gs_rings;
 244         bool                            init_config_has_vgt_flush;
 245         struct si_pm4_state             *vgt_shader_config[4];
 246
 247         /* shaders */
 248         struct si_shader_ctx_state      ps_shader;
 249         struct si_shader_ctx_state      gs_shader;
 250         struct si_shader_ctx_state      vs_shader;
 251         struct si_shader_ctx_state      tcs_shader;
 252         struct si_shader_ctx_state      tes_shader;
 253         struct si_cs_shader_state       cs_shader_state;
 254
 255         /* shader information */
 256         struct si_vertex_element        *vertex_elements;
 257         unsigned                        sprite_coord_enable;
 258         bool                            flatshade;
 259         bool                            do_update_shaders;
 260
 261         /* shader descriptors */
 262         struct si_descriptors           vertex_buffers;
 263         struct si_descriptors           descriptors[SI_NUM_DESCS];
 264         unsigned                        descriptors_dirty;
 265         struct si_buffer_resources      rw_buffers;
 266         struct si_buffer_resources      const_buffers[SI_NUM_SHADERS];
 267         struct si_buffer_resources      shader_buffers[SI_NUM_SHADERS];
 268         struct si_textures_info         samplers[SI_NUM_SHADERS];
 269         struct si_images_info           images[SI_NUM_SHADERS];
 270
 271         /* other shader resources */
 272         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 273         struct pipe_resource            *esgs_ring;
 274         struct pipe_resource            *gsvs_ring;
 275         struct pipe_resource            *tf_ring;
 276         struct pipe_resource            *tess_offchip_ring;
 277         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 278         struct r600_resource            *border_color_buffer;
 279         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 280         unsigned                        border_color_count;
 281
 282         /* Vertex and index buffers. */
 283         bool                            vertex_buffers_dirty;
 284         struct pipe_index_buffer        index_buffer;
 285         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 286
 287         /* MSAA config state. */
 288         int                             ps_iter_samples;
 289         bool                            smoothing_enabled;
 290
 291         /* DB render state. */
 292         bool                    dbcb_depth_copy_enabled;
 293         bool                    dbcb_stencil_copy_enabled;
 294         unsigned                dbcb_copy_sample;
 295         bool                    db_flush_depth_inplace;
 296         bool                    db_flush_stencil_inplace;
 297         bool                    db_depth_clear;
 298         bool                    db_depth_disable_expclear;
 299         bool                    db_stencil_clear;
 300         bool                    db_stencil_disable_expclear;
 301         unsigned                ps_db_shader_control;
 302         bool                    occlusion_queries_disabled;
 303
 304         /* Emitted draw state. */
 305         int                     last_index_size;
 306         int                     last_base_vertex;
 307         int                     last_start_instance;
 308         int                     last_drawid;
 309         int                     last_sh_base_reg;
 310         int                     last_primitive_restart_en;
 311         int                     last_restart_index;
 312         int                     last_gs_out_prim;
 313         int                     last_prim;
 314         int                     last_multi_vgt_param;
 315         int                     last_rast_prim;
 316         unsigned                last_sc_line_stipple;
 317         int                     last_vtx_reuse_depth;
 318         int                     current_rast_prim; /* primitive type after TES, GS */
 319         unsigned                last_gsvs_itemsize;
 320
 321         /* Scratch buffer */
 322         struct r600_resource    *scratch_buffer;
 323         bool                    emit_scratch_reloc;
 324         unsigned                scratch_waves;
 325         unsigned                spi_tmpring_size;
 326
 327         struct r600_resource    *compute_scratch_buffer;
 328
 329         /* Emitted derived tessellation state. */
 330         struct si_shader        *last_ls; /* local shader (VS) */
 331         struct si_shader_selector *last_tcs;
 332         int                     last_num_tcs_input_cp;
 333         int                     last_tes_sh_base;
 334
 335         /* Debug state. */
 336         bool                    is_debug;
 337         struct radeon_saved_cs  last_gfx;
 338         struct r600_resource    *last_trace_buf;
 339         struct r600_resource    *trace_buf;
 340         unsigned                trace_id;
 341         uint64_t                dmesg_timestamp;
 342         unsigned                apitrace_call_number;
 343
 344         /* Other state */
 345         bool need_check_render_feedback;
 346 };
 347
 348 /* cik_sdma.c */
 349 void cik_init_sdma_functions(struct si_context *sctx);
 350
 351 /* si_blit.c */
 352 void si_init_blit_functions(struct si_context *sctx);
 353 void si_decompress_graphics_textures(struct si_context *sctx);
 354 void si_decompress_compute_textures(struct si_context *sctx);
 355 void si_resource_copy_region(struct pipe_context *ctx,
 356                              struct pipe_resource *dst,
 357                              unsigned dst_level,
 358                              unsigned dstx, unsigned dsty, unsigned dstz,
 359                              struct pipe_resource *src,
 360                              unsigned src_level,
 361                              const struct pipe_box *src_box);
 362
 363 /* si_cp_dma.c */
 364 void si_copy_buffer(struct si_context *sctx,
 365                     struct pipe_resource *dst, struct pipe_resource *src,
 366                     uint64_t dst_offset, uint64_t src_offset, unsigned size);
 367 void si_init_cp_dma_functions(struct si_context *sctx);
 368
 369 /* si_debug.c */
 370 void si_init_debug_functions(struct si_context *sctx);
 371 void si_check_vm_faults(struct r600_common_context *ctx,
 372                         struct radeon_saved_cs *saved, enum ring_type ring);
 373 bool si_replace_shader(unsigned num, struct radeon_shader_binary *binary);
 374
 375 /* si_dma.c */
 376 void si_init_dma_functions(struct si_context *sctx);
 377
 378 /* si_hw_context.c */
 379 void si_context_gfx_flush(void *context, unsigned flags,
 380                           struct pipe_fence_handle **fence);
 381 void si_begin_new_cs(struct si_context *ctx);
 382 void si_need_cs_space(struct si_context *ctx);
 383
 384 /* si_compute.c */
 385 void si_init_compute_functions(struct si_context *sctx);
 386
 387 /* si_perfcounters.c */
 388 void si_init_perfcounters(struct si_screen *screen);
 389
 390 /* si_uvd.c */
 391 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 392                                                const struct pipe_video_codec *templ);
 393
 394 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 395                                                  const struct pipe_video_buffer *tmpl);
 396
 397 /*
 398  * common helpers
 399  */
 400
 401 static inline struct r600_resource *
 402 si_resource_create_custom(struct pipe_screen *screen,
 403                           unsigned usage, unsigned size)
 404 {
 405         assert(size);
 406         return r600_resource(pipe_buffer_create(screen,
 407                 PIPE_BIND_CUSTOM, usage, size));
 408 }
 409
 410 static inline void
 411 si_invalidate_draw_sh_constants(struct si_context *sctx)
 412 {
 413         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 414 }
 415
 416 static inline void
 417 si_set_atom_dirty(struct si_context *sctx,
 418                   struct r600_atom *atom, bool dirty)
 419 {
 420         unsigned bit = 1 << (atom->id - 1);
 421
 422         if (dirty)
 423                 sctx->dirty_atoms |= bit;
 424         else
 425                 sctx->dirty_atoms &= ~bit;
 426 }
 427
 428 static inline bool
 429 si_is_atom_dirty(struct si_context *sctx,
 430                   struct r600_atom *atom)
 431 {
 432         unsigned bit = 1 << (atom->id - 1);
 433
 434         return sctx->dirty_atoms & bit;
 435 }
 436
 437 static inline void
 438 si_mark_atom_dirty(struct si_context *sctx,
 439                    struct r600_atom *atom)
 440 {
 441         si_set_atom_dirty(sctx, atom, true);
 442 }
 443
 444 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 445 {
 446         if (sctx->gs_shader.cso)
 447                 return &sctx->gs_shader.cso->info;
 448         else if (sctx->tes_shader.cso)
 449                 return &sctx->tes_shader.cso->info;
 450         else if (sctx->vs_shader.cso)
 451                 return &sctx->vs_shader.cso->info;
 452         else
 453                 return NULL;
 454 }
 455
 456 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 457 {
 458         if (sctx->gs_shader.current)
 459                 return sctx->gs_shader.current->gs_copy_shader;
 460         else if (sctx->tes_shader.current)
 461                 return sctx->tes_shader.current;
 462         else
 463                 return sctx->vs_shader.current;
 464 }
 465
 466 static inline bool si_vs_exports_prim_id(struct si_shader *shader)
 467 {
 468         if (shader->selector->type == PIPE_SHADER_VERTEX)
 469                 return shader->key.vs.epilog.export_prim_id;
 470         else if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
 471                 return shader->key.tes.epilog.export_prim_id;
 472         else
 473                 return false;
 474 }
 475
 476 #endif