2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "si_shader.h"
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
38 #define SI_BIG_ENDIAN 0
41 #define ATI_VENDOR_ID 0x1002
43 #define SI_NOT_QUERY 0xffffffff
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_NUM_SMOOTH_AA_SAMPLES 8
51 #define SI_GS_PER_ES 128
52 /* Alignment for optimal CP DMA performance. */
53 #define SI_CPDMA_ALIGNMENT 32
55 /* Pipeline & streamout query controls. */
56 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
57 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
58 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
59 /* Instruction cache. */
60 #define SI_CONTEXT_INV_ICACHE (1 << 3)
61 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
62 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
63 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
64 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
65 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
66 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
67 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
68 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
69 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
70 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
71 * a CB or DB flush. */
72 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
73 /* Framebuffer caches. */
74 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
75 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
76 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
77 /* Engine synchronization. */
78 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
79 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
80 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
81 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
82 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
84 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
85 #define SI_PREFETCH_LS (1 << 1)
86 #define SI_PREFETCH_HS (1 << 2)
87 #define SI_PREFETCH_ES (1 << 3)
88 #define SI_PREFETCH_GS (1 << 4)
89 #define SI_PREFETCH_VS (1 << 5)
90 #define SI_PREFETCH_PS (1 << 6)
92 #define SI_MAX_BORDER_COLORS 4096
93 #define SI_MAX_VIEWPORTS 16
95 #define SI_MAP_BUFFER_ALIGNMENT 64
96 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
98 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
99 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
100 #define SI_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
101 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
102 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
103 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
104 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
108 /* Shader logging options: */
109 DBG_VS
= PIPE_SHADER_VERTEX
,
110 DBG_PS
= PIPE_SHADER_FRAGMENT
,
111 DBG_GS
= PIPE_SHADER_GEOMETRY
,
112 DBG_TCS
= PIPE_SHADER_TESS_CTRL
,
113 DBG_TES
= PIPE_SHADER_TESS_EVAL
,
114 DBG_CS
= PIPE_SHADER_COMPUTE
,
120 /* Shader compiler options the shader cache should be aware of: */
121 DBG_FS_CORRECT_DERIVS_AFTER_KILL
,
125 /* Shader compiler options (with no effect on the shader cache): */
128 DBG_MONOLITHIC_SHADERS
,
131 /* Information logging options: */
137 /* Driver options: */
145 /* 3D engine options: */
165 DBG_TEST_VMFAULT_SDMA
,
166 DBG_TEST_VMFAULT_SHADER
,
169 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
170 #define DBG(name) (1ull << DBG_##name)
174 struct u_suballocator
;
176 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
179 struct r600_resource
{
180 struct threaded_resource b
;
182 /* Winsys objects. */
183 struct pb_buffer
*buf
;
184 uint64_t gpu_address
;
185 /* Memory usage if the buffer placement is optimal. */
189 /* Resource properties. */
191 unsigned bo_alignment
;
192 enum radeon_bo_domain domains
;
193 enum radeon_bo_flag flags
;
194 unsigned bind_history
;
195 int max_forced_staging_uploads
;
197 /* The buffer range which is initialized (with a write transfer,
198 * streamout, DMA, or as a random access target). The rest of
199 * the buffer is considered invalid and can be mapped unsynchronized.
201 * This allows unsychronized mapping of a buffer range which hasn't
202 * been used yet. It's for applications which forget to use
203 * the unsynchronized map flag and expect the driver to figure it out.
205 struct util_range valid_buffer_range
;
207 /* For buffers only. This indicates that a write operation has been
208 * performed by TC L2, but the cache hasn't been flushed.
209 * Any hw block which doesn't use or bypasses TC L2 should check this
210 * flag and flush the cache before using the buffer.
212 * For example, TC L2 must be flushed if a buffer which has been
213 * modified by a shader store instruction is about to be used as
214 * an index buffer. The reason is that VGT DMA index fetching doesn't
219 /* Whether this resource is referenced by bindless handles. */
220 bool texture_handle_allocated
;
221 bool image_handle_allocated
;
223 /* Whether the resource has been exported via resource_get_handle. */
224 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
227 struct r600_transfer
{
228 struct threaded_transfer b
;
229 struct r600_resource
*staging
;
233 struct r600_cmask_info
{
237 unsigned slice_tile_max
;
238 uint64_t base_address_reg
;
242 struct r600_resource buffer
;
244 struct radeon_surf surface
;
246 struct si_texture
*flushed_depth_texture
;
248 /* Colorbuffer compression and fast clear. */
249 uint64_t fmask_offset
;
250 struct r600_cmask_info cmask
;
251 struct r600_resource
*cmask_buffer
;
252 uint64_t dcc_offset
; /* 0 = disabled */
253 unsigned cb_color_info
; /* fast clear enable bit */
254 unsigned color_clear_value
[2];
255 unsigned last_msaa_resolve_target_micro_mode
;
256 unsigned num_level0_transfers
;
257 unsigned num_color_samples
;
259 /* Depth buffer compression and fast clear. */
260 uint64_t htile_offset
;
261 float depth_clear_value
;
262 uint16_t dirty_level_mask
; /* each bit says if that mipmap is compressed */
263 uint16_t stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
264 enum pipe_format db_render_format
:16;
265 uint8_t stencil_clear_value
;
266 bool tc_compatible_htile
:1;
267 bool depth_cleared
:1; /* if it was cleared at least once */
268 bool stencil_cleared
:1; /* if it was cleared at least once */
269 bool upgraded_depth
:1; /* upgraded from unorm to Z32_FLOAT */
271 bool db_compatible
:1;
275 /* We need to track DCC dirtiness, because st/dri usually calls
276 * flush_resource twice per frame (not a bug) and we don't wanna
277 * decompress DCC twice. Also, the dirty tracking must be done even
278 * if DCC isn't used, because it's required by the DCC usage analysis
279 * for a possible future enablement.
281 bool separate_dcc_dirty
:1;
282 /* Statistics gathering for the DCC enablement heuristic. */
283 bool dcc_gather_statistics
:1;
284 /* Counter that should be non-zero if the texture is bound to a
287 unsigned framebuffers_bound
;
288 /* Whether the texture is a displayable back buffer and needs DCC
289 * decompression, which is expensive. Therefore, it's enabled only
290 * if statistics suggest that it will pay off and it's allocated
291 * separately. It can't be bound as a sampler by apps. Limited to
292 * target == 2D and last_level == 0. If enabled, dcc_offset contains
293 * the absolute GPUVM address, not the relative one.
295 struct r600_resource
*dcc_separate_buffer
;
296 /* When DCC is temporarily disabled, the separate buffer is here. */
297 struct r600_resource
*last_dcc_separate_buffer
;
298 /* Estimate of how much this color buffer is written to in units of
299 * full-screen draws: ps_invocations / (width * height)
300 * Shader kills, late Z, and blending with trivial discards make it
301 * inaccurate (we need to count CB updates, not PS invocations).
303 unsigned ps_draw_ratio
;
304 /* The number of clears since the last DCC usage analysis. */
305 unsigned num_slow_clears
;
308 struct r600_surface
{
309 struct pipe_surface base
;
311 /* These can vary with block-compressed textures. */
315 bool color_initialized
:1;
316 bool depth_initialized
:1;
318 /* Misc. color flags. */
319 bool color_is_int8
:1;
320 bool color_is_int10
:1;
321 bool dcc_incompatible
:1;
323 /* Color registers. */
324 unsigned cb_color_info
;
325 unsigned cb_color_view
;
326 unsigned cb_color_attrib
;
327 unsigned cb_color_attrib2
; /* GFX9 and later */
328 unsigned cb_dcc_control
; /* VI and later */
329 unsigned spi_shader_col_format
:8; /* no blending, no alpha-to-coverage. */
330 unsigned spi_shader_col_format_alpha
:8; /* alpha-to-coverage */
331 unsigned spi_shader_col_format_blend
:8; /* blending without alpha. */
332 unsigned spi_shader_col_format_blend_alpha
:8; /* blending with alpha. */
335 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE */
336 uint64_t db_stencil_base
;
337 uint64_t db_htile_data_base
;
338 unsigned db_depth_info
;
340 unsigned db_z_info2
; /* GFX9+ */
341 unsigned db_depth_view
;
342 unsigned db_depth_size
;
343 unsigned db_depth_slice
;
344 unsigned db_stencil_info
;
345 unsigned db_stencil_info2
; /* GFX9+ */
346 unsigned db_htile_surface
;
349 struct si_mmio_counter
{
354 union si_mmio_counters
{
356 /* For global GPU load including SDMA. */
357 struct si_mmio_counter gpu
;
360 struct si_mmio_counter spi
;
361 struct si_mmio_counter gui
;
362 struct si_mmio_counter ta
;
363 struct si_mmio_counter gds
;
364 struct si_mmio_counter vgt
;
365 struct si_mmio_counter ia
;
366 struct si_mmio_counter sx
;
367 struct si_mmio_counter wd
;
368 struct si_mmio_counter bci
;
369 struct si_mmio_counter sc
;
370 struct si_mmio_counter pa
;
371 struct si_mmio_counter db
;
372 struct si_mmio_counter cp
;
373 struct si_mmio_counter cb
;
376 struct si_mmio_counter sdma
;
379 struct si_mmio_counter pfp
;
380 struct si_mmio_counter meq
;
381 struct si_mmio_counter me
;
382 struct si_mmio_counter surf_sync
;
383 struct si_mmio_counter cp_dma
;
384 struct si_mmio_counter scratch_ram
;
389 struct si_memory_object
{
390 struct pipe_memory_object b
;
391 struct pb_buffer
*buf
;
395 /* Saved CS data for debugging features. */
396 struct radeon_saved_cs
{
400 struct radeon_bo_list_item
*bo_list
;
405 struct pipe_screen b
;
406 struct radeon_winsys
*ws
;
407 struct disk_cache
*disk_shader_cache
;
409 struct radeon_info info
;
410 uint64_t debug_flags
;
411 char renderer_string
[183];
413 unsigned gs_table_depth
;
414 unsigned tess_offchip_block_dw_size
;
415 unsigned tess_offchip_ring_size
;
416 unsigned tess_factor_ring_size
;
417 unsigned vgt_hs_offchip_param
;
418 unsigned eqaa_force_coverage_samples
;
419 unsigned eqaa_force_z_samples
;
420 unsigned eqaa_force_color_samples
;
421 bool has_clear_state
;
422 bool has_distributed_tess
;
423 bool has_draw_indirect_multi
;
424 bool has_out_of_order_rast
;
425 bool assume_no_z_fights
;
426 bool commutative_blend_add
;
427 bool clear_db_cache_before_clear
;
428 bool has_msaa_sample_loc_bug
;
429 bool has_ls_vgpr_init_bug
;
432 bool llvm_has_working_vgpr_indexing
;
434 /* Whether shaders are monolithic (1-part) or separate (3-part). */
435 bool use_monolithic_shaders
;
437 bool has_rbplus
; /* if RB+ registers exist */
438 bool rbplus_allowed
; /* if RB+ is allowed */
439 bool dcc_msaa_allowed
;
440 bool cpdma_prefetch_writes_memory
;
442 struct slab_parent_pool pool_transfers
;
444 /* Texture filter settings. */
445 int force_aniso
; /* -1 = disabled */
447 /* Auxiliary context. Mainly used to initialize resources.
448 * It must be locked prior to using and flushed before unlocking. */
449 struct pipe_context
*aux_context
;
450 mtx_t aux_context_lock
;
452 /* This must be in the screen, because UE4 uses one context for
453 * compilation and another one for rendering.
455 unsigned num_compilations
;
456 /* Along with ST_DEBUG=precompile, this should show if applications
457 * are loading shaders on demand. This is a monotonic counter.
459 unsigned num_shaders_created
;
460 unsigned num_shader_cache_hits
;
462 /* GPU load thread. */
463 mtx_t gpu_load_mutex
;
464 thrd_t gpu_load_thread
;
465 union si_mmio_counters mmio_counters
;
466 volatile unsigned gpu_load_stop_thread
; /* bool */
468 /* Performance counters. */
469 struct si_perfcounters
*perfcounters
;
471 /* If pipe_screen wants to recompute and re-emit the framebuffer,
472 * sampler, and image states of all contexts, it should atomically
475 * Each context will compare this with its own last known value of
476 * the counter before drawing and re-emit the states accordingly.
478 unsigned dirty_tex_counter
;
480 /* Atomically increment this counter when an existing texture's
481 * metadata is enabled or disabled in a way that requires changing
482 * contexts' compressed texture binding masks.
484 unsigned compressed_colortex_counter
;
487 /* Context flags to set so that all writes from earlier jobs
488 * in the CP are seen by L2 clients.
492 /* Context flags to set so that all writes from earlier jobs
493 * that end in L2 are seen by CP.
498 mtx_t shader_parts_mutex
;
499 struct si_shader_part
*vs_prologs
;
500 struct si_shader_part
*tcs_epilogs
;
501 struct si_shader_part
*gs_prologs
;
502 struct si_shader_part
*ps_prologs
;
503 struct si_shader_part
*ps_epilogs
;
505 /* Shader cache in memory.
507 * Design & limitations:
508 * - The shader cache is per screen (= per process), never saved to
509 * disk, and skips redundant shader compilations from TGSI to bytecode.
510 * - It can only be used with one-variant-per-shader support, in which
511 * case only the main (typically middle) part of shaders is cached.
512 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
513 * variants of VS and TES are cached, so LS and ES aren't.
514 * - GS and CS aren't cached, but it's certainly possible to cache
517 mtx_t shader_cache_mutex
;
518 struct hash_table
*shader_cache
;
520 /* Shader compiler queue for multithreaded compilation. */
521 struct util_queue shader_compiler_queue
;
522 /* Use at most 3 normal compiler threads on quadcore and better.
523 * Hyperthreaded CPUs report the number of threads, but we want
524 * the number of cores. We only need this many threads for shader-db. */
525 struct si_compiler compiler
[24]; /* used by the queue only */
527 struct util_queue shader_compiler_queue_low_priority
;
528 /* Use at most 2 low priority threads on quadcore and better.
529 * We want to minimize the impact on multithreaded Mesa. */
530 struct si_compiler compiler_lowp
[10];
533 struct si_blend_color
{
534 struct pipe_blend_color state
;
538 struct si_sampler_view
{
539 struct pipe_sampler_view base
;
540 /* [0..7] = image descriptor
541 * [4..7] = buffer descriptor */
543 uint32_t fmask_state
[8];
544 const struct legacy_surf_level
*base_level_info
;
547 bool is_stencil_sampler
;
549 bool dcc_incompatible
;
552 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
554 struct si_sampler_state
{
559 uint32_t integer_val
[4];
560 uint32_t upgraded_depth_val
[4];
563 struct si_cs_shader_state
{
564 struct si_compute
*program
;
565 struct si_compute
*emitted_program
;
572 struct pipe_sampler_view
*views
[SI_NUM_SAMPLERS
];
573 struct si_sampler_state
*sampler_states
[SI_NUM_SAMPLERS
];
575 /* The i-th bit is set if that element is enabled (non-NULL resource). */
576 unsigned enabled_mask
;
577 uint32_t needs_depth_decompress_mask
;
578 uint32_t needs_color_decompress_mask
;
582 struct pipe_image_view views
[SI_NUM_IMAGES
];
583 uint32_t needs_color_decompress_mask
;
584 unsigned enabled_mask
;
587 struct si_framebuffer
{
588 struct pipe_framebuffer_state state
;
589 unsigned colorbuf_enabled_4bit
;
590 unsigned spi_shader_col_format
;
591 unsigned spi_shader_col_format_alpha
;
592 unsigned spi_shader_col_format_blend
;
593 unsigned spi_shader_col_format_blend_alpha
;
594 ubyte nr_samples
:5; /* at most 16xAA */
595 ubyte log_samples
:3; /* at most 4 = 16xAA */
596 ubyte nr_color_samples
; /* at most 8xAA */
597 ubyte compressed_cb_mask
;
598 ubyte uncompressed_cb_mask
;
600 ubyte color_is_int10
;
604 bool CB_has_shader_readable_metadata
;
605 bool DB_has_shader_readable_metadata
;
608 struct si_signed_scissor
{
617 struct pipe_scissor_state states
[SI_MAX_VIEWPORTS
];
620 struct si_viewports
{
622 unsigned depth_range_dirty_mask
;
623 struct pipe_viewport_state states
[SI_MAX_VIEWPORTS
];
624 struct si_signed_scissor as_scissor
[SI_MAX_VIEWPORTS
];
627 struct si_clip_state
{
628 struct pipe_clip_state state
;
632 struct si_streamout_target
{
633 struct pipe_stream_output_target b
;
635 /* The buffer where BUFFER_FILLED_SIZE is stored. */
636 struct r600_resource
*buf_filled_size
;
637 unsigned buf_filled_size_offset
;
638 bool buf_filled_size_valid
;
640 unsigned stride_in_dw
;
643 struct si_streamout
{
646 unsigned enabled_mask
;
647 unsigned num_targets
;
648 struct si_streamout_target
*targets
[PIPE_MAX_SO_BUFFERS
];
650 unsigned append_bitmask
;
653 /* External state which comes from the vertex shader,
654 * it must be set explicitly when binding a shader. */
655 uint16_t *stride_in_dw
;
656 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
658 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
659 unsigned hw_enabled_mask
;
661 /* The state of VGT_STRMOUT_(CONFIG|EN). */
662 bool streamout_enabled
;
663 bool prims_gen_query_enabled
;
664 int num_prims_gen_queries
;
667 /* A shader state consists of the shader selector, which is a constant state
668 * object shared by multiple contexts and shouldn't be modified, and
669 * the current shader variant selected for this context.
671 struct si_shader_ctx_state
{
672 struct si_shader_selector
*cso
;
673 struct si_shader
*current
;
676 #define SI_NUM_VGT_PARAM_KEY_BITS 12
677 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
679 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
680 * Some fields are set by state-change calls, most are set by draw_vbo.
682 union si_vgt_param_key
{
684 #ifdef PIPE_ARCH_LITTLE_ENDIAN
686 unsigned uses_instancing
:1;
687 unsigned multi_instances_smaller_than_primgroup
:1;
688 unsigned primitive_restart
:1;
689 unsigned count_from_stream_output
:1;
690 unsigned line_stipple_enabled
:1;
691 unsigned uses_tess
:1;
692 unsigned tess_uses_prim_id
:1;
694 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
695 #else /* PIPE_ARCH_BIG_ENDIAN */
696 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
698 unsigned tess_uses_prim_id
:1;
699 unsigned uses_tess
:1;
700 unsigned line_stipple_enabled
:1;
701 unsigned count_from_stream_output
:1;
702 unsigned primitive_restart
:1;
703 unsigned multi_instances_smaller_than_primgroup
:1;
704 unsigned uses_instancing
:1;
711 struct si_texture_handle
715 struct pipe_sampler_view
*view
;
716 struct si_sampler_state sstate
;
719 struct si_image_handle
723 struct pipe_image_view view
;
727 struct pipe_reference reference
;
728 struct si_context
*ctx
;
729 struct radeon_saved_cs gfx
;
730 struct r600_resource
*trace_buf
;
733 unsigned gfx_last_dw
;
739 struct pipe_context b
; /* base class */
741 enum radeon_family family
;
742 enum chip_class chip_class
;
744 struct radeon_winsys
*ws
;
745 struct radeon_winsys_ctx
*ctx
;
746 struct radeon_cmdbuf
*gfx_cs
;
747 struct radeon_cmdbuf
*dma_cs
;
748 struct pipe_fence_handle
*last_gfx_fence
;
749 struct pipe_fence_handle
*last_sdma_fence
;
750 struct r600_resource
*eop_bug_scratch
;
751 struct u_upload_mgr
*cached_gtt_allocator
;
752 struct threaded_context
*tc
;
753 struct u_suballocator
*allocator_zeroed_memory
;
754 struct slab_child_pool pool_transfers
;
755 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
756 struct pipe_device_reset_callback device_reset_callback
;
757 struct u_log_context
*log
;
758 void *query_result_shader
;
759 struct blitter_context
*blitter
;
760 void *custom_dsa_flush
;
761 void *custom_blend_resolve
;
762 void *custom_blend_fmask_decompress
;
763 void *custom_blend_eliminate_fastclear
;
764 void *custom_blend_dcc_decompress
;
766 void *vs_blit_pos_layered
;
768 void *vs_blit_color_layered
;
769 void *vs_blit_texcoord
;
770 struct si_screen
*screen
;
771 struct pipe_debug_callback debug
;
772 struct si_compiler compiler
; /* only non-threaded compilation */
773 struct si_shader_ctx_state fixed_func_tcs_shader
;
774 struct r600_resource
*wait_mem_scratch
;
775 unsigned wait_mem_number
;
776 uint16_t prefetch_L2_mask
;
778 bool gfx_flush_in_progress
:1;
779 bool gfx_last_ib_is_busy
:1;
780 bool compute_is_busy
:1;
782 unsigned num_gfx_cs_flushes
;
783 unsigned initial_gfx_cs_size
;
784 unsigned gpu_reset_counter
;
785 unsigned last_dirty_tex_counter
;
786 unsigned last_compressed_colortex_counter
;
787 unsigned last_num_draw_calls
;
788 unsigned flags
; /* flush flags */
789 /* Current unaccounted memory usage. */
793 /* Atoms (direct states). */
794 union si_state_atoms atoms
;
795 unsigned dirty_atoms
; /* mask */
796 /* PM4 states (precomputed immutable states) */
797 unsigned dirty_states
;
798 union si_state queued
;
799 union si_state emitted
;
801 /* Atom declarations. */
802 struct si_framebuffer framebuffer
;
803 unsigned sample_locs_num_samples
;
804 uint16_t sample_mask
;
805 unsigned last_cb_target_mask
;
806 struct si_blend_color blend_color
;
807 struct si_clip_state clip_state
;
808 struct si_shader_data shader_pointers
;
809 struct si_stencil_ref stencil_ref
;
810 struct si_scissors scissors
;
811 struct si_streamout streamout
;
812 struct si_viewports viewports
;
814 /* Precomputed states. */
815 struct si_pm4_state
*init_config
;
816 struct si_pm4_state
*init_config_gs_rings
;
817 bool init_config_has_vgt_flush
;
818 struct si_pm4_state
*vgt_shader_config
[4];
821 struct si_shader_ctx_state ps_shader
;
822 struct si_shader_ctx_state gs_shader
;
823 struct si_shader_ctx_state vs_shader
;
824 struct si_shader_ctx_state tcs_shader
;
825 struct si_shader_ctx_state tes_shader
;
826 struct si_cs_shader_state cs_shader_state
;
828 /* shader information */
829 struct si_vertex_elements
*vertex_elements
;
830 unsigned sprite_coord_enable
;
832 bool do_update_shaders
;
834 /* vertex buffer descriptors */
835 uint32_t *vb_descriptors_gpu_list
;
836 struct r600_resource
*vb_descriptors_buffer
;
837 unsigned vb_descriptors_offset
;
839 /* shader descriptors */
840 struct si_descriptors descriptors
[SI_NUM_DESCS
];
841 unsigned descriptors_dirty
;
842 unsigned shader_pointers_dirty
;
843 unsigned shader_needs_decompress_mask
;
844 struct si_buffer_resources rw_buffers
;
845 struct si_buffer_resources const_and_shader_buffers
[SI_NUM_SHADERS
];
846 struct si_samplers samplers
[SI_NUM_SHADERS
];
847 struct si_images images
[SI_NUM_SHADERS
];
849 /* other shader resources */
850 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on CIK */
851 struct pipe_resource
*esgs_ring
;
852 struct pipe_resource
*gsvs_ring
;
853 struct pipe_resource
*tess_rings
;
854 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
855 struct r600_resource
*border_color_buffer
;
856 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
857 unsigned border_color_count
;
858 unsigned num_vs_blit_sgprs
;
859 uint32_t vs_blit_sh_data
[SI_VS_BLIT_SGPRS_POS_TEXCOORD
];
861 /* Vertex and index buffers. */
862 bool vertex_buffers_dirty
;
863 bool vertex_buffer_pointer_dirty
;
864 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
866 /* MSAA config state. */
868 bool ps_uses_fbfetch
;
869 bool smoothing_enabled
;
871 /* DB render state. */
872 unsigned ps_db_shader_control
;
873 unsigned dbcb_copy_sample
;
874 bool dbcb_depth_copy_enabled
:1;
875 bool dbcb_stencil_copy_enabled
:1;
876 bool db_flush_depth_inplace
:1;
877 bool db_flush_stencil_inplace
:1;
878 bool db_depth_clear
:1;
879 bool db_depth_disable_expclear
:1;
880 bool db_stencil_clear
:1;
881 bool db_stencil_disable_expclear
:1;
882 bool occlusion_queries_disabled
:1;
883 bool generate_mipmap_for_depth
:1;
885 /* Emitted draw state. */
886 bool gs_tri_strip_adj_fix
:1;
889 int last_base_vertex
;
890 int last_start_instance
;
892 int last_sh_base_reg
;
893 int last_primitive_restart_en
;
894 int last_restart_index
;
896 int last_multi_vgt_param
;
898 unsigned last_sc_line_stipple
;
899 unsigned current_vs_state
;
900 unsigned last_vs_state
;
901 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
904 struct r600_resource
*scratch_buffer
;
905 unsigned scratch_waves
;
906 unsigned spi_tmpring_size
;
908 struct r600_resource
*compute_scratch_buffer
;
910 /* Emitted derived tessellation state. */
911 /* Local shader (VS), or HS if LS-HS are merged. */
912 struct si_shader
*last_ls
;
913 struct si_shader_selector
*last_tcs
;
914 int last_num_tcs_input_cp
;
915 int last_tes_sh_base
;
916 bool last_tess_uses_primid
;
917 unsigned last_num_patches
;
918 int last_ls_hs_config
;
922 struct si_saved_cs
*current_saved_cs
;
923 uint64_t dmesg_timestamp
;
924 unsigned apitrace_call_number
;
927 bool need_check_render_feedback
;
928 bool decompression_enabled
;
930 bool vs_writes_viewport_index
;
931 bool vs_disables_clipping_viewport
;
933 /* Precomputed IA_MULTI_VGT_PARAM */
934 union si_vgt_param_key ia_multi_vgt_param_key
;
935 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
937 /* Bindless descriptors. */
938 struct si_descriptors bindless_descriptors
;
939 struct util_idalloc bindless_used_slots
;
940 unsigned num_bindless_descriptors
;
941 bool bindless_descriptors_dirty
;
942 bool graphics_bindless_pointer_dirty
;
943 bool compute_bindless_pointer_dirty
;
945 /* Allocated bindless handles */
946 struct hash_table
*tex_handles
;
947 struct hash_table
*img_handles
;
949 /* Resident bindless handles */
950 struct util_dynarray resident_tex_handles
;
951 struct util_dynarray resident_img_handles
;
953 /* Resident bindless handles which need decompression */
954 struct util_dynarray resident_tex_needs_color_decompress
;
955 struct util_dynarray resident_img_needs_color_decompress
;
956 struct util_dynarray resident_tex_needs_depth_decompress
;
959 bool uses_bindless_samplers
;
960 bool uses_bindless_images
;
962 /* MSAA sample locations.
963 * The first index is the sample index.
964 * The second index is the coordinate: X, Y. */
965 float sample_locations_1x
[1][2];
966 float sample_locations_2x
[2][2];
967 float sample_locations_4x
[4][2];
968 float sample_locations_8x
[8][2];
969 float sample_locations_16x
[16][2];
972 unsigned num_draw_calls
;
973 unsigned num_decompress_calls
;
974 unsigned num_mrt_draw_calls
;
975 unsigned num_prim_restart_calls
;
976 unsigned num_spill_draw_calls
;
977 unsigned num_compute_calls
;
978 unsigned num_spill_compute_calls
;
979 unsigned num_dma_calls
;
980 unsigned num_cp_dma_calls
;
981 unsigned num_vs_flushes
;
982 unsigned num_ps_flushes
;
983 unsigned num_cs_flushes
;
984 unsigned num_cb_cache_flushes
;
985 unsigned num_db_cache_flushes
;
986 unsigned num_L2_invalidates
;
987 unsigned num_L2_writebacks
;
988 unsigned num_resident_handles
;
989 uint64_t num_alloc_tex_transfer_bytes
;
990 unsigned last_tex_ps_draw_ratio
; /* for query */
993 /* Maintain the list of active queries for pausing between IBs. */
994 int num_occlusion_queries
;
995 int num_perfect_occlusion_queries
;
996 struct list_head active_queries
;
997 unsigned num_cs_dw_queries_suspend
;
999 /* Render condition. */
1000 struct pipe_query
*render_cond
;
1001 unsigned render_cond_mode
;
1002 bool render_cond_invert
;
1003 bool render_cond_force_off
; /* for u_blitter */
1005 /* Statistics gathering for the DCC enablement heuristic. It can't be
1006 * in si_texture because si_texture can be shared by multiple
1007 * contexts. This is for back buffers only. We shouldn't get too many
1010 * X11 DRI3 rotates among a finite set of back buffers. They should
1011 * all fit in this array. If they don't, separate DCC might never be
1012 * enabled by DCC stat gathering.
1015 struct si_texture
*tex
;
1016 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1017 struct pipe_query
*ps_stats
[3];
1018 /* If all slots are used and another slot is needed,
1019 * the least recently used slot is evicted based on this. */
1020 int64_t last_use_timestamp
;
1024 /* Copy one resource to another using async DMA. */
1025 void (*dma_copy
)(struct pipe_context
*ctx
,
1026 struct pipe_resource
*dst
,
1028 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
1029 struct pipe_resource
*src
,
1031 const struct pipe_box
*src_box
);
1033 void (*dma_clear_buffer
)(struct si_context
*sctx
, struct pipe_resource
*dst
,
1034 uint64_t offset
, uint64_t size
, unsigned value
);
1036 struct si_tracked_regs tracked_regs
;
1040 void cik_init_sdma_functions(struct si_context
*sctx
);
1043 enum si_blitter_op
/* bitmask */
1045 SI_SAVE_TEXTURES
= 1,
1046 SI_SAVE_FRAMEBUFFER
= 2,
1047 SI_SAVE_FRAGMENT_STATE
= 4,
1048 SI_DISABLE_RENDER_COND
= 8,
1051 void si_blitter_begin(struct si_context
*sctx
, enum si_blitter_op op
);
1052 void si_blitter_end(struct si_context
*sctx
);
1053 void si_init_blit_functions(struct si_context
*sctx
);
1054 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
);
1055 void si_resource_copy_region(struct pipe_context
*ctx
,
1056 struct pipe_resource
*dst
,
1058 unsigned dstx
, unsigned dsty
, unsigned dstz
,
1059 struct pipe_resource
*src
,
1061 const struct pipe_box
*src_box
);
1062 void si_decompress_dcc(struct si_context
*sctx
, struct si_texture
*tex
);
1063 void si_blit_decompress_depth(struct pipe_context
*ctx
,
1064 struct si_texture
*texture
,
1065 struct si_texture
*staging
,
1066 unsigned first_level
, unsigned last_level
,
1067 unsigned first_layer
, unsigned last_layer
,
1068 unsigned first_sample
, unsigned last_sample
);
1071 bool si_rings_is_buffer_referenced(struct si_context
*sctx
,
1072 struct pb_buffer
*buf
,
1073 enum radeon_bo_usage usage
);
1074 void *si_buffer_map_sync_with_rings(struct si_context
*sctx
,
1075 struct r600_resource
*resource
,
1077 void si_init_resource_fields(struct si_screen
*sscreen
,
1078 struct r600_resource
*res
,
1079 uint64_t size
, unsigned alignment
);
1080 bool si_alloc_resource(struct si_screen
*sscreen
,
1081 struct r600_resource
*res
);
1082 struct pipe_resource
*pipe_aligned_buffer_create(struct pipe_screen
*screen
,
1083 unsigned flags
, unsigned usage
,
1084 unsigned size
, unsigned alignment
);
1085 struct r600_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
,
1086 unsigned flags
, unsigned usage
,
1087 unsigned size
, unsigned alignment
);
1088 void si_replace_buffer_storage(struct pipe_context
*ctx
,
1089 struct pipe_resource
*dst
,
1090 struct pipe_resource
*src
);
1091 void si_init_screen_buffer_functions(struct si_screen
*sscreen
);
1092 void si_init_buffer_functions(struct si_context
*sctx
);
1095 enum pipe_format
si_simplify_cb_format(enum pipe_format format
);
1096 bool vi_alpha_is_on_msb(enum pipe_format format
);
1097 void vi_dcc_clear_level(struct si_context
*sctx
,
1098 struct si_texture
*tex
,
1099 unsigned level
, unsigned clear_value
);
1100 void si_init_clear_functions(struct si_context
*sctx
);
1103 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1104 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1105 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1106 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1107 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1108 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1109 SI_CPDMA_SKIP_SYNC_AFTER | \
1110 SI_CPDMA_SKIP_SYNC_BEFORE | \
1111 SI_CPDMA_SKIP_GFX_SYNC | \
1112 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1115 SI_COHERENCY_NONE
, /* no cache flushes needed */
1116 SI_COHERENCY_SHADER
,
1117 SI_COHERENCY_CB_META
,
1120 void si_cp_dma_wait_for_idle(struct si_context
*sctx
);
1121 void si_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1122 uint64_t offset
, uint64_t size
, unsigned value
,
1123 enum si_coherency coher
);
1124 void si_copy_buffer(struct si_context
*sctx
,
1125 struct pipe_resource
*dst
, struct pipe_resource
*src
,
1126 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
1127 unsigned user_flags
);
1128 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
1129 uint64_t offset
, unsigned size
);
1130 void cik_emit_prefetch_L2(struct si_context
*sctx
, bool vertex_stage_only
);
1131 void si_init_cp_dma_functions(struct si_context
*sctx
);
1134 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_cmdbuf
*cs
,
1135 struct radeon_saved_cs
*saved
, bool get_buffer_list
);
1136 void si_clear_saved_cs(struct radeon_saved_cs
*saved
);
1137 void si_destroy_saved_cs(struct si_saved_cs
*scs
);
1138 void si_auto_log_cs(void *data
, struct u_log_context
*log
);
1139 void si_log_hw_flush(struct si_context
*sctx
);
1140 void si_log_draw_state(struct si_context
*sctx
, struct u_log_context
*log
);
1141 void si_log_compute_state(struct si_context
*sctx
, struct u_log_context
*log
);
1142 void si_init_debug_functions(struct si_context
*sctx
);
1143 void si_check_vm_faults(struct si_context
*sctx
,
1144 struct radeon_saved_cs
*saved
, enum ring_type ring
);
1145 bool si_replace_shader(unsigned num
, struct ac_shader_binary
*binary
);
1148 void si_init_dma_functions(struct si_context
*sctx
);
1151 void si_need_dma_space(struct si_context
*ctx
, unsigned num_dw
,
1152 struct r600_resource
*dst
, struct r600_resource
*src
);
1153 void si_flush_dma_cs(struct si_context
*ctx
, unsigned flags
,
1154 struct pipe_fence_handle
**fence
);
1155 void si_screen_clear_buffer(struct si_screen
*sscreen
, struct pipe_resource
*dst
,
1156 uint64_t offset
, uint64_t size
, unsigned value
);
1159 void si_gfx_write_event_eop(struct si_context
*ctx
,
1160 unsigned event
, unsigned event_flags
,
1162 struct r600_resource
*buf
, uint64_t va
,
1163 uint32_t new_fence
, unsigned query_type
);
1164 unsigned si_gfx_write_fence_dwords(struct si_screen
*screen
);
1165 void si_gfx_wait_fence(struct si_context
*ctx
,
1166 uint64_t va
, uint32_t ref
, uint32_t mask
);
1167 void si_init_fence_functions(struct si_context
*ctx
);
1168 void si_init_screen_fence_functions(struct si_screen
*screen
);
1169 struct pipe_fence_handle
*si_create_fence(struct pipe_context
*ctx
,
1170 struct tc_unflushed_batch_token
*tc_token
);
1173 const char *si_get_family_name(const struct si_screen
*sscreen
);
1174 void si_init_screen_get_functions(struct si_screen
*sscreen
);
1177 void si_flush_gfx_cs(struct si_context
*ctx
, unsigned flags
,
1178 struct pipe_fence_handle
**fence
);
1179 void si_begin_new_gfx_cs(struct si_context
*ctx
);
1180 void si_need_gfx_cs_space(struct si_context
*ctx
);
1182 /* r600_gpu_load.c */
1183 void si_gpu_load_kill_thread(struct si_screen
*sscreen
);
1184 uint64_t si_begin_counter(struct si_screen
*sscreen
, unsigned type
);
1185 unsigned si_end_counter(struct si_screen
*sscreen
, unsigned type
,
1189 void si_init_compute_functions(struct si_context
*sctx
);
1191 /* r600_perfcounters.c */
1192 void si_perfcounters_destroy(struct si_screen
*sscreen
);
1194 /* si_perfcounters.c */
1195 void si_init_perfcounters(struct si_screen
*screen
);
1198 bool si_check_device_reset(struct si_context
*sctx
);
1201 void si_init_screen_query_functions(struct si_screen
*sscreen
);
1202 void si_init_query_functions(struct si_context
*sctx
);
1203 void si_suspend_queries(struct si_context
*sctx
);
1204 void si_resume_queries(struct si_context
*sctx
);
1207 void si_test_dma(struct si_screen
*sscreen
);
1210 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
1211 const struct pipe_video_codec
*templ
);
1213 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
1214 const struct pipe_video_buffer
*tmpl
);
1217 void si_update_vs_viewport_state(struct si_context
*ctx
);
1218 void si_init_viewport_functions(struct si_context
*ctx
);
1221 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
1222 struct si_texture
*dst
,
1223 unsigned dst_level
, unsigned dstx
,
1224 unsigned dsty
, unsigned dstz
,
1225 struct si_texture
*src
,
1227 const struct pipe_box
*src_box
);
1228 void si_texture_get_cmask_info(struct si_screen
*sscreen
,
1229 struct si_texture
*tex
,
1230 struct r600_cmask_info
*out
);
1231 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
1232 struct si_texture
*tex
);
1233 void si_texture_discard_cmask(struct si_screen
*sscreen
,
1234 struct si_texture
*tex
);
1235 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1236 struct pipe_resource
*texture
,
1237 struct si_texture
**staging
);
1238 void si_print_texture_info(struct si_screen
*sscreen
,
1239 struct si_texture
*tex
, struct u_log_context
*log
);
1240 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1241 const struct pipe_resource
*templ
);
1242 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1243 enum pipe_format format2
);
1244 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1246 enum pipe_format view_format
);
1247 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
1248 struct pipe_resource
*tex
,
1250 enum pipe_format view_format
);
1251 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1252 struct pipe_resource
*texture
,
1253 const struct pipe_surface
*templ
,
1254 unsigned width0
, unsigned height0
,
1255 unsigned width
, unsigned height
);
1256 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
1257 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
1258 struct si_texture
*tex
);
1259 void vi_separate_dcc_start_query(struct si_context
*sctx
,
1260 struct si_texture
*tex
);
1261 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
1262 struct si_texture
*tex
);
1263 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
1264 struct si_texture
*tex
);
1265 bool si_texture_disable_dcc(struct si_context
*sctx
,
1266 struct si_texture
*tex
);
1267 void si_init_screen_texture_functions(struct si_screen
*sscreen
);
1268 void si_init_context_texture_functions(struct si_context
*sctx
);
1275 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
1277 return (struct r600_resource
*)r
;
1281 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
1283 pipe_resource_reference((struct pipe_resource
**)ptr
,
1284 (struct pipe_resource
*)res
);
1288 si_texture_reference(struct si_texture
**ptr
, struct si_texture
*res
)
1290 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->buffer
.b
.b
);
1294 vi_dcc_enabled(struct si_texture
*tex
, unsigned level
)
1296 return tex
->dcc_offset
&& level
< tex
->surface
.num_dcc_levels
;
1299 static inline unsigned
1300 si_tile_mode_index(struct si_texture
*tex
, unsigned level
, bool stencil
)
1303 return tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
1305 return tex
->surface
.u
.legacy
.tiling_index
[level
];
1309 si_context_add_resource_size(struct si_context
*sctx
, struct pipe_resource
*r
)
1312 /* Add memory usage for need_gfx_cs_space */
1313 sctx
->vram
+= r600_resource(r
)->vram_usage
;
1314 sctx
->gtt
+= r600_resource(r
)->gart_usage
;
1319 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
1321 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
1324 static inline unsigned
1325 si_get_atom_bit(struct si_context
*sctx
, struct si_atom
*atom
)
1327 return 1 << (atom
- sctx
->atoms
.array
);
1331 si_set_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
, bool dirty
)
1333 unsigned bit
= si_get_atom_bit(sctx
, atom
);
1336 sctx
->dirty_atoms
|= bit
;
1338 sctx
->dirty_atoms
&= ~bit
;
1342 si_is_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1344 return (sctx
->dirty_atoms
& si_get_atom_bit(sctx
, atom
)) != 0;
1348 si_mark_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1350 si_set_atom_dirty(sctx
, atom
, true);
1353 static inline struct si_shader_ctx_state
*si_get_vs(struct si_context
*sctx
)
1355 if (sctx
->gs_shader
.cso
)
1356 return &sctx
->gs_shader
;
1357 if (sctx
->tes_shader
.cso
)
1358 return &sctx
->tes_shader
;
1360 return &sctx
->vs_shader
;
1363 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
1365 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1367 return vs
->cso
? &vs
->cso
->info
: NULL
;
1370 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
1372 if (sctx
->gs_shader
.cso
)
1373 return sctx
->gs_shader
.cso
->gs_copy_shader
;
1375 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1376 return vs
->current
? vs
->current
: NULL
;
1379 static inline bool si_can_dump_shader(struct si_screen
*sscreen
,
1382 return sscreen
->debug_flags
& (1 << processor
);
1385 static inline bool si_get_strmout_en(struct si_context
*sctx
)
1387 return sctx
->streamout
.streamout_enabled
||
1388 sctx
->streamout
.prims_gen_query_enabled
;
1391 static inline unsigned
1392 si_optimal_tcc_alignment(struct si_context
*sctx
, unsigned upload_size
)
1394 unsigned alignment
, tcc_cache_line_size
;
1396 /* If the upload size is less than the cache line size (e.g. 16, 32),
1397 * the whole thing will fit into a cache line if we align it to its size.
1398 * The idea is that multiple small uploads can share a cache line.
1399 * If the upload size is greater, align it to the cache line size.
1401 alignment
= util_next_power_of_two(upload_size
);
1402 tcc_cache_line_size
= sctx
->screen
->info
.tcc_cache_line_size
;
1403 return MIN2(alignment
, tcc_cache_line_size
);
1407 si_saved_cs_reference(struct si_saved_cs
**dst
, struct si_saved_cs
*src
)
1409 if (pipe_reference(&(*dst
)->reference
, &src
->reference
))
1410 si_destroy_saved_cs(*dst
);
1416 si_make_CB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1417 bool shaders_read_metadata
)
1419 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
|
1420 SI_CONTEXT_INV_VMEM_L1
;
1422 if (sctx
->chip_class
>= GFX9
) {
1423 /* Single-sample color is coherent with shaders on GFX9, but
1424 * L2 metadata must be flushed if shaders read metadata.
1427 if (num_samples
>= 2)
1428 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1429 else if (shaders_read_metadata
)
1430 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1433 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1438 si_make_DB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1439 bool include_stencil
, bool shaders_read_metadata
)
1441 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB
|
1442 SI_CONTEXT_INV_VMEM_L1
;
1444 if (sctx
->chip_class
>= GFX9
) {
1445 /* Single-sample depth (not stencil) is coherent with shaders
1446 * on GFX9, but L2 metadata must be flushed if shaders read
1449 if (num_samples
>= 2 || include_stencil
)
1450 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1451 else if (shaders_read_metadata
)
1452 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1455 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1460 si_can_sample_zs(struct si_texture
*tex
, bool stencil_sampler
)
1462 return (stencil_sampler
&& tex
->can_sample_s
) ||
1463 (!stencil_sampler
&& tex
->can_sample_z
);
1467 si_htile_enabled(struct si_texture
*tex
, unsigned level
)
1469 return tex
->htile_offset
&& level
== 0;
1473 vi_tc_compat_htile_enabled(struct si_texture
*tex
, unsigned level
)
1475 assert(!tex
->tc_compatible_htile
|| tex
->htile_offset
);
1476 return tex
->tc_compatible_htile
&& level
== 0;
1479 static inline unsigned si_get_ps_iter_samples(struct si_context
*sctx
)
1481 if (sctx
->ps_uses_fbfetch
)
1482 return sctx
->framebuffer
.nr_color_samples
;
1484 return MIN2(sctx
->ps_iter_samples
, sctx
->framebuffer
.nr_color_samples
);
1487 static inline unsigned si_get_total_colormask(struct si_context
*sctx
)
1489 if (sctx
->queued
.named
.rasterizer
->rasterizer_discard
)
1492 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1496 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
1497 sctx
->queued
.named
.blend
->cb_target_mask
;
1499 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
1500 colormask
&= ps
->colors_written_4bit
;
1501 else if (!ps
->colors_written_4bit
)
1502 colormask
= 0; /* color0 writes all cbufs, but it's not written */
1507 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1508 (1 << PIPE_PRIM_LINE_LOOP) | \
1509 (1 << PIPE_PRIM_LINE_STRIP) | \
1510 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1511 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1513 static inline bool util_prim_is_lines(unsigned prim
)
1515 return ((1 << prim
) & UTIL_ALL_PRIM_LINE_MODES
) != 0;
1518 static inline bool util_prim_is_points_or_lines(unsigned prim
)
1520 return ((1 << prim
) & (UTIL_ALL_PRIM_LINE_MODES
|
1521 (1 << PIPE_PRIM_POINTS
))) != 0;
1525 * Return true if there is enough memory in VRAM and GTT for the buffers
1528 * \param vram VRAM memory size not added to the buffer list yet
1529 * \param gtt GTT memory size not added to the buffer list yet
1532 radeon_cs_memory_below_limit(struct si_screen
*screen
,
1533 struct radeon_cmdbuf
*cs
,
1534 uint64_t vram
, uint64_t gtt
)
1536 vram
+= cs
->used_vram
;
1537 gtt
+= cs
->used_gart
;
1539 /* Anything that goes above the VRAM size should go to GTT. */
1540 if (vram
> screen
->info
.vram_size
)
1541 gtt
+= vram
- screen
->info
.vram_size
;
1543 /* Now we just need to check if we have enough GTT. */
1544 return gtt
< screen
->info
.gart_size
* 0.7;
1548 * Add a buffer to the buffer list for the given command stream (CS).
1550 * All buffers used by a CS must be added to the list. This tells the kernel
1551 * driver which buffers are used by GPU commands. Other buffers can
1552 * be swapped out (not accessible) during execution.
1554 * The buffer list becomes empty after every context flush and must be
1557 static inline void radeon_add_to_buffer_list(struct si_context
*sctx
,
1558 struct radeon_cmdbuf
*cs
,
1559 struct r600_resource
*rbo
,
1560 enum radeon_bo_usage usage
,
1561 enum radeon_bo_priority priority
)
1564 sctx
->ws
->cs_add_buffer(
1566 (enum radeon_bo_usage
)(usage
| RADEON_USAGE_SYNCHRONIZED
),
1567 rbo
->domains
, priority
);
1571 * Same as above, but also checks memory usage and flushes the context
1574 * When this SHOULD NOT be used:
1576 * - if si_context_add_resource_size has been called for the buffer
1577 * followed by *_need_cs_space for checking the memory usage
1579 * - if si_need_dma_space has been called for the buffer
1581 * - when emitting state packets and draw packets (because preceding packets
1582 * can't be re-emitted at that point)
1584 * - if shader resource "enabled_mask" is not up-to-date or there is
1585 * a different constraint disallowing a context flush
1588 radeon_add_to_gfx_buffer_list_check_mem(struct si_context
*sctx
,
1589 struct r600_resource
*rbo
,
1590 enum radeon_bo_usage usage
,
1591 enum radeon_bo_priority priority
,
1595 !radeon_cs_memory_below_limit(sctx
->screen
, sctx
->gfx_cs
,
1596 sctx
->vram
+ rbo
->vram_usage
,
1597 sctx
->gtt
+ rbo
->gart_usage
))
1598 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1600 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, rbo
, usage
, priority
);
1603 #define PRINT_ERR(fmt, args...) \
1604 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)