src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef SI_PIPE_H
  27 #define SI_PIPE_H
  28
  29 #include "si_shader.h"
  30
  31 #include "util/u_dynarray.h"
  32 #include "util/u_idalloc.h"
  33
  34 #ifdef PIPE_ARCH_BIG_ENDIAN
  35 #define SI_BIG_ENDIAN 1
  36 #else
  37 #define SI_BIG_ENDIAN 0
  38 #endif
  39
  40 /* The base vertex and primitive restart can be any number, but we must pick
  41  * one which will mean "unknown" for the purpose of state tracking and
  42  * the number shouldn't be a commonly-used one. */
  43 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  44 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  45 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  46 #define SI_GS_PER_ES 128
  47 /* Alignment for optimal CP DMA performance. */
  48 #define SI_CPDMA_ALIGNMENT      32
  49
  50 /* Instruction cache. */
  51 #define SI_CONTEXT_INV_ICACHE           (R600_CONTEXT_PRIVATE_FLAG << 0)
  52 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  53 #define SI_CONTEXT_INV_SMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 1)
  54 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  55 #define SI_CONTEXT_INV_VMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 2)
  56 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  57 #define SI_CONTEXT_INV_GLOBAL_L2        (R600_CONTEXT_PRIVATE_FLAG << 3)
  58 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  59  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
  60 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2  (R600_CONTEXT_PRIVATE_FLAG << 4)
  61 /* gaps */
  62 /* Framebuffer caches. */
  63 #define SI_CONTEXT_FLUSH_AND_INV_DB     (R600_CONTEXT_PRIVATE_FLAG << 7)
  64 #define SI_CONTEXT_FLUSH_AND_INV_CB     (R600_CONTEXT_PRIVATE_FLAG << 8)
  65 /* Engine synchronization. */
  66 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 9)
  67 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 10)
  68 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 11)
  69 #define SI_CONTEXT_VGT_FLUSH            (R600_CONTEXT_PRIVATE_FLAG << 12)
  70 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (R600_CONTEXT_PRIVATE_FLAG << 13)
  71
  72 #define SI_PREFETCH_VBO_DESCRIPTORS     (1 << 0)
  73 #define SI_PREFETCH_LS                  (1 << 1)
  74 #define SI_PREFETCH_HS                  (1 << 2)
  75 #define SI_PREFETCH_ES                  (1 << 3)
  76 #define SI_PREFETCH_GS                  (1 << 4)
  77 #define SI_PREFETCH_VS                  (1 << 5)
  78 #define SI_PREFETCH_PS                  (1 << 6)
  79
  80 #define SI_MAX_BORDER_COLORS    4096
  81 #define SIX_BITS                0x3F
  82
  83 struct si_compute;
  84 struct hash_table;
  85 struct u_suballocator;
  86
  87 struct si_screen {
  88         struct r600_common_screen       b;
  89         unsigned                        gs_table_depth;
  90         unsigned                        tess_offchip_block_dw_size;
  91         bool                            has_clear_state;
  92         bool                            has_distributed_tess;
  93         bool                            has_draw_indirect_multi;
  94         bool                            has_ds_bpermute;
  95         bool                            has_msaa_sample_loc_bug;
  96         bool                            llvm_has_working_vgpr_indexing;
  97
  98         /* Whether shaders are monolithic (1-part) or separate (3-part). */
  99         bool                            use_monolithic_shaders;
 100         bool                            record_llvm_ir;
 101
 102         mtx_t                   shader_parts_mutex;
 103         struct si_shader_part           *vs_prologs;
 104         struct si_shader_part           *tcs_epilogs;
 105         struct si_shader_part           *gs_prologs;
 106         struct si_shader_part           *ps_prologs;
 107         struct si_shader_part           *ps_epilogs;
 108
 109         /* Shader cache in memory.
 110          *
 111          * Design & limitations:
 112          * - The shader cache is per screen (= per process), never saved to
 113          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 114          * - It can only be used with one-variant-per-shader support, in which
 115          *   case only the main (typically middle) part of shaders is cached.
 116          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 117          *   variants of VS and TES are cached, so LS and ES aren't.
 118          * - GS and CS aren't cached, but it's certainly possible to cache
 119          *   those as well.
 120          */
 121         mtx_t                   shader_cache_mutex;
 122         struct hash_table               *shader_cache;
 123
 124         /* Shader compiler queue for multithreaded compilation. */
 125         struct util_queue               shader_compiler_queue;
 126         /* Use at most 3 normal compiler threads on quadcore and better.
 127          * Hyperthreaded CPUs report the number of threads, but we want
 128          * the number of cores. */
 129         LLVMTargetMachineRef            tm[3]; /* used by the queue only */
 130
 131         struct util_queue               shader_compiler_queue_low_priority;
 132         /* Use at most 2 low priority threads on quadcore and better.
 133          * We want to minimize the impact on multithreaded Mesa. */
 134         LLVMTargetMachineRef            tm_low_priority[2]; /* at most 2 threads */
 135 };
 136
 137 struct si_blend_color {
 138         struct r600_atom                atom;
 139         struct pipe_blend_color         state;
 140         bool                            any_nonzeros;
 141 };
 142
 143 struct si_sampler_view {
 144         struct pipe_sampler_view        base;
 145         /* [0..7] = image descriptor
 146          * [4..7] = buffer descriptor */
 147         uint32_t                        state[8];
 148         uint32_t                        fmask_state[8];
 149         const struct legacy_surf_level  *base_level_info;
 150         ubyte                           base_level;
 151         ubyte                           block_width;
 152         bool is_stencil_sampler;
 153         bool dcc_incompatible;
 154 };
 155
 156 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
 157
 158 struct si_sampler_state {
 159 #ifdef DEBUG
 160         unsigned                        magic;
 161 #endif
 162         uint32_t                        val[4];
 163 };
 164
 165 struct si_cs_shader_state {
 166         struct si_compute               *program;
 167         struct si_compute               *emitted_program;
 168         unsigned                        offset;
 169         bool                            initialized;
 170         bool                            uses_scratch;
 171 };
 172
 173 struct si_textures_info {
 174         struct si_sampler_views         views;
 175         uint32_t                        needs_depth_decompress_mask;
 176         uint32_t                        needs_color_decompress_mask;
 177 };
 178
 179 struct si_images_info {
 180         struct pipe_image_view          views[SI_NUM_IMAGES];
 181         uint32_t                        needs_color_decompress_mask;
 182         unsigned                        enabled_mask;
 183 };
 184
 185 struct si_framebuffer {
 186         struct r600_atom                atom;
 187         struct pipe_framebuffer_state   state;
 188         unsigned                        colorbuf_enabled_4bit;
 189         unsigned                        spi_shader_col_format;
 190         unsigned                        spi_shader_col_format_alpha;
 191         unsigned                        spi_shader_col_format_blend;
 192         unsigned                        spi_shader_col_format_blend_alpha;
 193         ubyte                           nr_samples:5; /* at most 16xAA */
 194         ubyte                           log_samples:3; /* at most 4 = 16xAA */
 195         ubyte                           compressed_cb_mask;
 196         ubyte                           color_is_int8;
 197         ubyte                           color_is_int10;
 198         ubyte                           dirty_cbufs;
 199         bool                            dirty_zsbuf;
 200         bool                            any_dst_linear;
 201 };
 202
 203 struct si_clip_state {
 204         struct r600_atom                atom;
 205         struct pipe_clip_state          state;
 206         bool                            any_nonzeros;
 207 };
 208
 209 struct si_sample_locs {
 210         struct r600_atom        atom;
 211         unsigned                nr_samples;
 212 };
 213
 214 struct si_sample_mask {
 215         struct r600_atom        atom;
 216         uint16_t                sample_mask;
 217 };
 218
 219 /* A shader state consists of the shader selector, which is a constant state
 220  * object shared by multiple contexts and shouldn't be modified, and
 221  * the current shader variant selected for this context.
 222  */
 223 struct si_shader_ctx_state {
 224         struct si_shader_selector       *cso;
 225         struct si_shader                *current;
 226 };
 227
 228 #define SI_NUM_VGT_PARAM_KEY_BITS 12
 229 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
 230
 231 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
 232  * Some fields are set by state-change calls, most are set by draw_vbo.
 233  */
 234 union si_vgt_param_key {
 235         struct {
 236                 unsigned prim:4;
 237                 unsigned uses_instancing:1;
 238                 unsigned multi_instances_smaller_than_primgroup:1;
 239                 unsigned primitive_restart:1;
 240                 unsigned count_from_stream_output:1;
 241                 unsigned line_stipple_enabled:1;
 242                 unsigned uses_tess:1;
 243                 unsigned tess_uses_prim_id:1;
 244                 unsigned uses_gs:1;
 245                 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
 246         } u;
 247         uint32_t index;
 248 };
 249
 250 struct si_texture_handle
 251 {
 252         unsigned                        desc_slot;
 253         bool                            desc_dirty;
 254         struct pipe_sampler_view        *view;
 255         struct si_sampler_state         sstate;
 256 };
 257
 258 struct si_image_handle
 259 {
 260         unsigned                        desc_slot;
 261         bool                            desc_dirty;
 262         struct pipe_image_view          view;
 263 };
 264
 265 struct si_saved_cs {
 266         struct pipe_reference   reference;
 267         struct si_context       *ctx;
 268         struct radeon_saved_cs  gfx;
 269         struct r600_resource    *trace_buf;
 270         unsigned                trace_id;
 271
 272         unsigned                gfx_last_dw;
 273         bool                    flushed;
 274 };
 275
 276 struct si_context {
 277         struct r600_common_context      b;
 278         struct blitter_context          *blitter;
 279         void                            *custom_dsa_flush;
 280         void                            *custom_blend_resolve;
 281         void                            *custom_blend_fmask_decompress;
 282         void                            *custom_blend_eliminate_fastclear;
 283         void                            *custom_blend_dcc_decompress;
 284         struct si_screen                *screen;
 285         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 286         struct si_shader_ctx_state      fixed_func_tcs_shader;
 287         struct r600_resource            *wait_mem_scratch;
 288         unsigned                        wait_mem_number;
 289         uint16_t                        prefetch_L2_mask;
 290
 291         bool                            gfx_flush_in_progress:1;
 292         bool                            compute_is_busy:1;
 293
 294         /* Atoms (direct states). */
 295         union si_state_atoms            atoms;
 296         unsigned                        dirty_atoms; /* mask */
 297         /* PM4 states (precomputed immutable states) */
 298         unsigned                        dirty_states;
 299         union si_state                  queued;
 300         union si_state                  emitted;
 301
 302         /* Atom declarations. */
 303         struct si_framebuffer           framebuffer;
 304         struct si_sample_locs           msaa_sample_locs;
 305         struct r600_atom                db_render_state;
 306         struct r600_atom                msaa_config;
 307         struct si_sample_mask           sample_mask;
 308         struct r600_atom                cb_render_state;
 309         unsigned                        last_cb_target_mask;
 310         struct si_blend_color           blend_color;
 311         struct r600_atom                clip_regs;
 312         struct si_clip_state            clip_state;
 313         struct si_shader_data           shader_pointers;
 314         struct si_stencil_ref           stencil_ref;
 315         struct r600_atom                spi_map;
 316
 317         /* Precomputed states. */
 318         struct si_pm4_state             *init_config;
 319         struct si_pm4_state             *init_config_gs_rings;
 320         bool                            init_config_has_vgt_flush;
 321         struct si_pm4_state             *vgt_shader_config[4];
 322
 323         /* shaders */
 324         struct si_shader_ctx_state      ps_shader;
 325         struct si_shader_ctx_state      gs_shader;
 326         struct si_shader_ctx_state      vs_shader;
 327         struct si_shader_ctx_state      tcs_shader;
 328         struct si_shader_ctx_state      tes_shader;
 329         struct si_cs_shader_state       cs_shader_state;
 330
 331         /* shader information */
 332         struct si_vertex_elements       *vertex_elements;
 333         unsigned                        sprite_coord_enable;
 334         bool                            flatshade;
 335         bool                            do_update_shaders;
 336
 337         /* shader descriptors */
 338         struct si_descriptors           vertex_buffers;
 339         struct si_descriptors           descriptors[SI_NUM_DESCS];
 340         unsigned                        descriptors_dirty;
 341         unsigned                        shader_pointers_dirty;
 342         unsigned                        shader_needs_decompress_mask;
 343         struct si_buffer_resources      rw_buffers;
 344         struct si_buffer_resources      const_and_shader_buffers[SI_NUM_SHADERS];
 345         struct si_textures_info         samplers[SI_NUM_SHADERS];
 346         struct si_images_info           images[SI_NUM_SHADERS];
 347
 348         /* other shader resources */
 349         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 350         struct pipe_resource            *esgs_ring;
 351         struct pipe_resource            *gsvs_ring;
 352         struct pipe_resource            *tf_ring;
 353         struct pipe_resource            *tess_offchip_ring;
 354         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 355         struct r600_resource            *border_color_buffer;
 356         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 357         unsigned                        border_color_count;
 358
 359         /* Vertex and index buffers. */
 360         bool                            vertex_buffers_dirty;
 361         bool                            vertex_buffer_pointer_dirty;
 362         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 363
 364         /* MSAA config state. */
 365         int                             ps_iter_samples;
 366         bool                            smoothing_enabled;
 367
 368         /* DB render state. */
 369         unsigned                ps_db_shader_control;
 370         unsigned                dbcb_copy_sample;
 371         bool                    dbcb_depth_copy_enabled:1;
 372         bool                    dbcb_stencil_copy_enabled:1;
 373         bool                    db_flush_depth_inplace:1;
 374         bool                    db_flush_stencil_inplace:1;
 375         bool                    db_depth_clear:1;
 376         bool                    db_depth_disable_expclear:1;
 377         bool                    db_stencil_clear:1;
 378         bool                    db_stencil_disable_expclear:1;
 379         bool                    occlusion_queries_disabled:1;
 380         bool                    generate_mipmap_for_depth:1;
 381
 382         /* Emitted draw state. */
 383         bool                    gs_tri_strip_adj_fix:1;
 384         int                     last_index_size;
 385         int                     last_base_vertex;
 386         int                     last_start_instance;
 387         int                     last_drawid;
 388         int                     last_sh_base_reg;
 389         int                     last_primitive_restart_en;
 390         int                     last_restart_index;
 391         int                     last_gs_out_prim;
 392         int                     last_prim;
 393         int                     last_multi_vgt_param;
 394         int                     last_rast_prim;
 395         unsigned                last_sc_line_stipple;
 396         unsigned                current_vs_state;
 397         unsigned                last_vs_state;
 398         enum pipe_prim_type     current_rast_prim; /* primitive type after TES, GS */
 399
 400         /* Scratch buffer */
 401         struct r600_atom        scratch_state;
 402         struct r600_resource    *scratch_buffer;
 403         unsigned                scratch_waves;
 404         unsigned                spi_tmpring_size;
 405
 406         struct r600_resource    *compute_scratch_buffer;
 407
 408         /* Emitted derived tessellation state. */
 409         /* Local shader (VS), or HS if LS-HS are merged. */
 410         struct si_shader        *last_ls;
 411         struct si_shader_selector *last_tcs;
 412         int                     last_num_tcs_input_cp;
 413         int                     last_tes_sh_base;
 414         bool                    last_tess_uses_primid;
 415         unsigned                last_num_patches;
 416
 417         /* Debug state. */
 418         bool                    is_debug;
 419         struct si_saved_cs      *current_saved_cs;
 420         uint64_t                dmesg_timestamp;
 421         unsigned                apitrace_call_number;
 422
 423         /* Other state */
 424         bool need_check_render_feedback;
 425         bool                    decompression_enabled;
 426
 427         /* Precomputed IA_MULTI_VGT_PARAM */
 428         union si_vgt_param_key  ia_multi_vgt_param_key;
 429         unsigned                ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
 430
 431         /* Bindless descriptors. */
 432         struct si_descriptors   bindless_descriptors;
 433         struct util_idalloc     bindless_used_slots;
 434         unsigned                num_bindless_descriptors;
 435         bool                    bindless_descriptors_dirty;
 436         bool                    graphics_bindless_pointer_dirty;
 437         bool                    compute_bindless_pointer_dirty;
 438
 439         /* Allocated bindless handles */
 440         struct hash_table       *tex_handles;
 441         struct hash_table       *img_handles;
 442
 443         /* Resident bindless handles */
 444         struct util_dynarray    resident_tex_handles;
 445         struct util_dynarray    resident_img_handles;
 446
 447         /* Resident bindless handles which need decompression */
 448         struct util_dynarray    resident_tex_needs_color_decompress;
 449         struct util_dynarray    resident_img_needs_color_decompress;
 450         struct util_dynarray    resident_tex_needs_depth_decompress;
 451
 452         /* Bindless state */
 453         bool                    uses_bindless_samplers;
 454         bool                    uses_bindless_images;
 455 };
 456
 457 /* cik_sdma.c */
 458 void cik_init_sdma_functions(struct si_context *sctx);
 459
 460 /* si_blit.c */
 461 void si_init_blit_functions(struct si_context *sctx);
 462 void si_decompress_graphics_textures(struct si_context *sctx);
 463 void si_decompress_compute_textures(struct si_context *sctx);
 464 void si_resource_copy_region(struct pipe_context *ctx,
 465                              struct pipe_resource *dst,
 466                              unsigned dst_level,
 467                              unsigned dstx, unsigned dsty, unsigned dstz,
 468                              struct pipe_resource *src,
 469                              unsigned src_level,
 470                              const struct pipe_box *src_box);
 471
 472 /* si_cp_dma.c */
 473 #define SI_CPDMA_SKIP_CHECK_CS_SPACE    (1 << 0) /* don't call need_cs_space */
 474 #define SI_CPDMA_SKIP_SYNC_AFTER        (1 << 1) /* don't wait for DMA after the copy */
 475 #define SI_CPDMA_SKIP_SYNC_BEFORE       (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
 476 #define SI_CPDMA_SKIP_GFX_SYNC          (1 << 3) /* don't flush caches and don't wait for PS/CS */
 477 #define SI_CPDMA_SKIP_BO_LIST_UPDATE    (1 << 4) /* don't update the BO list */
 478 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
 479                            SI_CPDMA_SKIP_SYNC_AFTER | \
 480                            SI_CPDMA_SKIP_SYNC_BEFORE | \
 481                            SI_CPDMA_SKIP_GFX_SYNC | \
 482                            SI_CPDMA_SKIP_BO_LIST_UPDATE)
 483
 484 void si_copy_buffer(struct si_context *sctx,
 485                     struct pipe_resource *dst, struct pipe_resource *src,
 486                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 487                     unsigned user_flags);
 488 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 489                               uint64_t offset, unsigned size);
 490 void cik_emit_prefetch_L2(struct si_context *sctx);
 491 void si_init_cp_dma_functions(struct si_context *sctx);
 492
 493 /* si_debug.c */
 494 void si_auto_log_cs(void *data, struct u_log_context *log);
 495 void si_log_hw_flush(struct si_context *sctx);
 496 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
 497 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
 498 void si_init_debug_functions(struct si_context *sctx);
 499 void si_check_vm_faults(struct r600_common_context *ctx,
 500                         struct radeon_saved_cs *saved, enum ring_type ring);
 501 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
 502
 503 /* si_dma.c */
 504 void si_init_dma_functions(struct si_context *sctx);
 505
 506 /* si_hw_context.c */
 507 void si_destroy_saved_cs(struct si_saved_cs *scs);
 508 void si_context_gfx_flush(void *context, unsigned flags,
 509                           struct pipe_fence_handle **fence);
 510 void si_begin_new_cs(struct si_context *ctx);
 511 void si_need_cs_space(struct si_context *ctx);
 512
 513 /* si_compute.c */
 514 void si_init_compute_functions(struct si_context *sctx);
 515
 516 /* si_perfcounters.c */
 517 void si_init_perfcounters(struct si_screen *screen);
 518
 519 /* si_uvd.c */
 520 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 521                                                const struct pipe_video_codec *templ);
 522
 523 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 524                                                  const struct pipe_video_buffer *tmpl);
 525
 526 /*
 527  * common helpers
 528  */
 529
 530 static inline void
 531 si_invalidate_draw_sh_constants(struct si_context *sctx)
 532 {
 533         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 534 }
 535
 536 static inline void
 537 si_set_atom_dirty(struct si_context *sctx,
 538                   struct r600_atom *atom, bool dirty)
 539 {
 540         unsigned bit = 1 << atom->id;
 541
 542         if (dirty)
 543                 sctx->dirty_atoms |= bit;
 544         else
 545                 sctx->dirty_atoms &= ~bit;
 546 }
 547
 548 static inline bool
 549 si_is_atom_dirty(struct si_context *sctx,
 550                   struct r600_atom *atom)
 551 {
 552         unsigned bit = 1 << atom->id;
 553
 554         return sctx->dirty_atoms & bit;
 555 }
 556
 557 static inline void
 558 si_mark_atom_dirty(struct si_context *sctx,
 559                    struct r600_atom *atom)
 560 {
 561         si_set_atom_dirty(sctx, atom, true);
 562 }
 563
 564 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
 565 {
 566         if (sctx->gs_shader.cso)
 567                 return &sctx->gs_shader;
 568         if (sctx->tes_shader.cso)
 569                 return &sctx->tes_shader;
 570
 571         return &sctx->vs_shader;
 572 }
 573
 574 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 575 {
 576         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 577
 578         return vs->cso ? &vs->cso->info : NULL;
 579 }
 580
 581 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 582 {
 583         if (sctx->gs_shader.cso)
 584                 return sctx->gs_shader.cso->gs_copy_shader;
 585
 586         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 587         return vs->current ? vs->current : NULL;
 588 }
 589
 590 static inline unsigned
 591 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
 592 {
 593         unsigned alignment, tcc_cache_line_size;
 594
 595         /* If the upload size is less than the cache line size (e.g. 16, 32),
 596          * the whole thing will fit into a cache line if we align it to its size.
 597          * The idea is that multiple small uploads can share a cache line.
 598          * If the upload size is greater, align it to the cache line size.
 599          */
 600         alignment = util_next_power_of_two(upload_size);
 601         tcc_cache_line_size = sctx->screen->b.info.tcc_cache_line_size;
 602         return MIN2(alignment, tcc_cache_line_size);
 603 }
 604
 605 static inline void
 606 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
 607 {
 608         if (pipe_reference(&(*dst)->reference, &src->reference))
 609                 si_destroy_saved_cs(*dst);
 610
 611         *dst = src;
 612 }
 613
 614 #endif