2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "si_shader.h"
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
38 #define SI_BIG_ENDIAN 0
41 #define ATI_VENDOR_ID 0x1002
43 #define SI_NOT_QUERY 0xffffffff
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_NUM_SMOOTH_AA_SAMPLES 8
51 #define SI_GS_PER_ES 128
52 /* Alignment for optimal CP DMA performance. */
53 #define SI_CPDMA_ALIGNMENT 32
55 /* Tunables for compute-based clear_buffer and copy_buffer: */
56 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
57 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
58 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
60 /* Pipeline & streamout query controls. */
61 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
62 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
63 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
64 /* Instruction cache. */
65 #define SI_CONTEXT_INV_ICACHE (1 << 3)
66 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
67 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
68 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
69 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
70 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
71 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
72 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
73 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
74 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
75 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
76 * a CB or DB flush. */
77 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
78 /* Framebuffer caches. */
79 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
80 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
81 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
82 /* Engine synchronization. */
83 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
84 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
85 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
86 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
87 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
89 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
90 #define SI_PREFETCH_LS (1 << 1)
91 #define SI_PREFETCH_HS (1 << 2)
92 #define SI_PREFETCH_ES (1 << 3)
93 #define SI_PREFETCH_GS (1 << 4)
94 #define SI_PREFETCH_VS (1 << 5)
95 #define SI_PREFETCH_PS (1 << 6)
97 #define SI_MAX_BORDER_COLORS 4096
98 #define SI_MAX_VIEWPORTS 16
100 #define SI_MAP_BUFFER_ALIGNMENT 64
101 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
103 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
104 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
105 #define SI_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
106 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
107 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
108 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
109 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
110 #define SI_RESOURCE_FLAG_SO_FILLED_SIZE (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
114 /* Shader logging options: */
115 DBG_VS
= PIPE_SHADER_VERTEX
,
116 DBG_PS
= PIPE_SHADER_FRAGMENT
,
117 DBG_GS
= PIPE_SHADER_GEOMETRY
,
118 DBG_TCS
= PIPE_SHADER_TESS_CTRL
,
119 DBG_TES
= PIPE_SHADER_TESS_EVAL
,
120 DBG_CS
= PIPE_SHADER_COMPUTE
,
126 /* Shader compiler options the shader cache should be aware of: */
127 DBG_FS_CORRECT_DERIVS_AFTER_KILL
,
132 /* Shader compiler options (with no effect on the shader cache): */
135 DBG_MONOLITHIC_SHADERS
,
138 /* Information logging options: */
144 /* Driver options: */
152 /* 3D engine options: */
172 DBG_TEST_VMFAULT_SDMA
,
173 DBG_TEST_VMFAULT_SHADER
,
178 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
179 #define DBG(name) (1ull << DBG_##name)
181 enum si_cache_policy
{
183 L2_STREAM
, /* same as SLC=1 */
184 L2_LRU
, /* same as SLC=0 */
188 SI_COHERENCY_NONE
, /* no cache flushes needed */
190 SI_COHERENCY_CB_META
,
196 struct u_suballocator
;
198 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
201 struct r600_resource
{
202 struct threaded_resource b
;
204 /* Winsys objects. */
205 struct pb_buffer
*buf
;
206 uint64_t gpu_address
;
207 /* Memory usage if the buffer placement is optimal. */
211 /* Resource properties. */
213 unsigned bo_alignment
;
214 enum radeon_bo_domain domains
;
215 enum radeon_bo_flag flags
;
216 unsigned bind_history
;
217 int max_forced_staging_uploads
;
219 /* The buffer range which is initialized (with a write transfer,
220 * streamout, DMA, or as a random access target). The rest of
221 * the buffer is considered invalid and can be mapped unsynchronized.
223 * This allows unsychronized mapping of a buffer range which hasn't
224 * been used yet. It's for applications which forget to use
225 * the unsynchronized map flag and expect the driver to figure it out.
227 struct util_range valid_buffer_range
;
229 /* For buffers only. This indicates that a write operation has been
230 * performed by TC L2, but the cache hasn't been flushed.
231 * Any hw block which doesn't use or bypasses TC L2 should check this
232 * flag and flush the cache before using the buffer.
234 * For example, TC L2 must be flushed if a buffer which has been
235 * modified by a shader store instruction is about to be used as
236 * an index buffer. The reason is that VGT DMA index fetching doesn't
241 /* Whether this resource is referenced by bindless handles. */
242 bool texture_handle_allocated
;
243 bool image_handle_allocated
;
245 /* Whether the resource has been exported via resource_get_handle. */
246 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
250 struct threaded_transfer b
;
251 struct r600_resource
*staging
;
256 struct r600_resource buffer
;
258 struct radeon_surf surface
;
260 struct si_texture
*flushed_depth_texture
;
262 /* Colorbuffer compression and fast clear. */
263 uint64_t fmask_offset
;
264 uint64_t cmask_offset
;
265 uint64_t cmask_base_address_reg
;
266 struct r600_resource
*cmask_buffer
;
267 uint64_t dcc_offset
; /* 0 = disabled */
268 unsigned cb_color_info
; /* fast clear enable bit */
269 unsigned color_clear_value
[2];
270 unsigned last_msaa_resolve_target_micro_mode
;
271 unsigned num_level0_transfers
;
273 /* Depth buffer compression and fast clear. */
274 uint64_t htile_offset
;
275 float depth_clear_value
;
276 uint16_t dirty_level_mask
; /* each bit says if that mipmap is compressed */
277 uint16_t stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
278 enum pipe_format db_render_format
:16;
279 uint8_t stencil_clear_value
;
280 bool tc_compatible_htile
:1;
281 bool depth_cleared
:1; /* if it was cleared at least once */
282 bool stencil_cleared
:1; /* if it was cleared at least once */
283 bool upgraded_depth
:1; /* upgraded from unorm to Z32_FLOAT */
285 bool db_compatible
:1;
289 /* We need to track DCC dirtiness, because st/dri usually calls
290 * flush_resource twice per frame (not a bug) and we don't wanna
291 * decompress DCC twice. Also, the dirty tracking must be done even
292 * if DCC isn't used, because it's required by the DCC usage analysis
293 * for a possible future enablement.
295 bool separate_dcc_dirty
:1;
296 /* Statistics gathering for the DCC enablement heuristic. */
297 bool dcc_gather_statistics
:1;
298 /* Counter that should be non-zero if the texture is bound to a
301 unsigned framebuffers_bound
;
302 /* Whether the texture is a displayable back buffer and needs DCC
303 * decompression, which is expensive. Therefore, it's enabled only
304 * if statistics suggest that it will pay off and it's allocated
305 * separately. It can't be bound as a sampler by apps. Limited to
306 * target == 2D and last_level == 0. If enabled, dcc_offset contains
307 * the absolute GPUVM address, not the relative one.
309 struct r600_resource
*dcc_separate_buffer
;
310 /* When DCC is temporarily disabled, the separate buffer is here. */
311 struct r600_resource
*last_dcc_separate_buffer
;
312 /* Estimate of how much this color buffer is written to in units of
313 * full-screen draws: ps_invocations / (width * height)
314 * Shader kills, late Z, and blending with trivial discards make it
315 * inaccurate (we need to count CB updates, not PS invocations).
317 unsigned ps_draw_ratio
;
318 /* The number of clears since the last DCC usage analysis. */
319 unsigned num_slow_clears
;
323 struct pipe_surface base
;
325 /* These can vary with block-compressed textures. */
329 bool color_initialized
:1;
330 bool depth_initialized
:1;
332 /* Misc. color flags. */
333 bool color_is_int8
:1;
334 bool color_is_int10
:1;
335 bool dcc_incompatible
:1;
337 /* Color registers. */
338 unsigned cb_color_info
;
339 unsigned cb_color_view
;
340 unsigned cb_color_attrib
;
341 unsigned cb_color_attrib2
; /* GFX9 and later */
342 unsigned cb_dcc_control
; /* VI and later */
343 unsigned spi_shader_col_format
:8; /* no blending, no alpha-to-coverage. */
344 unsigned spi_shader_col_format_alpha
:8; /* alpha-to-coverage */
345 unsigned spi_shader_col_format_blend
:8; /* blending without alpha. */
346 unsigned spi_shader_col_format_blend_alpha
:8; /* blending with alpha. */
349 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE */
350 uint64_t db_stencil_base
;
351 uint64_t db_htile_data_base
;
352 unsigned db_depth_info
;
354 unsigned db_z_info2
; /* GFX9+ */
355 unsigned db_depth_view
;
356 unsigned db_depth_size
;
357 unsigned db_depth_slice
;
358 unsigned db_stencil_info
;
359 unsigned db_stencil_info2
; /* GFX9+ */
360 unsigned db_htile_surface
;
363 struct si_mmio_counter
{
368 union si_mmio_counters
{
370 /* For global GPU load including SDMA. */
371 struct si_mmio_counter gpu
;
374 struct si_mmio_counter spi
;
375 struct si_mmio_counter gui
;
376 struct si_mmio_counter ta
;
377 struct si_mmio_counter gds
;
378 struct si_mmio_counter vgt
;
379 struct si_mmio_counter ia
;
380 struct si_mmio_counter sx
;
381 struct si_mmio_counter wd
;
382 struct si_mmio_counter bci
;
383 struct si_mmio_counter sc
;
384 struct si_mmio_counter pa
;
385 struct si_mmio_counter db
;
386 struct si_mmio_counter cp
;
387 struct si_mmio_counter cb
;
390 struct si_mmio_counter sdma
;
393 struct si_mmio_counter pfp
;
394 struct si_mmio_counter meq
;
395 struct si_mmio_counter me
;
396 struct si_mmio_counter surf_sync
;
397 struct si_mmio_counter cp_dma
;
398 struct si_mmio_counter scratch_ram
;
403 struct si_memory_object
{
404 struct pipe_memory_object b
;
405 struct pb_buffer
*buf
;
409 /* Saved CS data for debugging features. */
410 struct radeon_saved_cs
{
414 struct radeon_bo_list_item
*bo_list
;
419 struct pipe_screen b
;
420 struct radeon_winsys
*ws
;
421 struct disk_cache
*disk_shader_cache
;
423 struct radeon_info info
;
424 uint64_t debug_flags
;
425 char renderer_string
[183];
427 unsigned pa_sc_raster_config
;
428 unsigned pa_sc_raster_config_1
;
429 unsigned se_tile_repeat
;
430 unsigned gs_table_depth
;
431 unsigned tess_offchip_block_dw_size
;
432 unsigned tess_offchip_ring_size
;
433 unsigned tess_factor_ring_size
;
434 unsigned vgt_hs_offchip_param
;
435 unsigned eqaa_force_coverage_samples
;
436 unsigned eqaa_force_z_samples
;
437 unsigned eqaa_force_color_samples
;
438 bool has_clear_state
;
439 bool has_distributed_tess
;
440 bool has_draw_indirect_multi
;
441 bool has_out_of_order_rast
;
442 bool assume_no_z_fights
;
443 bool commutative_blend_add
;
444 bool clear_db_cache_before_clear
;
445 bool has_msaa_sample_loc_bug
;
446 bool has_ls_vgpr_init_bug
;
449 bool llvm_has_working_vgpr_indexing
;
451 /* Whether shaders are monolithic (1-part) or separate (3-part). */
452 bool use_monolithic_shaders
;
454 bool has_rbplus
; /* if RB+ registers exist */
455 bool rbplus_allowed
; /* if RB+ is allowed */
456 bool dcc_msaa_allowed
;
457 bool cpdma_prefetch_writes_memory
;
459 struct slab_parent_pool pool_transfers
;
461 /* Texture filter settings. */
462 int force_aniso
; /* -1 = disabled */
464 /* Auxiliary context. Mainly used to initialize resources.
465 * It must be locked prior to using and flushed before unlocking. */
466 struct pipe_context
*aux_context
;
467 mtx_t aux_context_lock
;
469 /* This must be in the screen, because UE4 uses one context for
470 * compilation and another one for rendering.
472 unsigned num_compilations
;
473 /* Along with ST_DEBUG=precompile, this should show if applications
474 * are loading shaders on demand. This is a monotonic counter.
476 unsigned num_shaders_created
;
477 unsigned num_shader_cache_hits
;
479 /* GPU load thread. */
480 mtx_t gpu_load_mutex
;
481 thrd_t gpu_load_thread
;
482 union si_mmio_counters mmio_counters
;
483 volatile unsigned gpu_load_stop_thread
; /* bool */
485 /* Performance counters. */
486 struct si_perfcounters
*perfcounters
;
488 /* If pipe_screen wants to recompute and re-emit the framebuffer,
489 * sampler, and image states of all contexts, it should atomically
492 * Each context will compare this with its own last known value of
493 * the counter before drawing and re-emit the states accordingly.
495 unsigned dirty_tex_counter
;
497 /* Atomically increment this counter when an existing texture's
498 * metadata is enabled or disabled in a way that requires changing
499 * contexts' compressed texture binding masks.
501 unsigned compressed_colortex_counter
;
504 /* Context flags to set so that all writes from earlier jobs
505 * in the CP are seen by L2 clients.
509 /* Context flags to set so that all writes from earlier jobs
510 * that end in L2 are seen by CP.
515 mtx_t shader_parts_mutex
;
516 struct si_shader_part
*vs_prologs
;
517 struct si_shader_part
*tcs_epilogs
;
518 struct si_shader_part
*gs_prologs
;
519 struct si_shader_part
*ps_prologs
;
520 struct si_shader_part
*ps_epilogs
;
522 /* Shader cache in memory.
524 * Design & limitations:
525 * - The shader cache is per screen (= per process), never saved to
526 * disk, and skips redundant shader compilations from TGSI to bytecode.
527 * - It can only be used with one-variant-per-shader support, in which
528 * case only the main (typically middle) part of shaders is cached.
529 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
530 * variants of VS and TES are cached, so LS and ES aren't.
531 * - GS and CS aren't cached, but it's certainly possible to cache
534 mtx_t shader_cache_mutex
;
535 struct hash_table
*shader_cache
;
537 /* Shader compiler queue for multithreaded compilation. */
538 struct util_queue shader_compiler_queue
;
539 /* Use at most 3 normal compiler threads on quadcore and better.
540 * Hyperthreaded CPUs report the number of threads, but we want
541 * the number of cores. We only need this many threads for shader-db. */
542 struct ac_llvm_compiler compiler
[24]; /* used by the queue only */
544 struct util_queue shader_compiler_queue_low_priority
;
545 /* Use at most 2 low priority threads on quadcore and better.
546 * We want to minimize the impact on multithreaded Mesa. */
547 struct ac_llvm_compiler compiler_lowp
[10];
550 struct si_blend_color
{
551 struct pipe_blend_color state
;
555 struct si_sampler_view
{
556 struct pipe_sampler_view base
;
557 /* [0..7] = image descriptor
558 * [4..7] = buffer descriptor */
560 uint32_t fmask_state
[8];
561 const struct legacy_surf_level
*base_level_info
;
564 bool is_stencil_sampler
;
566 bool dcc_incompatible
;
569 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
571 struct si_sampler_state
{
576 uint32_t integer_val
[4];
577 uint32_t upgraded_depth_val
[4];
580 struct si_cs_shader_state
{
581 struct si_compute
*program
;
582 struct si_compute
*emitted_program
;
589 struct pipe_sampler_view
*views
[SI_NUM_SAMPLERS
];
590 struct si_sampler_state
*sampler_states
[SI_NUM_SAMPLERS
];
592 /* The i-th bit is set if that element is enabled (non-NULL resource). */
593 unsigned enabled_mask
;
594 uint32_t needs_depth_decompress_mask
;
595 uint32_t needs_color_decompress_mask
;
599 struct pipe_image_view views
[SI_NUM_IMAGES
];
600 uint32_t needs_color_decompress_mask
;
601 unsigned enabled_mask
;
604 struct si_framebuffer
{
605 struct pipe_framebuffer_state state
;
606 unsigned colorbuf_enabled_4bit
;
607 unsigned spi_shader_col_format
;
608 unsigned spi_shader_col_format_alpha
;
609 unsigned spi_shader_col_format_blend
;
610 unsigned spi_shader_col_format_blend_alpha
;
611 ubyte nr_samples
:5; /* at most 16xAA */
612 ubyte log_samples
:3; /* at most 4 = 16xAA */
613 ubyte nr_color_samples
; /* at most 8xAA */
614 ubyte compressed_cb_mask
;
615 ubyte uncompressed_cb_mask
;
617 ubyte color_is_int10
;
621 bool CB_has_shader_readable_metadata
;
622 bool DB_has_shader_readable_metadata
;
626 /* This is the list we want to support. */
627 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH
,
628 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH
,
629 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH
,
632 struct si_signed_scissor
{
637 enum si_quant_mode quant_mode
;
642 struct pipe_scissor_state states
[SI_MAX_VIEWPORTS
];
645 struct si_viewports
{
647 unsigned depth_range_dirty_mask
;
648 struct pipe_viewport_state states
[SI_MAX_VIEWPORTS
];
649 struct si_signed_scissor as_scissor
[SI_MAX_VIEWPORTS
];
652 struct si_clip_state
{
653 struct pipe_clip_state state
;
657 struct si_streamout_target
{
658 struct pipe_stream_output_target b
;
660 /* The buffer where BUFFER_FILLED_SIZE is stored. */
661 struct r600_resource
*buf_filled_size
;
662 unsigned buf_filled_size_offset
;
663 bool buf_filled_size_valid
;
665 unsigned stride_in_dw
;
668 struct si_streamout
{
671 unsigned enabled_mask
;
672 unsigned num_targets
;
673 struct si_streamout_target
*targets
[PIPE_MAX_SO_BUFFERS
];
675 unsigned append_bitmask
;
678 /* External state which comes from the vertex shader,
679 * it must be set explicitly when binding a shader. */
680 uint16_t *stride_in_dw
;
681 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
683 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
684 unsigned hw_enabled_mask
;
686 /* The state of VGT_STRMOUT_(CONFIG|EN). */
687 bool streamout_enabled
;
688 bool prims_gen_query_enabled
;
689 int num_prims_gen_queries
;
692 /* A shader state consists of the shader selector, which is a constant state
693 * object shared by multiple contexts and shouldn't be modified, and
694 * the current shader variant selected for this context.
696 struct si_shader_ctx_state
{
697 struct si_shader_selector
*cso
;
698 struct si_shader
*current
;
701 #define SI_NUM_VGT_PARAM_KEY_BITS 12
702 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
704 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
705 * Some fields are set by state-change calls, most are set by draw_vbo.
707 union si_vgt_param_key
{
709 #ifdef PIPE_ARCH_LITTLE_ENDIAN
711 unsigned uses_instancing
:1;
712 unsigned multi_instances_smaller_than_primgroup
:1;
713 unsigned primitive_restart
:1;
714 unsigned count_from_stream_output
:1;
715 unsigned line_stipple_enabled
:1;
716 unsigned uses_tess
:1;
717 unsigned tess_uses_prim_id
:1;
719 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
720 #else /* PIPE_ARCH_BIG_ENDIAN */
721 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
723 unsigned tess_uses_prim_id
:1;
724 unsigned uses_tess
:1;
725 unsigned line_stipple_enabled
:1;
726 unsigned count_from_stream_output
:1;
727 unsigned primitive_restart
:1;
728 unsigned multi_instances_smaller_than_primgroup
:1;
729 unsigned uses_instancing
:1;
736 struct si_texture_handle
740 struct pipe_sampler_view
*view
;
741 struct si_sampler_state sstate
;
744 struct si_image_handle
748 struct pipe_image_view view
;
752 struct pipe_reference reference
;
753 struct si_context
*ctx
;
754 struct radeon_saved_cs gfx
;
755 struct r600_resource
*trace_buf
;
758 unsigned gfx_last_dw
;
764 struct pipe_context b
; /* base class */
766 enum radeon_family family
;
767 enum chip_class chip_class
;
769 struct radeon_winsys
*ws
;
770 struct radeon_winsys_ctx
*ctx
;
771 struct radeon_cmdbuf
*gfx_cs
;
772 struct radeon_cmdbuf
*dma_cs
;
773 struct pipe_fence_handle
*last_gfx_fence
;
774 struct pipe_fence_handle
*last_sdma_fence
;
775 struct r600_resource
*eop_bug_scratch
;
776 struct u_upload_mgr
*cached_gtt_allocator
;
777 struct threaded_context
*tc
;
778 struct u_suballocator
*allocator_zeroed_memory
;
779 struct slab_child_pool pool_transfers
;
780 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
781 struct pipe_device_reset_callback device_reset_callback
;
782 struct u_log_context
*log
;
783 void *query_result_shader
;
784 struct blitter_context
*blitter
;
785 void *custom_dsa_flush
;
786 void *custom_blend_resolve
;
787 void *custom_blend_fmask_decompress
;
788 void *custom_blend_eliminate_fastclear
;
789 void *custom_blend_dcc_decompress
;
791 void *vs_blit_pos_layered
;
793 void *vs_blit_color_layered
;
794 void *vs_blit_texcoord
;
795 void *cs_clear_buffer
;
796 void *cs_copy_buffer
;
797 struct si_screen
*screen
;
798 struct pipe_debug_callback debug
;
799 struct ac_llvm_compiler compiler
; /* only non-threaded compilation */
800 struct si_shader_ctx_state fixed_func_tcs_shader
;
801 struct r600_resource
*wait_mem_scratch
;
802 unsigned wait_mem_number
;
803 uint16_t prefetch_L2_mask
;
805 bool gfx_flush_in_progress
:1;
806 bool gfx_last_ib_is_busy
:1;
807 bool compute_is_busy
:1;
809 unsigned num_gfx_cs_flushes
;
810 unsigned initial_gfx_cs_size
;
811 unsigned gpu_reset_counter
;
812 unsigned last_dirty_tex_counter
;
813 unsigned last_compressed_colortex_counter
;
814 unsigned last_num_draw_calls
;
815 unsigned flags
; /* flush flags */
816 /* Current unaccounted memory usage. */
820 /* Atoms (direct states). */
821 union si_state_atoms atoms
;
822 unsigned dirty_atoms
; /* mask */
823 /* PM4 states (precomputed immutable states) */
824 unsigned dirty_states
;
825 union si_state queued
;
826 union si_state emitted
;
828 /* Atom declarations. */
829 struct si_framebuffer framebuffer
;
830 unsigned sample_locs_num_samples
;
831 uint16_t sample_mask
;
832 unsigned last_cb_target_mask
;
833 struct si_blend_color blend_color
;
834 struct si_clip_state clip_state
;
835 struct si_shader_data shader_pointers
;
836 struct si_stencil_ref stencil_ref
;
837 struct si_scissors scissors
;
838 struct si_streamout streamout
;
839 struct si_viewports viewports
;
840 unsigned num_window_rectangles
;
841 bool window_rectangles_include
;
842 struct pipe_scissor_state window_rectangles
[4];
844 /* Precomputed states. */
845 struct si_pm4_state
*init_config
;
846 struct si_pm4_state
*init_config_gs_rings
;
847 bool init_config_has_vgt_flush
;
848 struct si_pm4_state
*vgt_shader_config
[4];
851 struct si_shader_ctx_state ps_shader
;
852 struct si_shader_ctx_state gs_shader
;
853 struct si_shader_ctx_state vs_shader
;
854 struct si_shader_ctx_state tcs_shader
;
855 struct si_shader_ctx_state tes_shader
;
856 struct si_cs_shader_state cs_shader_state
;
858 /* shader information */
859 struct si_vertex_elements
*vertex_elements
;
860 unsigned sprite_coord_enable
;
861 unsigned cs_max_waves_per_sh
;
863 bool do_update_shaders
;
865 /* vertex buffer descriptors */
866 uint32_t *vb_descriptors_gpu_list
;
867 struct r600_resource
*vb_descriptors_buffer
;
868 unsigned vb_descriptors_offset
;
870 /* shader descriptors */
871 struct si_descriptors descriptors
[SI_NUM_DESCS
];
872 unsigned descriptors_dirty
;
873 unsigned shader_pointers_dirty
;
874 unsigned shader_needs_decompress_mask
;
875 struct si_buffer_resources rw_buffers
;
876 struct si_buffer_resources const_and_shader_buffers
[SI_NUM_SHADERS
];
877 struct si_samplers samplers
[SI_NUM_SHADERS
];
878 struct si_images images
[SI_NUM_SHADERS
];
880 /* other shader resources */
881 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on CIK */
882 struct pipe_resource
*esgs_ring
;
883 struct pipe_resource
*gsvs_ring
;
884 struct pipe_resource
*tess_rings
;
885 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
886 struct r600_resource
*border_color_buffer
;
887 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
888 unsigned border_color_count
;
889 unsigned num_vs_blit_sgprs
;
890 uint32_t vs_blit_sh_data
[SI_VS_BLIT_SGPRS_POS_TEXCOORD
];
891 uint32_t cs_user_data
[4];
893 /* Vertex and index buffers. */
894 bool vertex_buffers_dirty
;
895 bool vertex_buffer_pointer_dirty
;
896 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
898 /* MSAA config state. */
900 bool ps_uses_fbfetch
;
901 bool smoothing_enabled
;
903 /* DB render state. */
904 unsigned ps_db_shader_control
;
905 unsigned dbcb_copy_sample
;
906 bool dbcb_depth_copy_enabled
:1;
907 bool dbcb_stencil_copy_enabled
:1;
908 bool db_flush_depth_inplace
:1;
909 bool db_flush_stencil_inplace
:1;
910 bool db_depth_clear
:1;
911 bool db_depth_disable_expclear
:1;
912 bool db_stencil_clear
:1;
913 bool db_stencil_disable_expclear
:1;
914 bool occlusion_queries_disabled
:1;
915 bool generate_mipmap_for_depth
:1;
917 /* Emitted draw state. */
918 bool gs_tri_strip_adj_fix
:1;
921 int last_base_vertex
;
922 int last_start_instance
;
924 int last_sh_base_reg
;
925 int last_primitive_restart_en
;
926 int last_restart_index
;
928 int last_multi_vgt_param
;
930 unsigned last_sc_line_stipple
;
931 unsigned current_vs_state
;
932 unsigned last_vs_state
;
933 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
936 struct r600_resource
*scratch_buffer
;
937 unsigned scratch_waves
;
938 unsigned spi_tmpring_size
;
940 struct r600_resource
*compute_scratch_buffer
;
942 /* Emitted derived tessellation state. */
943 /* Local shader (VS), or HS if LS-HS are merged. */
944 struct si_shader
*last_ls
;
945 struct si_shader_selector
*last_tcs
;
946 int last_num_tcs_input_cp
;
947 int last_tes_sh_base
;
948 bool last_tess_uses_primid
;
949 unsigned last_num_patches
;
950 int last_ls_hs_config
;
954 struct si_saved_cs
*current_saved_cs
;
955 uint64_t dmesg_timestamp
;
956 unsigned apitrace_call_number
;
959 bool need_check_render_feedback
;
960 bool decompression_enabled
;
962 bool vs_writes_viewport_index
;
963 bool vs_disables_clipping_viewport
;
965 /* Precomputed IA_MULTI_VGT_PARAM */
966 union si_vgt_param_key ia_multi_vgt_param_key
;
967 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
969 /* Bindless descriptors. */
970 struct si_descriptors bindless_descriptors
;
971 struct util_idalloc bindless_used_slots
;
972 unsigned num_bindless_descriptors
;
973 bool bindless_descriptors_dirty
;
974 bool graphics_bindless_pointer_dirty
;
975 bool compute_bindless_pointer_dirty
;
977 /* Allocated bindless handles */
978 struct hash_table
*tex_handles
;
979 struct hash_table
*img_handles
;
981 /* Resident bindless handles */
982 struct util_dynarray resident_tex_handles
;
983 struct util_dynarray resident_img_handles
;
985 /* Resident bindless handles which need decompression */
986 struct util_dynarray resident_tex_needs_color_decompress
;
987 struct util_dynarray resident_img_needs_color_decompress
;
988 struct util_dynarray resident_tex_needs_depth_decompress
;
991 bool uses_bindless_samplers
;
992 bool uses_bindless_images
;
994 /* MSAA sample locations.
995 * The first index is the sample index.
996 * The second index is the coordinate: X, Y. */
1004 struct pipe_resource
*sample_pos_buffer
;
1007 unsigned num_draw_calls
;
1008 unsigned num_decompress_calls
;
1009 unsigned num_mrt_draw_calls
;
1010 unsigned num_prim_restart_calls
;
1011 unsigned num_spill_draw_calls
;
1012 unsigned num_compute_calls
;
1013 unsigned num_spill_compute_calls
;
1014 unsigned num_dma_calls
;
1015 unsigned num_cp_dma_calls
;
1016 unsigned num_vs_flushes
;
1017 unsigned num_ps_flushes
;
1018 unsigned num_cs_flushes
;
1019 unsigned num_cb_cache_flushes
;
1020 unsigned num_db_cache_flushes
;
1021 unsigned num_L2_invalidates
;
1022 unsigned num_L2_writebacks
;
1023 unsigned num_resident_handles
;
1024 uint64_t num_alloc_tex_transfer_bytes
;
1025 unsigned last_tex_ps_draw_ratio
; /* for query */
1026 unsigned context_roll_counter
;
1029 /* Maintain the list of active queries for pausing between IBs. */
1030 int num_occlusion_queries
;
1031 int num_perfect_occlusion_queries
;
1032 struct list_head active_queries
;
1033 unsigned num_cs_dw_queries_suspend
;
1035 /* Render condition. */
1036 struct pipe_query
*render_cond
;
1037 unsigned render_cond_mode
;
1038 bool render_cond_invert
;
1039 bool render_cond_force_off
; /* for u_blitter */
1041 /* Statistics gathering for the DCC enablement heuristic. It can't be
1042 * in si_texture because si_texture can be shared by multiple
1043 * contexts. This is for back buffers only. We shouldn't get too many
1046 * X11 DRI3 rotates among a finite set of back buffers. They should
1047 * all fit in this array. If they don't, separate DCC might never be
1048 * enabled by DCC stat gathering.
1051 struct si_texture
*tex
;
1052 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1053 struct pipe_query
*ps_stats
[3];
1054 /* If all slots are used and another slot is needed,
1055 * the least recently used slot is evicted based on this. */
1056 int64_t last_use_timestamp
;
1060 /* Copy one resource to another using async DMA. */
1061 void (*dma_copy
)(struct pipe_context
*ctx
,
1062 struct pipe_resource
*dst
,
1064 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
1065 struct pipe_resource
*src
,
1067 const struct pipe_box
*src_box
);
1069 struct si_tracked_regs tracked_regs
;
1073 void cik_init_sdma_functions(struct si_context
*sctx
);
1076 enum si_blitter_op
/* bitmask */
1078 SI_SAVE_TEXTURES
= 1,
1079 SI_SAVE_FRAMEBUFFER
= 2,
1080 SI_SAVE_FRAGMENT_STATE
= 4,
1081 SI_DISABLE_RENDER_COND
= 8,
1084 void si_blitter_begin(struct si_context
*sctx
, enum si_blitter_op op
);
1085 void si_blitter_end(struct si_context
*sctx
);
1086 void si_init_blit_functions(struct si_context
*sctx
);
1087 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
);
1088 void si_resource_copy_region(struct pipe_context
*ctx
,
1089 struct pipe_resource
*dst
,
1091 unsigned dstx
, unsigned dsty
, unsigned dstz
,
1092 struct pipe_resource
*src
,
1094 const struct pipe_box
*src_box
);
1095 void si_decompress_dcc(struct si_context
*sctx
, struct si_texture
*tex
);
1096 void si_blit_decompress_depth(struct pipe_context
*ctx
,
1097 struct si_texture
*texture
,
1098 struct si_texture
*staging
,
1099 unsigned first_level
, unsigned last_level
,
1100 unsigned first_layer
, unsigned last_layer
,
1101 unsigned first_sample
, unsigned last_sample
);
1104 bool si_rings_is_buffer_referenced(struct si_context
*sctx
,
1105 struct pb_buffer
*buf
,
1106 enum radeon_bo_usage usage
);
1107 void *si_buffer_map_sync_with_rings(struct si_context
*sctx
,
1108 struct r600_resource
*resource
,
1110 void si_init_resource_fields(struct si_screen
*sscreen
,
1111 struct r600_resource
*res
,
1112 uint64_t size
, unsigned alignment
);
1113 bool si_alloc_resource(struct si_screen
*sscreen
,
1114 struct r600_resource
*res
);
1115 struct pipe_resource
*pipe_aligned_buffer_create(struct pipe_screen
*screen
,
1116 unsigned flags
, unsigned usage
,
1117 unsigned size
, unsigned alignment
);
1118 struct r600_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
,
1119 unsigned flags
, unsigned usage
,
1120 unsigned size
, unsigned alignment
);
1121 void si_replace_buffer_storage(struct pipe_context
*ctx
,
1122 struct pipe_resource
*dst
,
1123 struct pipe_resource
*src
);
1124 void si_init_screen_buffer_functions(struct si_screen
*sscreen
);
1125 void si_init_buffer_functions(struct si_context
*sctx
);
1128 enum pipe_format
si_simplify_cb_format(enum pipe_format format
);
1129 bool vi_alpha_is_on_msb(enum pipe_format format
);
1130 void vi_dcc_clear_level(struct si_context
*sctx
,
1131 struct si_texture
*tex
,
1132 unsigned level
, unsigned clear_value
);
1133 void si_init_clear_functions(struct si_context
*sctx
);
1135 /* si_compute_blit.c */
1136 unsigned si_get_flush_flags(struct si_context
*sctx
, enum si_coherency coher
,
1137 enum si_cache_policy cache_policy
);
1138 void si_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1139 uint64_t offset
, uint64_t size
, uint32_t *clear_value
,
1140 uint32_t clear_value_size
, enum si_coherency coher
);
1141 void si_copy_buffer(struct si_context
*sctx
,
1142 struct pipe_resource
*dst
, struct pipe_resource
*src
,
1143 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
);
1144 void si_init_compute_blit_functions(struct si_context
*sctx
);
1147 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1148 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1149 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1150 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1151 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1152 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1153 SI_CPDMA_SKIP_SYNC_AFTER | \
1154 SI_CPDMA_SKIP_SYNC_BEFORE | \
1155 SI_CPDMA_SKIP_GFX_SYNC | \
1156 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1158 void si_cp_dma_wait_for_idle(struct si_context
*sctx
);
1159 void si_cp_dma_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1160 uint64_t offset
, uint64_t size
, unsigned value
,
1161 enum si_coherency coher
,
1162 enum si_cache_policy cache_policy
);
1163 void si_cp_dma_copy_buffer(struct si_context
*sctx
,
1164 struct pipe_resource
*dst
, struct pipe_resource
*src
,
1165 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
1166 unsigned user_flags
, enum si_coherency coher
,
1167 enum si_cache_policy cache_policy
);
1168 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
1169 uint64_t offset
, unsigned size
);
1170 void cik_emit_prefetch_L2(struct si_context
*sctx
, bool vertex_stage_only
);
1171 void si_test_gds(struct si_context
*sctx
);
1174 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_cmdbuf
*cs
,
1175 struct radeon_saved_cs
*saved
, bool get_buffer_list
);
1176 void si_clear_saved_cs(struct radeon_saved_cs
*saved
);
1177 void si_destroy_saved_cs(struct si_saved_cs
*scs
);
1178 void si_auto_log_cs(void *data
, struct u_log_context
*log
);
1179 void si_log_hw_flush(struct si_context
*sctx
);
1180 void si_log_draw_state(struct si_context
*sctx
, struct u_log_context
*log
);
1181 void si_log_compute_state(struct si_context
*sctx
, struct u_log_context
*log
);
1182 void si_init_debug_functions(struct si_context
*sctx
);
1183 void si_check_vm_faults(struct si_context
*sctx
,
1184 struct radeon_saved_cs
*saved
, enum ring_type ring
);
1185 bool si_replace_shader(unsigned num
, struct ac_shader_binary
*binary
);
1188 void si_init_dma_functions(struct si_context
*sctx
);
1191 void si_dma_emit_timestamp(struct si_context
*sctx
, struct r600_resource
*dst
,
1193 void si_sdma_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1194 uint64_t offset
, uint64_t size
, unsigned clear_value
);
1195 void si_need_dma_space(struct si_context
*ctx
, unsigned num_dw
,
1196 struct r600_resource
*dst
, struct r600_resource
*src
);
1197 void si_flush_dma_cs(struct si_context
*ctx
, unsigned flags
,
1198 struct pipe_fence_handle
**fence
);
1199 void si_screen_clear_buffer(struct si_screen
*sscreen
, struct pipe_resource
*dst
,
1200 uint64_t offset
, uint64_t size
, unsigned value
);
1203 void si_cp_release_mem(struct si_context
*ctx
,
1204 unsigned event
, unsigned event_flags
,
1205 unsigned dst_sel
, unsigned int_sel
, unsigned data_sel
,
1206 struct r600_resource
*buf
, uint64_t va
,
1207 uint32_t new_fence
, unsigned query_type
);
1208 unsigned si_cp_write_fence_dwords(struct si_screen
*screen
);
1209 void si_cp_wait_mem(struct si_context
*ctx
,
1210 uint64_t va
, uint32_t ref
, uint32_t mask
, unsigned flags
);
1211 void si_init_fence_functions(struct si_context
*ctx
);
1212 void si_init_screen_fence_functions(struct si_screen
*screen
);
1213 struct pipe_fence_handle
*si_create_fence(struct pipe_context
*ctx
,
1214 struct tc_unflushed_batch_token
*tc_token
);
1217 void si_init_screen_get_functions(struct si_screen
*sscreen
);
1220 void si_flush_gfx_cs(struct si_context
*ctx
, unsigned flags
,
1221 struct pipe_fence_handle
**fence
);
1222 void si_begin_new_gfx_cs(struct si_context
*ctx
);
1223 void si_need_gfx_cs_space(struct si_context
*ctx
);
1225 /* r600_gpu_load.c */
1226 void si_gpu_load_kill_thread(struct si_screen
*sscreen
);
1227 uint64_t si_begin_counter(struct si_screen
*sscreen
, unsigned type
);
1228 unsigned si_end_counter(struct si_screen
*sscreen
, unsigned type
,
1232 void si_init_compute_functions(struct si_context
*sctx
);
1234 /* r600_perfcounters.c */
1235 void si_perfcounters_destroy(struct si_screen
*sscreen
);
1237 /* si_perfcounters.c */
1238 void si_init_perfcounters(struct si_screen
*screen
);
1241 bool si_check_device_reset(struct si_context
*sctx
);
1244 void si_init_screen_query_functions(struct si_screen
*sscreen
);
1245 void si_init_query_functions(struct si_context
*sctx
);
1246 void si_suspend_queries(struct si_context
*sctx
);
1247 void si_resume_queries(struct si_context
*sctx
);
1249 /* si_shaderlib_tgsi.c */
1250 void *si_get_blitter_vs(struct si_context
*sctx
, enum blitter_attrib_type type
,
1251 unsigned num_layers
);
1252 void *si_create_fixed_func_tcs(struct si_context
*sctx
);
1253 void *si_create_dma_compute_shader(struct pipe_context
*ctx
,
1254 unsigned num_dwords_per_thread
,
1255 bool dst_stream_cache_policy
, bool is_copy
);
1256 void *si_create_query_result_cs(struct si_context
*sctx
);
1259 void si_test_dma(struct si_screen
*sscreen
);
1261 /* si_test_clearbuffer.c */
1262 void si_test_dma_perf(struct si_screen
*sscreen
);
1265 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
1266 const struct pipe_video_codec
*templ
);
1268 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
1269 const struct pipe_video_buffer
*tmpl
);
1272 void si_update_vs_viewport_state(struct si_context
*ctx
);
1273 void si_init_viewport_functions(struct si_context
*ctx
);
1276 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
1277 struct si_texture
*dst
,
1278 unsigned dst_level
, unsigned dstx
,
1279 unsigned dsty
, unsigned dstz
,
1280 struct si_texture
*src
,
1282 const struct pipe_box
*src_box
);
1283 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
1284 struct si_texture
*tex
);
1285 void si_texture_discard_cmask(struct si_screen
*sscreen
,
1286 struct si_texture
*tex
);
1287 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1288 struct pipe_resource
*texture
,
1289 struct si_texture
**staging
);
1290 void si_print_texture_info(struct si_screen
*sscreen
,
1291 struct si_texture
*tex
, struct u_log_context
*log
);
1292 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1293 const struct pipe_resource
*templ
);
1294 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1295 enum pipe_format format2
);
1296 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1298 enum pipe_format view_format
);
1299 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
1300 struct pipe_resource
*tex
,
1302 enum pipe_format view_format
);
1303 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1304 struct pipe_resource
*texture
,
1305 const struct pipe_surface
*templ
,
1306 unsigned width0
, unsigned height0
,
1307 unsigned width
, unsigned height
);
1308 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
1309 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
1310 struct si_texture
*tex
);
1311 void vi_separate_dcc_start_query(struct si_context
*sctx
,
1312 struct si_texture
*tex
);
1313 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
1314 struct si_texture
*tex
);
1315 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
1316 struct si_texture
*tex
);
1317 bool si_texture_disable_dcc(struct si_context
*sctx
,
1318 struct si_texture
*tex
);
1319 void si_init_screen_texture_functions(struct si_screen
*sscreen
);
1320 void si_init_context_texture_functions(struct si_context
*sctx
);
1327 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
1329 return (struct r600_resource
*)r
;
1333 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
1335 pipe_resource_reference((struct pipe_resource
**)ptr
,
1336 (struct pipe_resource
*)res
);
1340 si_texture_reference(struct si_texture
**ptr
, struct si_texture
*res
)
1342 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->buffer
.b
.b
);
1346 vi_dcc_enabled(struct si_texture
*tex
, unsigned level
)
1348 return tex
->dcc_offset
&& level
< tex
->surface
.num_dcc_levels
;
1351 static inline unsigned
1352 si_tile_mode_index(struct si_texture
*tex
, unsigned level
, bool stencil
)
1355 return tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
1357 return tex
->surface
.u
.legacy
.tiling_index
[level
];
1361 si_context_add_resource_size(struct si_context
*sctx
, struct pipe_resource
*r
)
1364 /* Add memory usage for need_gfx_cs_space */
1365 sctx
->vram
+= r600_resource(r
)->vram_usage
;
1366 sctx
->gtt
+= r600_resource(r
)->gart_usage
;
1371 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
1373 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
1376 static inline unsigned
1377 si_get_atom_bit(struct si_context
*sctx
, struct si_atom
*atom
)
1379 return 1 << (atom
- sctx
->atoms
.array
);
1383 si_set_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
, bool dirty
)
1385 unsigned bit
= si_get_atom_bit(sctx
, atom
);
1388 sctx
->dirty_atoms
|= bit
;
1390 sctx
->dirty_atoms
&= ~bit
;
1394 si_is_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1396 return (sctx
->dirty_atoms
& si_get_atom_bit(sctx
, atom
)) != 0;
1400 si_mark_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1402 si_set_atom_dirty(sctx
, atom
, true);
1405 static inline struct si_shader_ctx_state
*si_get_vs(struct si_context
*sctx
)
1407 if (sctx
->gs_shader
.cso
)
1408 return &sctx
->gs_shader
;
1409 if (sctx
->tes_shader
.cso
)
1410 return &sctx
->tes_shader
;
1412 return &sctx
->vs_shader
;
1415 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
1417 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1419 return vs
->cso
? &vs
->cso
->info
: NULL
;
1422 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
1424 if (sctx
->gs_shader
.cso
)
1425 return sctx
->gs_shader
.cso
->gs_copy_shader
;
1427 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1428 return vs
->current
? vs
->current
: NULL
;
1431 static inline bool si_can_dump_shader(struct si_screen
*sscreen
,
1434 return sscreen
->debug_flags
& (1 << processor
);
1437 static inline bool si_get_strmout_en(struct si_context
*sctx
)
1439 return sctx
->streamout
.streamout_enabled
||
1440 sctx
->streamout
.prims_gen_query_enabled
;
1443 static inline unsigned
1444 si_optimal_tcc_alignment(struct si_context
*sctx
, unsigned upload_size
)
1446 unsigned alignment
, tcc_cache_line_size
;
1448 /* If the upload size is less than the cache line size (e.g. 16, 32),
1449 * the whole thing will fit into a cache line if we align it to its size.
1450 * The idea is that multiple small uploads can share a cache line.
1451 * If the upload size is greater, align it to the cache line size.
1453 alignment
= util_next_power_of_two(upload_size
);
1454 tcc_cache_line_size
= sctx
->screen
->info
.tcc_cache_line_size
;
1455 return MIN2(alignment
, tcc_cache_line_size
);
1459 si_saved_cs_reference(struct si_saved_cs
**dst
, struct si_saved_cs
*src
)
1461 if (pipe_reference(&(*dst
)->reference
, &src
->reference
))
1462 si_destroy_saved_cs(*dst
);
1468 si_make_CB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1469 bool shaders_read_metadata
)
1471 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
|
1472 SI_CONTEXT_INV_VMEM_L1
;
1474 if (sctx
->chip_class
>= GFX9
) {
1475 /* Single-sample color is coherent with shaders on GFX9, but
1476 * L2 metadata must be flushed if shaders read metadata.
1479 if (num_samples
>= 2)
1480 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1481 else if (shaders_read_metadata
)
1482 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1485 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1490 si_make_DB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1491 bool include_stencil
, bool shaders_read_metadata
)
1493 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB
|
1494 SI_CONTEXT_INV_VMEM_L1
;
1496 if (sctx
->chip_class
>= GFX9
) {
1497 /* Single-sample depth (not stencil) is coherent with shaders
1498 * on GFX9, but L2 metadata must be flushed if shaders read
1501 if (num_samples
>= 2 || include_stencil
)
1502 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1503 else if (shaders_read_metadata
)
1504 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1507 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1512 si_can_sample_zs(struct si_texture
*tex
, bool stencil_sampler
)
1514 return (stencil_sampler
&& tex
->can_sample_s
) ||
1515 (!stencil_sampler
&& tex
->can_sample_z
);
1519 si_htile_enabled(struct si_texture
*tex
, unsigned level
)
1521 return tex
->htile_offset
&& level
== 0;
1525 vi_tc_compat_htile_enabled(struct si_texture
*tex
, unsigned level
)
1527 assert(!tex
->tc_compatible_htile
|| tex
->htile_offset
);
1528 return tex
->tc_compatible_htile
&& level
== 0;
1531 static inline unsigned si_get_ps_iter_samples(struct si_context
*sctx
)
1533 if (sctx
->ps_uses_fbfetch
)
1534 return sctx
->framebuffer
.nr_color_samples
;
1536 return MIN2(sctx
->ps_iter_samples
, sctx
->framebuffer
.nr_color_samples
);
1539 static inline unsigned si_get_total_colormask(struct si_context
*sctx
)
1541 if (sctx
->queued
.named
.rasterizer
->rasterizer_discard
)
1544 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1548 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
1549 sctx
->queued
.named
.blend
->cb_target_mask
;
1551 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
1552 colormask
&= ps
->colors_written_4bit
;
1553 else if (!ps
->colors_written_4bit
)
1554 colormask
= 0; /* color0 writes all cbufs, but it's not written */
1559 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1560 (1 << PIPE_PRIM_LINE_LOOP) | \
1561 (1 << PIPE_PRIM_LINE_STRIP) | \
1562 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1563 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1565 static inline bool util_prim_is_lines(unsigned prim
)
1567 return ((1 << prim
) & UTIL_ALL_PRIM_LINE_MODES
) != 0;
1570 static inline bool util_prim_is_points_or_lines(unsigned prim
)
1572 return ((1 << prim
) & (UTIL_ALL_PRIM_LINE_MODES
|
1573 (1 << PIPE_PRIM_POINTS
))) != 0;
1577 * Return true if there is enough memory in VRAM and GTT for the buffers
1580 * \param vram VRAM memory size not added to the buffer list yet
1581 * \param gtt GTT memory size not added to the buffer list yet
1584 radeon_cs_memory_below_limit(struct si_screen
*screen
,
1585 struct radeon_cmdbuf
*cs
,
1586 uint64_t vram
, uint64_t gtt
)
1588 vram
+= cs
->used_vram
;
1589 gtt
+= cs
->used_gart
;
1591 /* Anything that goes above the VRAM size should go to GTT. */
1592 if (vram
> screen
->info
.vram_size
)
1593 gtt
+= vram
- screen
->info
.vram_size
;
1595 /* Now we just need to check if we have enough GTT. */
1596 return gtt
< screen
->info
.gart_size
* 0.7;
1600 * Add a buffer to the buffer list for the given command stream (CS).
1602 * All buffers used by a CS must be added to the list. This tells the kernel
1603 * driver which buffers are used by GPU commands. Other buffers can
1604 * be swapped out (not accessible) during execution.
1606 * The buffer list becomes empty after every context flush and must be
1609 static inline void radeon_add_to_buffer_list(struct si_context
*sctx
,
1610 struct radeon_cmdbuf
*cs
,
1611 struct r600_resource
*rbo
,
1612 enum radeon_bo_usage usage
,
1613 enum radeon_bo_priority priority
)
1616 sctx
->ws
->cs_add_buffer(
1618 (enum radeon_bo_usage
)(usage
| RADEON_USAGE_SYNCHRONIZED
),
1619 rbo
->domains
, priority
);
1623 * Same as above, but also checks memory usage and flushes the context
1626 * When this SHOULD NOT be used:
1628 * - if si_context_add_resource_size has been called for the buffer
1629 * followed by *_need_cs_space for checking the memory usage
1631 * - if si_need_dma_space has been called for the buffer
1633 * - when emitting state packets and draw packets (because preceding packets
1634 * can't be re-emitted at that point)
1636 * - if shader resource "enabled_mask" is not up-to-date or there is
1637 * a different constraint disallowing a context flush
1640 radeon_add_to_gfx_buffer_list_check_mem(struct si_context
*sctx
,
1641 struct r600_resource
*rbo
,
1642 enum radeon_bo_usage usage
,
1643 enum radeon_bo_priority priority
,
1647 !radeon_cs_memory_below_limit(sctx
->screen
, sctx
->gfx_cs
,
1648 sctx
->vram
+ rbo
->vram_usage
,
1649 sctx
->gtt
+ rbo
->gart_usage
))
1650 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1652 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, rbo
, usage
, priority
);
1655 #define PRINT_ERR(fmt, args...) \
1656 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)