src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef SI_PIPE_H
  24 #define SI_PIPE_H
  25
  26 #include "si_shader.h"
  27
  28 #include "util/u_dynarray.h"
  29 #include "util/u_idalloc.h"
  30
  31 #ifdef PIPE_ARCH_BIG_ENDIAN
  32 #define SI_BIG_ENDIAN 1
  33 #else
  34 #define SI_BIG_ENDIAN 0
  35 #endif
  36
  37 /* The base vertex and primitive restart can be any number, but we must pick
  38  * one which will mean "unknown" for the purpose of state tracking and
  39  * the number shouldn't be a commonly-used one. */
  40 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  41 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  42 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  43 #define SI_GS_PER_ES 128
  44 /* Alignment for optimal CP DMA performance. */
  45 #define SI_CPDMA_ALIGNMENT      32
  46
  47 /* Instruction cache. */
  48 #define SI_CONTEXT_INV_ICACHE           (R600_CONTEXT_PRIVATE_FLAG << 0)
  49 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  50 #define SI_CONTEXT_INV_SMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 1)
  51 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  52 #define SI_CONTEXT_INV_VMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 2)
  53 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  54 #define SI_CONTEXT_INV_GLOBAL_L2        (R600_CONTEXT_PRIVATE_FLAG << 3)
  55 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  56  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
  57 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2  (R600_CONTEXT_PRIVATE_FLAG << 4)
  58 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
  59  * a CB or DB flush. */
  60 #define SI_CONTEXT_INV_L2_METADATA      (R600_CONTEXT_PRIVATE_FLAG << 5)
  61 /* Framebuffer caches. */
  62 #define SI_CONTEXT_FLUSH_AND_INV_DB     (R600_CONTEXT_PRIVATE_FLAG << 6)
  63 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 7)
  64 #define SI_CONTEXT_FLUSH_AND_INV_CB     (R600_CONTEXT_PRIVATE_FLAG << 8)
  65 /* Engine synchronization. */
  66 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 9)
  67 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 10)
  68 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 11)
  69 #define SI_CONTEXT_VGT_FLUSH            (R600_CONTEXT_PRIVATE_FLAG << 12)
  70 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (R600_CONTEXT_PRIVATE_FLAG << 13)
  71
  72 #define SI_PREFETCH_VBO_DESCRIPTORS     (1 << 0)
  73 #define SI_PREFETCH_LS                  (1 << 1)
  74 #define SI_PREFETCH_HS                  (1 << 2)
  75 #define SI_PREFETCH_ES                  (1 << 3)
  76 #define SI_PREFETCH_GS                  (1 << 4)
  77 #define SI_PREFETCH_VS                  (1 << 5)
  78 #define SI_PREFETCH_PS                  (1 << 6)
  79
  80 #define SI_MAX_BORDER_COLORS    4096
  81 #define SI_MAX_VIEWPORTS        16
  82 #define SIX_BITS                0x3F
  83
  84 struct si_compute;
  85 struct hash_table;
  86 struct u_suballocator;
  87
  88 struct si_screen {
  89         struct r600_common_screen       b;
  90         unsigned                        gs_table_depth;
  91         unsigned                        tess_offchip_block_dw_size;
  92         bool                            has_clear_state;
  93         bool                            has_distributed_tess;
  94         bool                            has_draw_indirect_multi;
  95         bool                            has_out_of_order_rast;
  96         bool                            assume_no_z_fights;
  97         bool                            commutative_blend_add;
  98         bool                            clear_db_cache_before_clear;
  99         bool                            has_msaa_sample_loc_bug;
 100         bool                            has_ls_vgpr_init_bug;
 101         bool                            dpbb_allowed;
 102         bool                            dfsm_allowed;
 103         bool                            llvm_has_working_vgpr_indexing;
 104
 105         /* Whether shaders are monolithic (1-part) or separate (3-part). */
 106         bool                            use_monolithic_shaders;
 107         bool                            record_llvm_ir;
 108
 109         mtx_t                   shader_parts_mutex;
 110         struct si_shader_part           *vs_prologs;
 111         struct si_shader_part           *tcs_epilogs;
 112         struct si_shader_part           *gs_prologs;
 113         struct si_shader_part           *ps_prologs;
 114         struct si_shader_part           *ps_epilogs;
 115
 116         /* Shader cache in memory.
 117          *
 118          * Design & limitations:
 119          * - The shader cache is per screen (= per process), never saved to
 120          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 121          * - It can only be used with one-variant-per-shader support, in which
 122          *   case only the main (typically middle) part of shaders is cached.
 123          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 124          *   variants of VS and TES are cached, so LS and ES aren't.
 125          * - GS and CS aren't cached, but it's certainly possible to cache
 126          *   those as well.
 127          */
 128         mtx_t                   shader_cache_mutex;
 129         struct hash_table               *shader_cache;
 130
 131         /* Shader compiler queue for multithreaded compilation. */
 132         struct util_queue               shader_compiler_queue;
 133         /* Use at most 3 normal compiler threads on quadcore and better.
 134          * Hyperthreaded CPUs report the number of threads, but we want
 135          * the number of cores. */
 136         LLVMTargetMachineRef            tm[3]; /* used by the queue only */
 137
 138         struct util_queue               shader_compiler_queue_low_priority;
 139         /* Use at most 2 low priority threads on quadcore and better.
 140          * We want to minimize the impact on multithreaded Mesa. */
 141         LLVMTargetMachineRef            tm_low_priority[2]; /* at most 2 threads */
 142 };
 143
 144 struct si_blend_color {
 145         struct r600_atom                atom;
 146         struct pipe_blend_color         state;
 147         bool                            any_nonzeros;
 148 };
 149
 150 struct si_sampler_view {
 151         struct pipe_sampler_view        base;
 152         /* [0..7] = image descriptor
 153          * [4..7] = buffer descriptor */
 154         uint32_t                        state[8];
 155         uint32_t                        fmask_state[8];
 156         const struct legacy_surf_level  *base_level_info;
 157         ubyte                           base_level;
 158         ubyte                           block_width;
 159         bool is_stencil_sampler;
 160         bool is_integer;
 161         bool dcc_incompatible;
 162 };
 163
 164 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
 165
 166 struct si_sampler_state {
 167 #ifdef DEBUG
 168         unsigned                        magic;
 169 #endif
 170         uint32_t                        val[4];
 171         uint32_t                        integer_val[4];
 172         uint32_t                        upgraded_depth_val[4];
 173 };
 174
 175 struct si_cs_shader_state {
 176         struct si_compute               *program;
 177         struct si_compute               *emitted_program;
 178         unsigned                        offset;
 179         bool                            initialized;
 180         bool                            uses_scratch;
 181 };
 182
 183 struct si_samplers {
 184         struct pipe_sampler_view        *views[SI_NUM_SAMPLERS];
 185         struct si_sampler_state         *sampler_states[SI_NUM_SAMPLERS];
 186
 187         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 188         unsigned                        enabled_mask;
 189         uint32_t                        needs_depth_decompress_mask;
 190         uint32_t                        needs_color_decompress_mask;
 191 };
 192
 193 struct si_images {
 194         struct pipe_image_view          views[SI_NUM_IMAGES];
 195         uint32_t                        needs_color_decompress_mask;
 196         unsigned                        enabled_mask;
 197 };
 198
 199 struct si_framebuffer {
 200         struct r600_atom                atom;
 201         struct pipe_framebuffer_state   state;
 202         unsigned                        colorbuf_enabled_4bit;
 203         unsigned                        spi_shader_col_format;
 204         unsigned                        spi_shader_col_format_alpha;
 205         unsigned                        spi_shader_col_format_blend;
 206         unsigned                        spi_shader_col_format_blend_alpha;
 207         ubyte                           nr_samples:5; /* at most 16xAA */
 208         ubyte                           log_samples:3; /* at most 4 = 16xAA */
 209         ubyte                           compressed_cb_mask;
 210         ubyte                           color_is_int8;
 211         ubyte                           color_is_int10;
 212         ubyte                           dirty_cbufs;
 213         bool                            dirty_zsbuf;
 214         bool                            any_dst_linear;
 215         bool                            CB_has_shader_readable_metadata;
 216         bool                            DB_has_shader_readable_metadata;
 217 };
 218
 219 struct si_signed_scissor {
 220         int minx;
 221         int miny;
 222         int maxx;
 223         int maxy;
 224 };
 225
 226 struct si_scissors {
 227         struct r600_atom                atom;
 228         unsigned                        dirty_mask;
 229         struct pipe_scissor_state       states[SI_MAX_VIEWPORTS];
 230 };
 231
 232 struct si_viewports {
 233         struct r600_atom                atom;
 234         unsigned                        dirty_mask;
 235         unsigned                        depth_range_dirty_mask;
 236         struct pipe_viewport_state      states[SI_MAX_VIEWPORTS];
 237         struct si_signed_scissor        as_scissor[SI_MAX_VIEWPORTS];
 238 };
 239
 240 struct si_clip_state {
 241         struct r600_atom                atom;
 242         struct pipe_clip_state          state;
 243         bool                            any_nonzeros;
 244 };
 245
 246 struct si_sample_locs {
 247         struct r600_atom        atom;
 248         unsigned                nr_samples;
 249 };
 250
 251 struct si_sample_mask {
 252         struct r600_atom        atom;
 253         uint16_t                sample_mask;
 254 };
 255
 256 struct si_streamout_target {
 257         struct pipe_stream_output_target b;
 258
 259         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 260         struct r600_resource    *buf_filled_size;
 261         unsigned                buf_filled_size_offset;
 262         bool                    buf_filled_size_valid;
 263
 264         unsigned                stride_in_dw;
 265 };
 266
 267 struct si_streamout {
 268         struct r600_atom                begin_atom;
 269         bool                            begin_emitted;
 270
 271         unsigned                        enabled_mask;
 272         unsigned                        num_targets;
 273         struct si_streamout_target      *targets[PIPE_MAX_SO_BUFFERS];
 274
 275         unsigned                        append_bitmask;
 276         bool                            suspended;
 277
 278         /* External state which comes from the vertex shader,
 279          * it must be set explicitly when binding a shader. */
 280         uint16_t                        *stride_in_dw;
 281         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 282
 283         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 284         unsigned                        hw_enabled_mask;
 285
 286         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 287         struct r600_atom                enable_atom;
 288         bool                            streamout_enabled;
 289         bool                            prims_gen_query_enabled;
 290         int                             num_prims_gen_queries;
 291 };
 292
 293 /* A shader state consists of the shader selector, which is a constant state
 294  * object shared by multiple contexts and shouldn't be modified, and
 295  * the current shader variant selected for this context.
 296  */
 297 struct si_shader_ctx_state {
 298         struct si_shader_selector       *cso;
 299         struct si_shader                *current;
 300 };
 301
 302 #define SI_NUM_VGT_PARAM_KEY_BITS 12
 303 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
 304
 305 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
 306  * Some fields are set by state-change calls, most are set by draw_vbo.
 307  */
 308 union si_vgt_param_key {
 309         struct {
 310                 unsigned prim:4;
 311                 unsigned uses_instancing:1;
 312                 unsigned multi_instances_smaller_than_primgroup:1;
 313                 unsigned primitive_restart:1;
 314                 unsigned count_from_stream_output:1;
 315                 unsigned line_stipple_enabled:1;
 316                 unsigned uses_tess:1;
 317                 unsigned tess_uses_prim_id:1;
 318                 unsigned uses_gs:1;
 319                 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
 320         } u;
 321         uint32_t index;
 322 };
 323
 324 struct si_texture_handle
 325 {
 326         unsigned                        desc_slot;
 327         bool                            desc_dirty;
 328         struct pipe_sampler_view        *view;
 329         struct si_sampler_state         sstate;
 330 };
 331
 332 struct si_image_handle
 333 {
 334         unsigned                        desc_slot;
 335         bool                            desc_dirty;
 336         struct pipe_image_view          view;
 337 };
 338
 339 struct si_saved_cs {
 340         struct pipe_reference   reference;
 341         struct si_context       *ctx;
 342         struct radeon_saved_cs  gfx;
 343         struct r600_resource    *trace_buf;
 344         unsigned                trace_id;
 345
 346         unsigned                gfx_last_dw;
 347         bool                    flushed;
 348         int64_t                 time_flush;
 349 };
 350
 351 struct si_context {
 352         struct r600_common_context      b;
 353         struct blitter_context          *blitter;
 354         void                            *custom_dsa_flush;
 355         void                            *custom_blend_resolve;
 356         void                            *custom_blend_fmask_decompress;
 357         void                            *custom_blend_eliminate_fastclear;
 358         void                            *custom_blend_dcc_decompress;
 359         void                            *vs_blit_pos;
 360         void                            *vs_blit_pos_layered;
 361         void                            *vs_blit_color;
 362         void                            *vs_blit_color_layered;
 363         void                            *vs_blit_texcoord;
 364         struct si_screen                *screen;
 365         struct pipe_debug_callback      debug;
 366         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 367         struct si_shader_ctx_state      fixed_func_tcs_shader;
 368         struct r600_resource            *wait_mem_scratch;
 369         unsigned                        wait_mem_number;
 370         uint16_t                        prefetch_L2_mask;
 371
 372         bool                            gfx_flush_in_progress:1;
 373         bool                            compute_is_busy:1;
 374
 375         /* Atoms (direct states). */
 376         union si_state_atoms            atoms;
 377         unsigned                        dirty_atoms; /* mask */
 378         /* PM4 states (precomputed immutable states) */
 379         unsigned                        dirty_states;
 380         union si_state                  queued;
 381         union si_state                  emitted;
 382
 383         /* Atom declarations. */
 384         struct si_framebuffer           framebuffer;
 385         struct si_sample_locs           msaa_sample_locs;
 386         struct r600_atom                db_render_state;
 387         struct r600_atom                dpbb_state;
 388         struct r600_atom                msaa_config;
 389         struct si_sample_mask           sample_mask;
 390         struct r600_atom                cb_render_state;
 391         unsigned                        last_cb_target_mask;
 392         struct si_blend_color           blend_color;
 393         struct r600_atom                clip_regs;
 394         struct si_clip_state            clip_state;
 395         struct si_shader_data           shader_pointers;
 396         struct si_stencil_ref           stencil_ref;
 397         struct r600_atom                spi_map;
 398         struct si_scissors              scissors;
 399         struct si_streamout             streamout;
 400         struct si_viewports             viewports;
 401
 402         /* Precomputed states. */
 403         struct si_pm4_state             *init_config;
 404         struct si_pm4_state             *init_config_gs_rings;
 405         bool                            init_config_has_vgt_flush;
 406         struct si_pm4_state             *vgt_shader_config[4];
 407
 408         /* shaders */
 409         struct si_shader_ctx_state      ps_shader;
 410         struct si_shader_ctx_state      gs_shader;
 411         struct si_shader_ctx_state      vs_shader;
 412         struct si_shader_ctx_state      tcs_shader;
 413         struct si_shader_ctx_state      tes_shader;
 414         struct si_cs_shader_state       cs_shader_state;
 415
 416         /* shader information */
 417         struct si_vertex_elements       *vertex_elements;
 418         unsigned                        sprite_coord_enable;
 419         bool                            flatshade;
 420         bool                            do_update_shaders;
 421
 422         /* shader descriptors */
 423         struct si_descriptors           vertex_buffers;
 424         struct si_descriptors           descriptors[SI_NUM_DESCS];
 425         unsigned                        descriptors_dirty;
 426         unsigned                        shader_pointers_dirty;
 427         unsigned                        shader_needs_decompress_mask;
 428         struct si_buffer_resources      rw_buffers;
 429         struct si_buffer_resources      const_and_shader_buffers[SI_NUM_SHADERS];
 430         struct si_samplers              samplers[SI_NUM_SHADERS];
 431         struct si_images                images[SI_NUM_SHADERS];
 432
 433         /* other shader resources */
 434         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 435         struct pipe_resource            *esgs_ring;
 436         struct pipe_resource            *gsvs_ring;
 437         struct pipe_resource            *tf_ring;
 438         struct pipe_resource            *tess_offchip_ring;
 439         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 440         struct r600_resource            *border_color_buffer;
 441         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 442         unsigned                        border_color_count;
 443         unsigned                        num_vs_blit_sgprs;
 444         uint32_t                        vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
 445
 446         /* Vertex and index buffers. */
 447         bool                            vertex_buffers_dirty;
 448         bool                            vertex_buffer_pointer_dirty;
 449         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 450
 451         /* MSAA config state. */
 452         int                             ps_iter_samples;
 453         bool                            smoothing_enabled;
 454
 455         /* DB render state. */
 456         unsigned                ps_db_shader_control;
 457         unsigned                dbcb_copy_sample;
 458         bool                    dbcb_depth_copy_enabled:1;
 459         bool                    dbcb_stencil_copy_enabled:1;
 460         bool                    db_flush_depth_inplace:1;
 461         bool                    db_flush_stencil_inplace:1;
 462         bool                    db_depth_clear:1;
 463         bool                    db_depth_disable_expclear:1;
 464         bool                    db_stencil_clear:1;
 465         bool                    db_stencil_disable_expclear:1;
 466         bool                    occlusion_queries_disabled:1;
 467         bool                    generate_mipmap_for_depth:1;
 468
 469         /* Emitted draw state. */
 470         bool                    gs_tri_strip_adj_fix:1;
 471         bool                    ls_vgpr_fix:1;
 472         int                     last_index_size;
 473         int                     last_base_vertex;
 474         int                     last_start_instance;
 475         int                     last_drawid;
 476         int                     last_sh_base_reg;
 477         int                     last_primitive_restart_en;
 478         int                     last_restart_index;
 479         int                     last_gs_out_prim;
 480         int                     last_prim;
 481         int                     last_multi_vgt_param;
 482         int                     last_rast_prim;
 483         unsigned                last_sc_line_stipple;
 484         unsigned                current_vs_state;
 485         unsigned                last_vs_state;
 486         enum pipe_prim_type     current_rast_prim; /* primitive type after TES, GS */
 487
 488         /* Scratch buffer */
 489         struct r600_atom        scratch_state;
 490         struct r600_resource    *scratch_buffer;
 491         unsigned                scratch_waves;
 492         unsigned                spi_tmpring_size;
 493
 494         struct r600_resource    *compute_scratch_buffer;
 495
 496         /* Emitted derived tessellation state. */
 497         /* Local shader (VS), or HS if LS-HS are merged. */
 498         struct si_shader        *last_ls;
 499         struct si_shader_selector *last_tcs;
 500         int                     last_num_tcs_input_cp;
 501         int                     last_tes_sh_base;
 502         bool                    last_tess_uses_primid;
 503         unsigned                last_num_patches;
 504
 505         /* Debug state. */
 506         bool                    is_debug;
 507         struct si_saved_cs      *current_saved_cs;
 508         uint64_t                dmesg_timestamp;
 509         unsigned                apitrace_call_number;
 510
 511         /* Other state */
 512         bool need_check_render_feedback;
 513         bool                    decompression_enabled;
 514
 515         bool                    vs_writes_viewport_index;
 516         bool                    vs_disables_clipping_viewport;
 517
 518         /* Precomputed IA_MULTI_VGT_PARAM */
 519         union si_vgt_param_key  ia_multi_vgt_param_key;
 520         unsigned                ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
 521
 522         /* Bindless descriptors. */
 523         struct si_descriptors   bindless_descriptors;
 524         struct util_idalloc     bindless_used_slots;
 525         unsigned                num_bindless_descriptors;
 526         bool                    bindless_descriptors_dirty;
 527         bool                    graphics_bindless_pointer_dirty;
 528         bool                    compute_bindless_pointer_dirty;
 529
 530         /* Allocated bindless handles */
 531         struct hash_table       *tex_handles;
 532         struct hash_table       *img_handles;
 533
 534         /* Resident bindless handles */
 535         struct util_dynarray    resident_tex_handles;
 536         struct util_dynarray    resident_img_handles;
 537
 538         /* Resident bindless handles which need decompression */
 539         struct util_dynarray    resident_tex_needs_color_decompress;
 540         struct util_dynarray    resident_img_needs_color_decompress;
 541         struct util_dynarray    resident_tex_needs_depth_decompress;
 542
 543         /* Bindless state */
 544         bool                    uses_bindless_samplers;
 545         bool                    uses_bindless_images;
 546
 547         /* MSAA sample locations.
 548          * The first index is the sample index.
 549          * The second index is the coordinate: X, Y. */
 550         float                   sample_locations_1x[1][2];
 551         float                   sample_locations_2x[2][2];
 552         float                   sample_locations_4x[4][2];
 553         float                   sample_locations_8x[8][2];
 554         float                   sample_locations_16x[16][2];
 555 };
 556
 557 /* cik_sdma.c */
 558 void cik_init_sdma_functions(struct si_context *sctx);
 559
 560 /* si_blit.c */
 561 void si_init_blit_functions(struct si_context *sctx);
 562 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
 563 void si_resource_copy_region(struct pipe_context *ctx,
 564                              struct pipe_resource *dst,
 565                              unsigned dst_level,
 566                              unsigned dstx, unsigned dsty, unsigned dstz,
 567                              struct pipe_resource *src,
 568                              unsigned src_level,
 569                              const struct pipe_box *src_box);
 570
 571 /* si_cp_dma.c */
 572 #define SI_CPDMA_SKIP_CHECK_CS_SPACE    (1 << 0) /* don't call need_cs_space */
 573 #define SI_CPDMA_SKIP_SYNC_AFTER        (1 << 1) /* don't wait for DMA after the copy */
 574 #define SI_CPDMA_SKIP_SYNC_BEFORE       (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
 575 #define SI_CPDMA_SKIP_GFX_SYNC          (1 << 3) /* don't flush caches and don't wait for PS/CS */
 576 #define SI_CPDMA_SKIP_BO_LIST_UPDATE    (1 << 4) /* don't update the BO list */
 577 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
 578                            SI_CPDMA_SKIP_SYNC_AFTER | \
 579                            SI_CPDMA_SKIP_SYNC_BEFORE | \
 580                            SI_CPDMA_SKIP_GFX_SYNC | \
 581                            SI_CPDMA_SKIP_BO_LIST_UPDATE)
 582
 583 void si_copy_buffer(struct si_context *sctx,
 584                     struct pipe_resource *dst, struct pipe_resource *src,
 585                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 586                     unsigned user_flags);
 587 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 588                               uint64_t offset, unsigned size);
 589 void cik_emit_prefetch_L2(struct si_context *sctx);
 590 void si_init_cp_dma_functions(struct si_context *sctx);
 591
 592 /* si_debug.c */
 593 void si_auto_log_cs(void *data, struct u_log_context *log);
 594 void si_log_hw_flush(struct si_context *sctx);
 595 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
 596 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
 597 void si_init_debug_functions(struct si_context *sctx);
 598 void si_check_vm_faults(struct r600_common_context *ctx,
 599                         struct radeon_saved_cs *saved, enum ring_type ring);
 600 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
 601
 602 /* si_dma.c */
 603 void si_init_dma_functions(struct si_context *sctx);
 604
 605 /* si_fence.c */
 606 void si_init_fence_functions(struct si_context *ctx);
 607 void si_init_screen_fence_functions(struct si_screen *screen);
 608 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
 609                                           struct tc_unflushed_batch_token *tc_token);
 610
 611 /* si_hw_context.c */
 612 void si_destroy_saved_cs(struct si_saved_cs *scs);
 613 void si_context_gfx_flush(void *context, unsigned flags,
 614                           struct pipe_fence_handle **fence);
 615 void si_begin_new_cs(struct si_context *ctx);
 616 void si_need_cs_space(struct si_context *ctx);
 617
 618 /* si_compute.c */
 619 void si_init_compute_functions(struct si_context *sctx);
 620
 621 /* si_perfcounters.c */
 622 void si_init_perfcounters(struct si_screen *screen);
 623
 624 /* si_uvd.c */
 625 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 626                                                const struct pipe_video_codec *templ);
 627
 628 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 629                                                  const struct pipe_video_buffer *tmpl);
 630
 631 /* si_viewport.c */
 632 void si_update_vs_viewport_state(struct si_context *ctx);
 633 void si_init_viewport_functions(struct si_context *ctx);
 634
 635
 636 /*
 637  * common helpers
 638  */
 639
 640 static inline void
 641 si_invalidate_draw_sh_constants(struct si_context *sctx)
 642 {
 643         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 644 }
 645
 646 static inline void
 647 si_set_atom_dirty(struct si_context *sctx,
 648                   struct r600_atom *atom, bool dirty)
 649 {
 650         unsigned bit = 1 << atom->id;
 651
 652         if (dirty)
 653                 sctx->dirty_atoms |= bit;
 654         else
 655                 sctx->dirty_atoms &= ~bit;
 656 }
 657
 658 static inline bool
 659 si_is_atom_dirty(struct si_context *sctx,
 660                   struct r600_atom *atom)
 661 {
 662         unsigned bit = 1 << atom->id;
 663
 664         return sctx->dirty_atoms & bit;
 665 }
 666
 667 static inline void
 668 si_mark_atom_dirty(struct si_context *sctx,
 669                    struct r600_atom *atom)
 670 {
 671         si_set_atom_dirty(sctx, atom, true);
 672 }
 673
 674 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
 675 {
 676         if (sctx->gs_shader.cso)
 677                 return &sctx->gs_shader;
 678         if (sctx->tes_shader.cso)
 679                 return &sctx->tes_shader;
 680
 681         return &sctx->vs_shader;
 682 }
 683
 684 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 685 {
 686         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 687
 688         return vs->cso ? &vs->cso->info : NULL;
 689 }
 690
 691 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 692 {
 693         if (sctx->gs_shader.cso)
 694                 return sctx->gs_shader.cso->gs_copy_shader;
 695
 696         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 697         return vs->current ? vs->current : NULL;
 698 }
 699
 700 static inline bool si_get_strmout_en(struct si_context *sctx)
 701 {
 702         return sctx->streamout.streamout_enabled ||
 703                sctx->streamout.prims_gen_query_enabled;
 704 }
 705
 706 static inline unsigned
 707 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
 708 {
 709         unsigned alignment, tcc_cache_line_size;
 710
 711         /* If the upload size is less than the cache line size (e.g. 16, 32),
 712          * the whole thing will fit into a cache line if we align it to its size.
 713          * The idea is that multiple small uploads can share a cache line.
 714          * If the upload size is greater, align it to the cache line size.
 715          */
 716         alignment = util_next_power_of_two(upload_size);
 717         tcc_cache_line_size = sctx->screen->b.info.tcc_cache_line_size;
 718         return MIN2(alignment, tcc_cache_line_size);
 719 }
 720
 721 static inline void
 722 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
 723 {
 724         if (pipe_reference(&(*dst)->reference, &src->reference))
 725                 si_destroy_saved_cs(*dst);
 726
 727         *dst = src;
 728 }
 729
 730 static inline void
 731 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 732                            bool shaders_read_metadata)
 733 {
 734         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
 735                          SI_CONTEXT_INV_VMEM_L1;
 736
 737         if (sctx->b.chip_class >= GFX9) {
 738                 /* Single-sample color is coherent with shaders on GFX9, but
 739                  * L2 metadata must be flushed if shaders read metadata.
 740                  * (DCC, CMASK).
 741                  */
 742                 if (num_samples >= 2)
 743                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 744                 else if (shaders_read_metadata)
 745                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 746         } else {
 747                 /* SI-CI-VI */
 748                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 749         }
 750 }
 751
 752 static inline void
 753 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 754                            bool include_stencil, bool shaders_read_metadata)
 755 {
 756         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
 757                          SI_CONTEXT_INV_VMEM_L1;
 758
 759         if (sctx->b.chip_class >= GFX9) {
 760                 /* Single-sample depth (not stencil) is coherent with shaders
 761                  * on GFX9, but L2 metadata must be flushed if shaders read
 762                  * metadata.
 763                  */
 764                 if (num_samples >= 2 || include_stencil)
 765                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 766                 else if (shaders_read_metadata)
 767                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 768         } else {
 769                 /* SI-CI-VI */
 770                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 771         }
 772 }
 773
 774 #endif