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[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
34
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
37 #else
38 #define SI_BIG_ENDIAN 0
39 #endif
40
41 #define ATI_VENDOR_ID 0x1002
42
43 #define SI_NOT_QUERY 0xffffffff
44
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_NUM_SMOOTH_AA_SAMPLES 8
51 #define SI_GS_PER_ES 128
52 /* Alignment for optimal CP DMA performance. */
53 #define SI_CPDMA_ALIGNMENT 32
54
55 /* Tunables for compute-based clear_buffer and copy_buffer: */
56 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
57 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
58 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
59
60 /* Pipeline & streamout query controls. */
61 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
62 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
63 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
64 /* Instruction cache. */
65 #define SI_CONTEXT_INV_ICACHE (1 << 3)
66 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
67 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
68 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
69 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
70 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
71 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
72 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
73 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
74 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
75 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
76 * a CB or DB flush. */
77 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
78 /* Framebuffer caches. */
79 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
80 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
81 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
82 /* Engine synchronization. */
83 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
84 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
85 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
86 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
87 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
88
89 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
90 #define SI_PREFETCH_LS (1 << 1)
91 #define SI_PREFETCH_HS (1 << 2)
92 #define SI_PREFETCH_ES (1 << 3)
93 #define SI_PREFETCH_GS (1 << 4)
94 #define SI_PREFETCH_VS (1 << 5)
95 #define SI_PREFETCH_PS (1 << 6)
96
97 #define SI_MAX_BORDER_COLORS 4096
98 #define SI_MAX_VIEWPORTS 16
99 #define SIX_BITS 0x3F
100 #define SI_MAP_BUFFER_ALIGNMENT 64
101 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
102
103 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
104 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
105 #define SI_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
106 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
107 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
108 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
109 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
110 #define SI_RESOURCE_FLAG_SO_FILLED_SIZE (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
111
112 /* Debug flags. */
113 enum {
114 /* Shader logging options: */
115 DBG_VS = PIPE_SHADER_VERTEX,
116 DBG_PS = PIPE_SHADER_FRAGMENT,
117 DBG_GS = PIPE_SHADER_GEOMETRY,
118 DBG_TCS = PIPE_SHADER_TESS_CTRL,
119 DBG_TES = PIPE_SHADER_TESS_EVAL,
120 DBG_CS = PIPE_SHADER_COMPUTE,
121 DBG_NO_IR,
122 DBG_NO_TGSI,
123 DBG_NO_ASM,
124 DBG_PREOPT_IR,
125
126 /* Shader compiler options the shader cache should be aware of: */
127 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
128 DBG_UNSAFE_MATH,
129 DBG_SI_SCHED,
130 DBG_GISEL,
131
132 /* Shader compiler options (with no effect on the shader cache): */
133 DBG_CHECK_IR,
134 DBG_NIR,
135 DBG_MONOLITHIC_SHADERS,
136 DBG_NO_OPT_VARIANT,
137
138 /* Information logging options: */
139 DBG_INFO,
140 DBG_TEX,
141 DBG_COMPUTE,
142 DBG_VM,
143
144 /* Driver options: */
145 DBG_FORCE_DMA,
146 DBG_NO_ASYNC_DMA,
147 DBG_NO_WC,
148 DBG_CHECK_VM,
149 DBG_RESERVE_VMID,
150 DBG_ZERO_VRAM,
151
152 /* 3D engine options: */
153 DBG_SWITCH_ON_EOP,
154 DBG_NO_OUT_OF_ORDER,
155 DBG_NO_DPBB,
156 DBG_NO_DFSM,
157 DBG_DPBB,
158 DBG_DFSM,
159 DBG_NO_HYPERZ,
160 DBG_NO_RB_PLUS,
161 DBG_NO_2D_TILING,
162 DBG_NO_TILING,
163 DBG_NO_DCC,
164 DBG_NO_DCC_CLEAR,
165 DBG_NO_DCC_FB,
166 DBG_NO_DCC_MSAA,
167 DBG_NO_FMASK,
168
169 /* Tests: */
170 DBG_TEST_DMA,
171 DBG_TEST_VMFAULT_CP,
172 DBG_TEST_VMFAULT_SDMA,
173 DBG_TEST_VMFAULT_SHADER,
174 DBG_TEST_DMA_PERF,
175 DBG_TEST_GDS,
176 };
177
178 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
179 #define DBG(name) (1ull << DBG_##name)
180
181 enum si_cache_policy {
182 L2_BYPASS,
183 L2_STREAM, /* same as SLC=1 */
184 L2_LRU, /* same as SLC=0 */
185 };
186
187 enum si_coherency {
188 SI_COHERENCY_NONE, /* no cache flushes needed */
189 SI_COHERENCY_SHADER,
190 SI_COHERENCY_CB_META,
191 SI_COHERENCY_CP,
192 };
193
194 struct si_compute;
195 struct hash_table;
196 struct u_suballocator;
197
198 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
199 * at the moment.
200 */
201 struct r600_resource {
202 struct threaded_resource b;
203
204 /* Winsys objects. */
205 struct pb_buffer *buf;
206 uint64_t gpu_address;
207 /* Memory usage if the buffer placement is optimal. */
208 uint64_t vram_usage;
209 uint64_t gart_usage;
210
211 /* Resource properties. */
212 uint64_t bo_size;
213 unsigned bo_alignment;
214 enum radeon_bo_domain domains;
215 enum radeon_bo_flag flags;
216 unsigned bind_history;
217 int max_forced_staging_uploads;
218
219 /* The buffer range which is initialized (with a write transfer,
220 * streamout, DMA, or as a random access target). The rest of
221 * the buffer is considered invalid and can be mapped unsynchronized.
222 *
223 * This allows unsychronized mapping of a buffer range which hasn't
224 * been used yet. It's for applications which forget to use
225 * the unsynchronized map flag and expect the driver to figure it out.
226 */
227 struct util_range valid_buffer_range;
228
229 /* For buffers only. This indicates that a write operation has been
230 * performed by TC L2, but the cache hasn't been flushed.
231 * Any hw block which doesn't use or bypasses TC L2 should check this
232 * flag and flush the cache before using the buffer.
233 *
234 * For example, TC L2 must be flushed if a buffer which has been
235 * modified by a shader store instruction is about to be used as
236 * an index buffer. The reason is that VGT DMA index fetching doesn't
237 * use TC L2.
238 */
239 bool TC_L2_dirty;
240
241 /* Whether this resource is referenced by bindless handles. */
242 bool texture_handle_allocated;
243 bool image_handle_allocated;
244
245 /* Whether the resource has been exported via resource_get_handle. */
246 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
247 };
248
249 struct si_transfer {
250 struct threaded_transfer b;
251 struct r600_resource *staging;
252 unsigned offset;
253 };
254
255 struct si_texture {
256 struct r600_resource buffer;
257
258 struct radeon_surf surface;
259 uint64_t size;
260 struct si_texture *flushed_depth_texture;
261
262 /* Colorbuffer compression and fast clear. */
263 uint64_t fmask_offset;
264 uint64_t cmask_offset;
265 uint64_t cmask_base_address_reg;
266 struct r600_resource *cmask_buffer;
267 uint64_t dcc_offset; /* 0 = disabled */
268 unsigned cb_color_info; /* fast clear enable bit */
269 unsigned color_clear_value[2];
270 unsigned last_msaa_resolve_target_micro_mode;
271 unsigned num_level0_transfers;
272
273 /* Depth buffer compression and fast clear. */
274 uint64_t htile_offset;
275 float depth_clear_value;
276 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
277 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
278 enum pipe_format db_render_format:16;
279 uint8_t stencil_clear_value;
280 bool tc_compatible_htile:1;
281 bool depth_cleared:1; /* if it was cleared at least once */
282 bool stencil_cleared:1; /* if it was cleared at least once */
283 bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
284 bool is_depth:1;
285 bool db_compatible:1;
286 bool can_sample_z:1;
287 bool can_sample_s:1;
288
289 /* We need to track DCC dirtiness, because st/dri usually calls
290 * flush_resource twice per frame (not a bug) and we don't wanna
291 * decompress DCC twice. Also, the dirty tracking must be done even
292 * if DCC isn't used, because it's required by the DCC usage analysis
293 * for a possible future enablement.
294 */
295 bool separate_dcc_dirty:1;
296 /* Statistics gathering for the DCC enablement heuristic. */
297 bool dcc_gather_statistics:1;
298 /* Counter that should be non-zero if the texture is bound to a
299 * framebuffer.
300 */
301 unsigned framebuffers_bound;
302 /* Whether the texture is a displayable back buffer and needs DCC
303 * decompression, which is expensive. Therefore, it's enabled only
304 * if statistics suggest that it will pay off and it's allocated
305 * separately. It can't be bound as a sampler by apps. Limited to
306 * target == 2D and last_level == 0. If enabled, dcc_offset contains
307 * the absolute GPUVM address, not the relative one.
308 */
309 struct r600_resource *dcc_separate_buffer;
310 /* When DCC is temporarily disabled, the separate buffer is here. */
311 struct r600_resource *last_dcc_separate_buffer;
312 /* Estimate of how much this color buffer is written to in units of
313 * full-screen draws: ps_invocations / (width * height)
314 * Shader kills, late Z, and blending with trivial discards make it
315 * inaccurate (we need to count CB updates, not PS invocations).
316 */
317 unsigned ps_draw_ratio;
318 /* The number of clears since the last DCC usage analysis. */
319 unsigned num_slow_clears;
320 };
321
322 struct si_surface {
323 struct pipe_surface base;
324
325 /* These can vary with block-compressed textures. */
326 uint16_t width0;
327 uint16_t height0;
328
329 bool color_initialized:1;
330 bool depth_initialized:1;
331
332 /* Misc. color flags. */
333 bool color_is_int8:1;
334 bool color_is_int10:1;
335 bool dcc_incompatible:1;
336
337 /* Color registers. */
338 unsigned cb_color_info;
339 unsigned cb_color_view;
340 unsigned cb_color_attrib;
341 unsigned cb_color_attrib2; /* GFX9 and later */
342 unsigned cb_dcc_control; /* VI and later */
343 unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */
344 unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
345 unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
346 unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
347
348 /* DB registers. */
349 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
350 uint64_t db_stencil_base;
351 uint64_t db_htile_data_base;
352 unsigned db_depth_info;
353 unsigned db_z_info;
354 unsigned db_z_info2; /* GFX9+ */
355 unsigned db_depth_view;
356 unsigned db_depth_size;
357 unsigned db_depth_slice;
358 unsigned db_stencil_info;
359 unsigned db_stencil_info2; /* GFX9+ */
360 unsigned db_htile_surface;
361 };
362
363 struct si_mmio_counter {
364 unsigned busy;
365 unsigned idle;
366 };
367
368 union si_mmio_counters {
369 struct {
370 /* For global GPU load including SDMA. */
371 struct si_mmio_counter gpu;
372
373 /* GRBM_STATUS */
374 struct si_mmio_counter spi;
375 struct si_mmio_counter gui;
376 struct si_mmio_counter ta;
377 struct si_mmio_counter gds;
378 struct si_mmio_counter vgt;
379 struct si_mmio_counter ia;
380 struct si_mmio_counter sx;
381 struct si_mmio_counter wd;
382 struct si_mmio_counter bci;
383 struct si_mmio_counter sc;
384 struct si_mmio_counter pa;
385 struct si_mmio_counter db;
386 struct si_mmio_counter cp;
387 struct si_mmio_counter cb;
388
389 /* SRBM_STATUS2 */
390 struct si_mmio_counter sdma;
391
392 /* CP_STAT */
393 struct si_mmio_counter pfp;
394 struct si_mmio_counter meq;
395 struct si_mmio_counter me;
396 struct si_mmio_counter surf_sync;
397 struct si_mmio_counter cp_dma;
398 struct si_mmio_counter scratch_ram;
399 } named;
400 unsigned array[0];
401 };
402
403 struct si_memory_object {
404 struct pipe_memory_object b;
405 struct pb_buffer *buf;
406 uint32_t stride;
407 };
408
409 /* Saved CS data for debugging features. */
410 struct radeon_saved_cs {
411 uint32_t *ib;
412 unsigned num_dw;
413
414 struct radeon_bo_list_item *bo_list;
415 unsigned bo_count;
416 };
417
418 struct si_screen {
419 struct pipe_screen b;
420 struct radeon_winsys *ws;
421 struct disk_cache *disk_shader_cache;
422
423 struct radeon_info info;
424 uint64_t debug_flags;
425 char renderer_string[183];
426
427 unsigned pa_sc_raster_config;
428 unsigned pa_sc_raster_config_1;
429 unsigned se_tile_repeat;
430 unsigned gs_table_depth;
431 unsigned tess_offchip_block_dw_size;
432 unsigned tess_offchip_ring_size;
433 unsigned tess_factor_ring_size;
434 unsigned vgt_hs_offchip_param;
435 unsigned eqaa_force_coverage_samples;
436 unsigned eqaa_force_z_samples;
437 unsigned eqaa_force_color_samples;
438 bool has_clear_state;
439 bool has_distributed_tess;
440 bool has_draw_indirect_multi;
441 bool has_out_of_order_rast;
442 bool assume_no_z_fights;
443 bool commutative_blend_add;
444 bool clear_db_cache_before_clear;
445 bool has_msaa_sample_loc_bug;
446 bool has_ls_vgpr_init_bug;
447 bool dpbb_allowed;
448 bool dfsm_allowed;
449 bool llvm_has_working_vgpr_indexing;
450
451 /* Whether shaders are monolithic (1-part) or separate (3-part). */
452 bool use_monolithic_shaders;
453 bool record_llvm_ir;
454 bool has_rbplus; /* if RB+ registers exist */
455 bool rbplus_allowed; /* if RB+ is allowed */
456 bool dcc_msaa_allowed;
457 bool cpdma_prefetch_writes_memory;
458
459 struct slab_parent_pool pool_transfers;
460
461 /* Texture filter settings. */
462 int force_aniso; /* -1 = disabled */
463
464 /* Auxiliary context. Mainly used to initialize resources.
465 * It must be locked prior to using and flushed before unlocking. */
466 struct pipe_context *aux_context;
467 mtx_t aux_context_lock;
468
469 /* This must be in the screen, because UE4 uses one context for
470 * compilation and another one for rendering.
471 */
472 unsigned num_compilations;
473 /* Along with ST_DEBUG=precompile, this should show if applications
474 * are loading shaders on demand. This is a monotonic counter.
475 */
476 unsigned num_shaders_created;
477 unsigned num_shader_cache_hits;
478
479 /* GPU load thread. */
480 mtx_t gpu_load_mutex;
481 thrd_t gpu_load_thread;
482 union si_mmio_counters mmio_counters;
483 volatile unsigned gpu_load_stop_thread; /* bool */
484
485 /* Performance counters. */
486 struct si_perfcounters *perfcounters;
487
488 /* If pipe_screen wants to recompute and re-emit the framebuffer,
489 * sampler, and image states of all contexts, it should atomically
490 * increment this.
491 *
492 * Each context will compare this with its own last known value of
493 * the counter before drawing and re-emit the states accordingly.
494 */
495 unsigned dirty_tex_counter;
496
497 /* Atomically increment this counter when an existing texture's
498 * metadata is enabled or disabled in a way that requires changing
499 * contexts' compressed texture binding masks.
500 */
501 unsigned compressed_colortex_counter;
502
503 struct {
504 /* Context flags to set so that all writes from earlier jobs
505 * in the CP are seen by L2 clients.
506 */
507 unsigned cp_to_L2;
508
509 /* Context flags to set so that all writes from earlier jobs
510 * that end in L2 are seen by CP.
511 */
512 unsigned L2_to_cp;
513 } barrier_flags;
514
515 mtx_t shader_parts_mutex;
516 struct si_shader_part *vs_prologs;
517 struct si_shader_part *tcs_epilogs;
518 struct si_shader_part *gs_prologs;
519 struct si_shader_part *ps_prologs;
520 struct si_shader_part *ps_epilogs;
521
522 /* Shader cache in memory.
523 *
524 * Design & limitations:
525 * - The shader cache is per screen (= per process), never saved to
526 * disk, and skips redundant shader compilations from TGSI to bytecode.
527 * - It can only be used with one-variant-per-shader support, in which
528 * case only the main (typically middle) part of shaders is cached.
529 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
530 * variants of VS and TES are cached, so LS and ES aren't.
531 * - GS and CS aren't cached, but it's certainly possible to cache
532 * those as well.
533 */
534 mtx_t shader_cache_mutex;
535 struct hash_table *shader_cache;
536
537 /* Shader compiler queue for multithreaded compilation. */
538 struct util_queue shader_compiler_queue;
539 /* Use at most 3 normal compiler threads on quadcore and better.
540 * Hyperthreaded CPUs report the number of threads, but we want
541 * the number of cores. We only need this many threads for shader-db. */
542 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
543
544 struct util_queue shader_compiler_queue_low_priority;
545 /* Use at most 2 low priority threads on quadcore and better.
546 * We want to minimize the impact on multithreaded Mesa. */
547 struct ac_llvm_compiler compiler_lowp[10];
548 };
549
550 struct si_blend_color {
551 struct pipe_blend_color state;
552 bool any_nonzeros;
553 };
554
555 struct si_sampler_view {
556 struct pipe_sampler_view base;
557 /* [0..7] = image descriptor
558 * [4..7] = buffer descriptor */
559 uint32_t state[8];
560 uint32_t fmask_state[8];
561 const struct legacy_surf_level *base_level_info;
562 ubyte base_level;
563 ubyte block_width;
564 bool is_stencil_sampler;
565 bool is_integer;
566 bool dcc_incompatible;
567 };
568
569 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
570
571 struct si_sampler_state {
572 #ifdef DEBUG
573 unsigned magic;
574 #endif
575 uint32_t val[4];
576 uint32_t integer_val[4];
577 uint32_t upgraded_depth_val[4];
578 };
579
580 struct si_cs_shader_state {
581 struct si_compute *program;
582 struct si_compute *emitted_program;
583 unsigned offset;
584 bool initialized;
585 bool uses_scratch;
586 };
587
588 struct si_samplers {
589 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
590 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
591
592 /* The i-th bit is set if that element is enabled (non-NULL resource). */
593 unsigned enabled_mask;
594 uint32_t needs_depth_decompress_mask;
595 uint32_t needs_color_decompress_mask;
596 };
597
598 struct si_images {
599 struct pipe_image_view views[SI_NUM_IMAGES];
600 uint32_t needs_color_decompress_mask;
601 unsigned enabled_mask;
602 };
603
604 struct si_framebuffer {
605 struct pipe_framebuffer_state state;
606 unsigned colorbuf_enabled_4bit;
607 unsigned spi_shader_col_format;
608 unsigned spi_shader_col_format_alpha;
609 unsigned spi_shader_col_format_blend;
610 unsigned spi_shader_col_format_blend_alpha;
611 ubyte nr_samples:5; /* at most 16xAA */
612 ubyte log_samples:3; /* at most 4 = 16xAA */
613 ubyte nr_color_samples; /* at most 8xAA */
614 ubyte compressed_cb_mask;
615 ubyte uncompressed_cb_mask;
616 ubyte color_is_int8;
617 ubyte color_is_int10;
618 ubyte dirty_cbufs;
619 bool dirty_zsbuf;
620 bool any_dst_linear;
621 bool CB_has_shader_readable_metadata;
622 bool DB_has_shader_readable_metadata;
623 };
624
625 enum si_quant_mode {
626 /* This is the list we want to support. */
627 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
628 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
629 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
630 };
631
632 struct si_signed_scissor {
633 int minx;
634 int miny;
635 int maxx;
636 int maxy;
637 enum si_quant_mode quant_mode;
638 };
639
640 struct si_scissors {
641 unsigned dirty_mask;
642 struct pipe_scissor_state states[SI_MAX_VIEWPORTS];
643 };
644
645 struct si_viewports {
646 unsigned dirty_mask;
647 unsigned depth_range_dirty_mask;
648 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
649 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
650 };
651
652 struct si_clip_state {
653 struct pipe_clip_state state;
654 bool any_nonzeros;
655 };
656
657 struct si_streamout_target {
658 struct pipe_stream_output_target b;
659
660 /* The buffer where BUFFER_FILLED_SIZE is stored. */
661 struct r600_resource *buf_filled_size;
662 unsigned buf_filled_size_offset;
663 bool buf_filled_size_valid;
664
665 unsigned stride_in_dw;
666 };
667
668 struct si_streamout {
669 bool begin_emitted;
670
671 unsigned enabled_mask;
672 unsigned num_targets;
673 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
674
675 unsigned append_bitmask;
676 bool suspended;
677
678 /* External state which comes from the vertex shader,
679 * it must be set explicitly when binding a shader. */
680 uint16_t *stride_in_dw;
681 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
682
683 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
684 unsigned hw_enabled_mask;
685
686 /* The state of VGT_STRMOUT_(CONFIG|EN). */
687 bool streamout_enabled;
688 bool prims_gen_query_enabled;
689 int num_prims_gen_queries;
690 };
691
692 /* A shader state consists of the shader selector, which is a constant state
693 * object shared by multiple contexts and shouldn't be modified, and
694 * the current shader variant selected for this context.
695 */
696 struct si_shader_ctx_state {
697 struct si_shader_selector *cso;
698 struct si_shader *current;
699 };
700
701 #define SI_NUM_VGT_PARAM_KEY_BITS 12
702 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
703
704 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
705 * Some fields are set by state-change calls, most are set by draw_vbo.
706 */
707 union si_vgt_param_key {
708 struct {
709 #ifdef PIPE_ARCH_LITTLE_ENDIAN
710 unsigned prim:4;
711 unsigned uses_instancing:1;
712 unsigned multi_instances_smaller_than_primgroup:1;
713 unsigned primitive_restart:1;
714 unsigned count_from_stream_output:1;
715 unsigned line_stipple_enabled:1;
716 unsigned uses_tess:1;
717 unsigned tess_uses_prim_id:1;
718 unsigned uses_gs:1;
719 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
720 #else /* PIPE_ARCH_BIG_ENDIAN */
721 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
722 unsigned uses_gs:1;
723 unsigned tess_uses_prim_id:1;
724 unsigned uses_tess:1;
725 unsigned line_stipple_enabled:1;
726 unsigned count_from_stream_output:1;
727 unsigned primitive_restart:1;
728 unsigned multi_instances_smaller_than_primgroup:1;
729 unsigned uses_instancing:1;
730 unsigned prim:4;
731 #endif
732 } u;
733 uint32_t index;
734 };
735
736 struct si_texture_handle
737 {
738 unsigned desc_slot;
739 bool desc_dirty;
740 struct pipe_sampler_view *view;
741 struct si_sampler_state sstate;
742 };
743
744 struct si_image_handle
745 {
746 unsigned desc_slot;
747 bool desc_dirty;
748 struct pipe_image_view view;
749 };
750
751 struct si_saved_cs {
752 struct pipe_reference reference;
753 struct si_context *ctx;
754 struct radeon_saved_cs gfx;
755 struct r600_resource *trace_buf;
756 unsigned trace_id;
757
758 unsigned gfx_last_dw;
759 bool flushed;
760 int64_t time_flush;
761 };
762
763 struct si_context {
764 struct pipe_context b; /* base class */
765
766 enum radeon_family family;
767 enum chip_class chip_class;
768
769 struct radeon_winsys *ws;
770 struct radeon_winsys_ctx *ctx;
771 struct radeon_cmdbuf *gfx_cs;
772 struct radeon_cmdbuf *dma_cs;
773 struct pipe_fence_handle *last_gfx_fence;
774 struct pipe_fence_handle *last_sdma_fence;
775 struct r600_resource *eop_bug_scratch;
776 struct u_upload_mgr *cached_gtt_allocator;
777 struct threaded_context *tc;
778 struct u_suballocator *allocator_zeroed_memory;
779 struct slab_child_pool pool_transfers;
780 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
781 struct pipe_device_reset_callback device_reset_callback;
782 struct u_log_context *log;
783 void *query_result_shader;
784 struct blitter_context *blitter;
785 void *custom_dsa_flush;
786 void *custom_blend_resolve;
787 void *custom_blend_fmask_decompress;
788 void *custom_blend_eliminate_fastclear;
789 void *custom_blend_dcc_decompress;
790 void *vs_blit_pos;
791 void *vs_blit_pos_layered;
792 void *vs_blit_color;
793 void *vs_blit_color_layered;
794 void *vs_blit_texcoord;
795 void *cs_clear_buffer;
796 void *cs_copy_buffer;
797 struct si_screen *screen;
798 struct pipe_debug_callback debug;
799 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
800 struct si_shader_ctx_state fixed_func_tcs_shader;
801 struct r600_resource *wait_mem_scratch;
802 unsigned wait_mem_number;
803 uint16_t prefetch_L2_mask;
804
805 bool gfx_flush_in_progress:1;
806 bool gfx_last_ib_is_busy:1;
807 bool compute_is_busy:1;
808
809 unsigned num_gfx_cs_flushes;
810 unsigned initial_gfx_cs_size;
811 unsigned gpu_reset_counter;
812 unsigned last_dirty_tex_counter;
813 unsigned last_compressed_colortex_counter;
814 unsigned last_num_draw_calls;
815 unsigned flags; /* flush flags */
816 /* Current unaccounted memory usage. */
817 uint64_t vram;
818 uint64_t gtt;
819
820 /* Atoms (direct states). */
821 union si_state_atoms atoms;
822 unsigned dirty_atoms; /* mask */
823 /* PM4 states (precomputed immutable states) */
824 unsigned dirty_states;
825 union si_state queued;
826 union si_state emitted;
827
828 /* Atom declarations. */
829 struct si_framebuffer framebuffer;
830 unsigned sample_locs_num_samples;
831 uint16_t sample_mask;
832 unsigned last_cb_target_mask;
833 struct si_blend_color blend_color;
834 struct si_clip_state clip_state;
835 struct si_shader_data shader_pointers;
836 struct si_stencil_ref stencil_ref;
837 struct si_scissors scissors;
838 struct si_streamout streamout;
839 struct si_viewports viewports;
840 unsigned num_window_rectangles;
841 bool window_rectangles_include;
842 struct pipe_scissor_state window_rectangles[4];
843
844 /* Precomputed states. */
845 struct si_pm4_state *init_config;
846 struct si_pm4_state *init_config_gs_rings;
847 bool init_config_has_vgt_flush;
848 struct si_pm4_state *vgt_shader_config[4];
849
850 /* shaders */
851 struct si_shader_ctx_state ps_shader;
852 struct si_shader_ctx_state gs_shader;
853 struct si_shader_ctx_state vs_shader;
854 struct si_shader_ctx_state tcs_shader;
855 struct si_shader_ctx_state tes_shader;
856 struct si_cs_shader_state cs_shader_state;
857
858 /* shader information */
859 struct si_vertex_elements *vertex_elements;
860 unsigned sprite_coord_enable;
861 unsigned cs_max_waves_per_sh;
862 bool flatshade;
863 bool do_update_shaders;
864
865 /* vertex buffer descriptors */
866 uint32_t *vb_descriptors_gpu_list;
867 struct r600_resource *vb_descriptors_buffer;
868 unsigned vb_descriptors_offset;
869
870 /* shader descriptors */
871 struct si_descriptors descriptors[SI_NUM_DESCS];
872 unsigned descriptors_dirty;
873 unsigned shader_pointers_dirty;
874 unsigned shader_needs_decompress_mask;
875 struct si_buffer_resources rw_buffers;
876 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
877 struct si_samplers samplers[SI_NUM_SHADERS];
878 struct si_images images[SI_NUM_SHADERS];
879
880 /* other shader resources */
881 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
882 struct pipe_resource *esgs_ring;
883 struct pipe_resource *gsvs_ring;
884 struct pipe_resource *tess_rings;
885 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
886 struct r600_resource *border_color_buffer;
887 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
888 unsigned border_color_count;
889 unsigned num_vs_blit_sgprs;
890 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
891 uint32_t cs_user_data[4];
892
893 /* Vertex and index buffers. */
894 bool vertex_buffers_dirty;
895 bool vertex_buffer_pointer_dirty;
896 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
897
898 /* MSAA config state. */
899 int ps_iter_samples;
900 bool ps_uses_fbfetch;
901 bool smoothing_enabled;
902
903 /* DB render state. */
904 unsigned ps_db_shader_control;
905 unsigned dbcb_copy_sample;
906 bool dbcb_depth_copy_enabled:1;
907 bool dbcb_stencil_copy_enabled:1;
908 bool db_flush_depth_inplace:1;
909 bool db_flush_stencil_inplace:1;
910 bool db_depth_clear:1;
911 bool db_depth_disable_expclear:1;
912 bool db_stencil_clear:1;
913 bool db_stencil_disable_expclear:1;
914 bool occlusion_queries_disabled:1;
915 bool generate_mipmap_for_depth:1;
916
917 /* Emitted draw state. */
918 bool gs_tri_strip_adj_fix:1;
919 bool ls_vgpr_fix:1;
920 int last_index_size;
921 int last_base_vertex;
922 int last_start_instance;
923 int last_drawid;
924 int last_sh_base_reg;
925 int last_primitive_restart_en;
926 int last_restart_index;
927 int last_prim;
928 int last_multi_vgt_param;
929 int last_rast_prim;
930 unsigned last_sc_line_stipple;
931 unsigned current_vs_state;
932 unsigned last_vs_state;
933 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
934
935 /* Scratch buffer */
936 struct r600_resource *scratch_buffer;
937 unsigned scratch_waves;
938 unsigned spi_tmpring_size;
939
940 struct r600_resource *compute_scratch_buffer;
941
942 /* Emitted derived tessellation state. */
943 /* Local shader (VS), or HS if LS-HS are merged. */
944 struct si_shader *last_ls;
945 struct si_shader_selector *last_tcs;
946 int last_num_tcs_input_cp;
947 int last_tes_sh_base;
948 bool last_tess_uses_primid;
949 unsigned last_num_patches;
950 int last_ls_hs_config;
951
952 /* Debug state. */
953 bool is_debug;
954 struct si_saved_cs *current_saved_cs;
955 uint64_t dmesg_timestamp;
956 unsigned apitrace_call_number;
957
958 /* Other state */
959 bool need_check_render_feedback;
960 bool decompression_enabled;
961 bool dpbb_force_off;
962 bool vs_writes_viewport_index;
963 bool vs_disables_clipping_viewport;
964
965 /* Precomputed IA_MULTI_VGT_PARAM */
966 union si_vgt_param_key ia_multi_vgt_param_key;
967 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
968
969 /* Bindless descriptors. */
970 struct si_descriptors bindless_descriptors;
971 struct util_idalloc bindless_used_slots;
972 unsigned num_bindless_descriptors;
973 bool bindless_descriptors_dirty;
974 bool graphics_bindless_pointer_dirty;
975 bool compute_bindless_pointer_dirty;
976
977 /* Allocated bindless handles */
978 struct hash_table *tex_handles;
979 struct hash_table *img_handles;
980
981 /* Resident bindless handles */
982 struct util_dynarray resident_tex_handles;
983 struct util_dynarray resident_img_handles;
984
985 /* Resident bindless handles which need decompression */
986 struct util_dynarray resident_tex_needs_color_decompress;
987 struct util_dynarray resident_img_needs_color_decompress;
988 struct util_dynarray resident_tex_needs_depth_decompress;
989
990 /* Bindless state */
991 bool uses_bindless_samplers;
992 bool uses_bindless_images;
993
994 /* MSAA sample locations.
995 * The first index is the sample index.
996 * The second index is the coordinate: X, Y. */
997 struct {
998 float x1[1][2];
999 float x2[2][2];
1000 float x4[4][2];
1001 float x8[8][2];
1002 float x16[16][2];
1003 } sample_positions;
1004 struct pipe_resource *sample_pos_buffer;
1005
1006 /* Misc stats. */
1007 unsigned num_draw_calls;
1008 unsigned num_decompress_calls;
1009 unsigned num_mrt_draw_calls;
1010 unsigned num_prim_restart_calls;
1011 unsigned num_spill_draw_calls;
1012 unsigned num_compute_calls;
1013 unsigned num_spill_compute_calls;
1014 unsigned num_dma_calls;
1015 unsigned num_cp_dma_calls;
1016 unsigned num_vs_flushes;
1017 unsigned num_ps_flushes;
1018 unsigned num_cs_flushes;
1019 unsigned num_cb_cache_flushes;
1020 unsigned num_db_cache_flushes;
1021 unsigned num_L2_invalidates;
1022 unsigned num_L2_writebacks;
1023 unsigned num_resident_handles;
1024 uint64_t num_alloc_tex_transfer_bytes;
1025 unsigned last_tex_ps_draw_ratio; /* for query */
1026
1027 /* Queries. */
1028 /* Maintain the list of active queries for pausing between IBs. */
1029 int num_occlusion_queries;
1030 int num_perfect_occlusion_queries;
1031 struct list_head active_queries;
1032 unsigned num_cs_dw_queries_suspend;
1033
1034 /* Render condition. */
1035 struct pipe_query *render_cond;
1036 unsigned render_cond_mode;
1037 bool render_cond_invert;
1038 bool render_cond_force_off; /* for u_blitter */
1039
1040 /* Statistics gathering for the DCC enablement heuristic. It can't be
1041 * in si_texture because si_texture can be shared by multiple
1042 * contexts. This is for back buffers only. We shouldn't get too many
1043 * of those.
1044 *
1045 * X11 DRI3 rotates among a finite set of back buffers. They should
1046 * all fit in this array. If they don't, separate DCC might never be
1047 * enabled by DCC stat gathering.
1048 */
1049 struct {
1050 struct si_texture *tex;
1051 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1052 struct pipe_query *ps_stats[3];
1053 /* If all slots are used and another slot is needed,
1054 * the least recently used slot is evicted based on this. */
1055 int64_t last_use_timestamp;
1056 bool query_active;
1057 } dcc_stats[5];
1058
1059 /* Copy one resource to another using async DMA. */
1060 void (*dma_copy)(struct pipe_context *ctx,
1061 struct pipe_resource *dst,
1062 unsigned dst_level,
1063 unsigned dst_x, unsigned dst_y, unsigned dst_z,
1064 struct pipe_resource *src,
1065 unsigned src_level,
1066 const struct pipe_box *src_box);
1067
1068 struct si_tracked_regs tracked_regs;
1069 };
1070
1071 /* cik_sdma.c */
1072 void cik_init_sdma_functions(struct si_context *sctx);
1073
1074 /* si_blit.c */
1075 enum si_blitter_op /* bitmask */
1076 {
1077 SI_SAVE_TEXTURES = 1,
1078 SI_SAVE_FRAMEBUFFER = 2,
1079 SI_SAVE_FRAGMENT_STATE = 4,
1080 SI_DISABLE_RENDER_COND = 8,
1081 };
1082
1083 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1084 void si_blitter_end(struct si_context *sctx);
1085 void si_init_blit_functions(struct si_context *sctx);
1086 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1087 void si_resource_copy_region(struct pipe_context *ctx,
1088 struct pipe_resource *dst,
1089 unsigned dst_level,
1090 unsigned dstx, unsigned dsty, unsigned dstz,
1091 struct pipe_resource *src,
1092 unsigned src_level,
1093 const struct pipe_box *src_box);
1094 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1095 void si_blit_decompress_depth(struct pipe_context *ctx,
1096 struct si_texture *texture,
1097 struct si_texture *staging,
1098 unsigned first_level, unsigned last_level,
1099 unsigned first_layer, unsigned last_layer,
1100 unsigned first_sample, unsigned last_sample);
1101
1102 /* si_buffer.c */
1103 bool si_rings_is_buffer_referenced(struct si_context *sctx,
1104 struct pb_buffer *buf,
1105 enum radeon_bo_usage usage);
1106 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
1107 struct r600_resource *resource,
1108 unsigned usage);
1109 void si_init_resource_fields(struct si_screen *sscreen,
1110 struct r600_resource *res,
1111 uint64_t size, unsigned alignment);
1112 bool si_alloc_resource(struct si_screen *sscreen,
1113 struct r600_resource *res);
1114 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
1115 unsigned flags, unsigned usage,
1116 unsigned size, unsigned alignment);
1117 struct r600_resource *si_aligned_buffer_create(struct pipe_screen *screen,
1118 unsigned flags, unsigned usage,
1119 unsigned size, unsigned alignment);
1120 void si_replace_buffer_storage(struct pipe_context *ctx,
1121 struct pipe_resource *dst,
1122 struct pipe_resource *src);
1123 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1124 void si_init_buffer_functions(struct si_context *sctx);
1125
1126 /* si_clear.c */
1127 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1128 bool vi_alpha_is_on_msb(enum pipe_format format);
1129 void vi_dcc_clear_level(struct si_context *sctx,
1130 struct si_texture *tex,
1131 unsigned level, unsigned clear_value);
1132 void si_init_clear_functions(struct si_context *sctx);
1133
1134 /* si_compute_blit.c */
1135 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1136 enum si_cache_policy cache_policy);
1137 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1138 uint64_t offset, uint64_t size, uint32_t *clear_value,
1139 uint32_t clear_value_size, enum si_coherency coher);
1140 void si_copy_buffer(struct si_context *sctx,
1141 struct pipe_resource *dst, struct pipe_resource *src,
1142 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1143 void si_init_compute_blit_functions(struct si_context *sctx);
1144
1145 /* si_cp_dma.c */
1146 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1147 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1148 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1149 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1150 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1151 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1152 SI_CPDMA_SKIP_SYNC_AFTER | \
1153 SI_CPDMA_SKIP_SYNC_BEFORE | \
1154 SI_CPDMA_SKIP_GFX_SYNC | \
1155 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1156
1157 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1158 void si_cp_dma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1159 uint64_t offset, uint64_t size, unsigned value,
1160 enum si_coherency coher,
1161 enum si_cache_policy cache_policy);
1162 void si_cp_dma_copy_buffer(struct si_context *sctx,
1163 struct pipe_resource *dst, struct pipe_resource *src,
1164 uint64_t dst_offset, uint64_t src_offset, unsigned size,
1165 unsigned user_flags, enum si_coherency coher,
1166 enum si_cache_policy cache_policy);
1167 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
1168 uint64_t offset, unsigned size);
1169 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1170 void si_test_gds(struct si_context *sctx);
1171
1172 /* si_debug.c */
1173 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
1174 struct radeon_saved_cs *saved, bool get_buffer_list);
1175 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1176 void si_destroy_saved_cs(struct si_saved_cs *scs);
1177 void si_auto_log_cs(void *data, struct u_log_context *log);
1178 void si_log_hw_flush(struct si_context *sctx);
1179 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1180 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1181 void si_init_debug_functions(struct si_context *sctx);
1182 void si_check_vm_faults(struct si_context *sctx,
1183 struct radeon_saved_cs *saved, enum ring_type ring);
1184 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
1185
1186 /* si_dma.c */
1187 void si_init_dma_functions(struct si_context *sctx);
1188
1189 /* si_dma_cs.c */
1190 void si_dma_emit_timestamp(struct si_context *sctx, struct r600_resource *dst,
1191 uint64_t offset);
1192 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1193 uint64_t offset, uint64_t size, unsigned clear_value);
1194 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
1195 struct r600_resource *dst, struct r600_resource *src);
1196 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
1197 struct pipe_fence_handle **fence);
1198 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
1199 uint64_t offset, uint64_t size, unsigned value);
1200
1201 /* si_fence.c */
1202 void si_cp_release_mem(struct si_context *ctx,
1203 unsigned event, unsigned event_flags,
1204 unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1205 struct r600_resource *buf, uint64_t va,
1206 uint32_t new_fence, unsigned query_type);
1207 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1208 void si_cp_wait_mem(struct si_context *ctx,
1209 uint64_t va, uint32_t ref, uint32_t mask, unsigned flags);
1210 void si_init_fence_functions(struct si_context *ctx);
1211 void si_init_screen_fence_functions(struct si_screen *screen);
1212 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1213 struct tc_unflushed_batch_token *tc_token);
1214
1215 /* si_get.c */
1216 void si_init_screen_get_functions(struct si_screen *sscreen);
1217
1218 /* si_gfx_cs.c */
1219 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
1220 struct pipe_fence_handle **fence);
1221 void si_begin_new_gfx_cs(struct si_context *ctx);
1222 void si_need_gfx_cs_space(struct si_context *ctx);
1223
1224 /* r600_gpu_load.c */
1225 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1226 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1227 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
1228 uint64_t begin);
1229
1230 /* si_compute.c */
1231 void si_init_compute_functions(struct si_context *sctx);
1232
1233 /* r600_perfcounters.c */
1234 void si_perfcounters_destroy(struct si_screen *sscreen);
1235
1236 /* si_perfcounters.c */
1237 void si_init_perfcounters(struct si_screen *screen);
1238
1239 /* si_pipe.c */
1240 bool si_check_device_reset(struct si_context *sctx);
1241
1242 /* si_query.c */
1243 void si_init_screen_query_functions(struct si_screen *sscreen);
1244 void si_init_query_functions(struct si_context *sctx);
1245 void si_suspend_queries(struct si_context *sctx);
1246 void si_resume_queries(struct si_context *sctx);
1247
1248 /* si_shaderlib_tgsi.c */
1249 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1250 unsigned num_layers);
1251 void *si_create_fixed_func_tcs(struct si_context *sctx);
1252 void *si_create_dma_compute_shader(struct pipe_context *ctx,
1253 unsigned num_dwords_per_thread,
1254 bool dst_stream_cache_policy, bool is_copy);
1255 void *si_create_query_result_cs(struct si_context *sctx);
1256
1257 /* si_test_dma.c */
1258 void si_test_dma(struct si_screen *sscreen);
1259
1260 /* si_test_clearbuffer.c */
1261 void si_test_dma_perf(struct si_screen *sscreen);
1262
1263 /* si_uvd.c */
1264 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1265 const struct pipe_video_codec *templ);
1266
1267 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1268 const struct pipe_video_buffer *tmpl);
1269
1270 /* si_viewport.c */
1271 void si_update_vs_viewport_state(struct si_context *ctx);
1272 void si_init_viewport_functions(struct si_context *ctx);
1273
1274 /* si_texture.c */
1275 bool si_prepare_for_dma_blit(struct si_context *sctx,
1276 struct si_texture *dst,
1277 unsigned dst_level, unsigned dstx,
1278 unsigned dsty, unsigned dstz,
1279 struct si_texture *src,
1280 unsigned src_level,
1281 const struct pipe_box *src_box);
1282 void si_eliminate_fast_color_clear(struct si_context *sctx,
1283 struct si_texture *tex);
1284 void si_texture_discard_cmask(struct si_screen *sscreen,
1285 struct si_texture *tex);
1286 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1287 struct pipe_resource *texture,
1288 struct si_texture **staging);
1289 void si_print_texture_info(struct si_screen *sscreen,
1290 struct si_texture *tex, struct u_log_context *log);
1291 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1292 const struct pipe_resource *templ);
1293 bool vi_dcc_formats_compatible(enum pipe_format format1,
1294 enum pipe_format format2);
1295 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1296 unsigned level,
1297 enum pipe_format view_format);
1298 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1299 struct pipe_resource *tex,
1300 unsigned level,
1301 enum pipe_format view_format);
1302 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1303 struct pipe_resource *texture,
1304 const struct pipe_surface *templ,
1305 unsigned width0, unsigned height0,
1306 unsigned width, unsigned height);
1307 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1308 void vi_separate_dcc_try_enable(struct si_context *sctx,
1309 struct si_texture *tex);
1310 void vi_separate_dcc_start_query(struct si_context *sctx,
1311 struct si_texture *tex);
1312 void vi_separate_dcc_stop_query(struct si_context *sctx,
1313 struct si_texture *tex);
1314 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1315 struct si_texture *tex);
1316 bool si_texture_disable_dcc(struct si_context *sctx,
1317 struct si_texture *tex);
1318 void si_init_screen_texture_functions(struct si_screen *sscreen);
1319 void si_init_context_texture_functions(struct si_context *sctx);
1320
1321
1322 /*
1323 * common helpers
1324 */
1325
1326 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
1327 {
1328 return (struct r600_resource*)r;
1329 }
1330
1331 static inline void
1332 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
1333 {
1334 pipe_resource_reference((struct pipe_resource **)ptr,
1335 (struct pipe_resource *)res);
1336 }
1337
1338 static inline void
1339 si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1340 {
1341 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1342 }
1343
1344 static inline bool
1345 vi_dcc_enabled(struct si_texture *tex, unsigned level)
1346 {
1347 return tex->dcc_offset && level < tex->surface.num_dcc_levels;
1348 }
1349
1350 static inline unsigned
1351 si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1352 {
1353 if (stencil)
1354 return tex->surface.u.legacy.stencil_tiling_index[level];
1355 else
1356 return tex->surface.u.legacy.tiling_index[level];
1357 }
1358
1359 static inline void
1360 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1361 {
1362 if (r) {
1363 /* Add memory usage for need_gfx_cs_space */
1364 sctx->vram += r600_resource(r)->vram_usage;
1365 sctx->gtt += r600_resource(r)->gart_usage;
1366 }
1367 }
1368
1369 static inline void
1370 si_invalidate_draw_sh_constants(struct si_context *sctx)
1371 {
1372 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1373 }
1374
1375 static inline unsigned
1376 si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1377 {
1378 return 1 << (atom - sctx->atoms.array);
1379 }
1380
1381 static inline void
1382 si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1383 {
1384 unsigned bit = si_get_atom_bit(sctx, atom);
1385
1386 if (dirty)
1387 sctx->dirty_atoms |= bit;
1388 else
1389 sctx->dirty_atoms &= ~bit;
1390 }
1391
1392 static inline bool
1393 si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1394 {
1395 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1396 }
1397
1398 static inline void
1399 si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1400 {
1401 si_set_atom_dirty(sctx, atom, true);
1402 }
1403
1404 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1405 {
1406 if (sctx->gs_shader.cso)
1407 return &sctx->gs_shader;
1408 if (sctx->tes_shader.cso)
1409 return &sctx->tes_shader;
1410
1411 return &sctx->vs_shader;
1412 }
1413
1414 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1415 {
1416 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1417
1418 return vs->cso ? &vs->cso->info : NULL;
1419 }
1420
1421 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1422 {
1423 if (sctx->gs_shader.cso)
1424 return sctx->gs_shader.cso->gs_copy_shader;
1425
1426 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1427 return vs->current ? vs->current : NULL;
1428 }
1429
1430 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1431 unsigned processor)
1432 {
1433 return sscreen->debug_flags & (1 << processor);
1434 }
1435
1436 static inline bool si_get_strmout_en(struct si_context *sctx)
1437 {
1438 return sctx->streamout.streamout_enabled ||
1439 sctx->streamout.prims_gen_query_enabled;
1440 }
1441
1442 static inline unsigned
1443 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1444 {
1445 unsigned alignment, tcc_cache_line_size;
1446
1447 /* If the upload size is less than the cache line size (e.g. 16, 32),
1448 * the whole thing will fit into a cache line if we align it to its size.
1449 * The idea is that multiple small uploads can share a cache line.
1450 * If the upload size is greater, align it to the cache line size.
1451 */
1452 alignment = util_next_power_of_two(upload_size);
1453 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1454 return MIN2(alignment, tcc_cache_line_size);
1455 }
1456
1457 static inline void
1458 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1459 {
1460 if (pipe_reference(&(*dst)->reference, &src->reference))
1461 si_destroy_saved_cs(*dst);
1462
1463 *dst = src;
1464 }
1465
1466 static inline void
1467 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1468 bool shaders_read_metadata)
1469 {
1470 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1471 SI_CONTEXT_INV_VMEM_L1;
1472
1473 if (sctx->chip_class >= GFX9) {
1474 /* Single-sample color is coherent with shaders on GFX9, but
1475 * L2 metadata must be flushed if shaders read metadata.
1476 * (DCC, CMASK).
1477 */
1478 if (num_samples >= 2)
1479 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1480 else if (shaders_read_metadata)
1481 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1482 } else {
1483 /* SI-CI-VI */
1484 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1485 }
1486 }
1487
1488 static inline void
1489 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1490 bool include_stencil, bool shaders_read_metadata)
1491 {
1492 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1493 SI_CONTEXT_INV_VMEM_L1;
1494
1495 if (sctx->chip_class >= GFX9) {
1496 /* Single-sample depth (not stencil) is coherent with shaders
1497 * on GFX9, but L2 metadata must be flushed if shaders read
1498 * metadata.
1499 */
1500 if (num_samples >= 2 || include_stencil)
1501 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1502 else if (shaders_read_metadata)
1503 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1504 } else {
1505 /* SI-CI-VI */
1506 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1507 }
1508 }
1509
1510 static inline bool
1511 si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1512 {
1513 return (stencil_sampler && tex->can_sample_s) ||
1514 (!stencil_sampler && tex->can_sample_z);
1515 }
1516
1517 static inline bool
1518 si_htile_enabled(struct si_texture *tex, unsigned level)
1519 {
1520 return tex->htile_offset && level == 0;
1521 }
1522
1523 static inline bool
1524 vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level)
1525 {
1526 assert(!tex->tc_compatible_htile || tex->htile_offset);
1527 return tex->tc_compatible_htile && level == 0;
1528 }
1529
1530 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1531 {
1532 if (sctx->ps_uses_fbfetch)
1533 return sctx->framebuffer.nr_color_samples;
1534
1535 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1536 }
1537
1538 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1539 {
1540 if (sctx->queued.named.rasterizer->rasterizer_discard)
1541 return 0;
1542
1543 struct si_shader_selector *ps = sctx->ps_shader.cso;
1544 if (!ps)
1545 return 0;
1546
1547 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1548 sctx->queued.named.blend->cb_target_mask;
1549
1550 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1551 colormask &= ps->colors_written_4bit;
1552 else if (!ps->colors_written_4bit)
1553 colormask = 0; /* color0 writes all cbufs, but it's not written */
1554
1555 return colormask;
1556 }
1557
1558 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1559 (1 << PIPE_PRIM_LINE_LOOP) | \
1560 (1 << PIPE_PRIM_LINE_STRIP) | \
1561 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1562 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1563
1564 static inline bool util_prim_is_lines(unsigned prim)
1565 {
1566 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1567 }
1568
1569 static inline bool util_prim_is_points_or_lines(unsigned prim)
1570 {
1571 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES |
1572 (1 << PIPE_PRIM_POINTS))) != 0;
1573 }
1574
1575 /**
1576 * Return true if there is enough memory in VRAM and GTT for the buffers
1577 * added so far.
1578 *
1579 * \param vram VRAM memory size not added to the buffer list yet
1580 * \param gtt GTT memory size not added to the buffer list yet
1581 */
1582 static inline bool
1583 radeon_cs_memory_below_limit(struct si_screen *screen,
1584 struct radeon_cmdbuf *cs,
1585 uint64_t vram, uint64_t gtt)
1586 {
1587 vram += cs->used_vram;
1588 gtt += cs->used_gart;
1589
1590 /* Anything that goes above the VRAM size should go to GTT. */
1591 if (vram > screen->info.vram_size)
1592 gtt += vram - screen->info.vram_size;
1593
1594 /* Now we just need to check if we have enough GTT. */
1595 return gtt < screen->info.gart_size * 0.7;
1596 }
1597
1598 /**
1599 * Add a buffer to the buffer list for the given command stream (CS).
1600 *
1601 * All buffers used by a CS must be added to the list. This tells the kernel
1602 * driver which buffers are used by GPU commands. Other buffers can
1603 * be swapped out (not accessible) during execution.
1604 *
1605 * The buffer list becomes empty after every context flush and must be
1606 * rebuilt.
1607 */
1608 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1609 struct radeon_cmdbuf *cs,
1610 struct r600_resource *rbo,
1611 enum radeon_bo_usage usage,
1612 enum radeon_bo_priority priority)
1613 {
1614 assert(usage);
1615 sctx->ws->cs_add_buffer(
1616 cs, rbo->buf,
1617 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1618 rbo->domains, priority);
1619 }
1620
1621 /**
1622 * Same as above, but also checks memory usage and flushes the context
1623 * accordingly.
1624 *
1625 * When this SHOULD NOT be used:
1626 *
1627 * - if si_context_add_resource_size has been called for the buffer
1628 * followed by *_need_cs_space for checking the memory usage
1629 *
1630 * - if si_need_dma_space has been called for the buffer
1631 *
1632 * - when emitting state packets and draw packets (because preceding packets
1633 * can't be re-emitted at that point)
1634 *
1635 * - if shader resource "enabled_mask" is not up-to-date or there is
1636 * a different constraint disallowing a context flush
1637 */
1638 static inline void
1639 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1640 struct r600_resource *rbo,
1641 enum radeon_bo_usage usage,
1642 enum radeon_bo_priority priority,
1643 bool check_mem)
1644 {
1645 if (check_mem &&
1646 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1647 sctx->vram + rbo->vram_usage,
1648 sctx->gtt + rbo->gart_usage))
1649 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1650
1651 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, rbo, usage, priority);
1652 }
1653
1654 #define PRINT_ERR(fmt, args...) \
1655 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1656
1657 #endif