src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef SI_PIPE_H
  24 #define SI_PIPE_H
  25
  26 #include "si_shader.h"
  27
  28 #include "util/u_dynarray.h"
  29 #include "util/u_idalloc.h"
  30
  31 #ifdef PIPE_ARCH_BIG_ENDIAN
  32 #define SI_BIG_ENDIAN 1
  33 #else
  34 #define SI_BIG_ENDIAN 0
  35 #endif
  36
  37 #define ATI_VENDOR_ID 0x1002
  38
  39 #define SI_NOT_QUERY            0xffffffff
  40
  41 /* The base vertex and primitive restart can be any number, but we must pick
  42  * one which will mean "unknown" for the purpose of state tracking and
  43  * the number shouldn't be a commonly-used one. */
  44 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  45 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  46 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  47 #define SI_GS_PER_ES 128
  48 /* Alignment for optimal CP DMA performance. */
  49 #define SI_CPDMA_ALIGNMENT      32
  50
  51 /* Pipeline & streamout query controls. */
  52 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
  53 #define SI_CONTEXT_STOP_PIPELINE_STATS  (1 << 1)
  54 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
  55 /* Instruction cache. */
  56 #define SI_CONTEXT_INV_ICACHE           (1 << 3)
  57 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  58 #define SI_CONTEXT_INV_SMEM_L1          (1 << 4)
  59 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  60 #define SI_CONTEXT_INV_VMEM_L1          (1 << 5)
  61 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  62 #define SI_CONTEXT_INV_GLOBAL_L2        (1 << 6)
  63 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  64  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
  65 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2  (1 << 7)
  66 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
  67  * a CB or DB flush. */
  68 #define SI_CONTEXT_INV_L2_METADATA      (1 << 8)
  69 /* Framebuffer caches. */
  70 #define SI_CONTEXT_FLUSH_AND_INV_DB     (1 << 9)
  71 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
  72 #define SI_CONTEXT_FLUSH_AND_INV_CB     (1 << 11)
  73 /* Engine synchronization. */
  74 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (1 << 12)
  75 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (1 << 13)
  76 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (1 << 14)
  77 #define SI_CONTEXT_VGT_FLUSH            (1 << 15)
  78 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (1 << 16)
  79
  80 #define SI_PREFETCH_VBO_DESCRIPTORS     (1 << 0)
  81 #define SI_PREFETCH_LS                  (1 << 1)
  82 #define SI_PREFETCH_HS                  (1 << 2)
  83 #define SI_PREFETCH_ES                  (1 << 3)
  84 #define SI_PREFETCH_GS                  (1 << 4)
  85 #define SI_PREFETCH_VS                  (1 << 5)
  86 #define SI_PREFETCH_PS                  (1 << 6)
  87
  88 #define SI_MAX_BORDER_COLORS    4096
  89 #define SI_MAX_VIEWPORTS        16
  90 #define SIX_BITS                0x3F
  91
  92 struct si_compute;
  93 struct hash_table;
  94 struct u_suballocator;
  95
  96 struct si_screen {
  97         struct pipe_screen              b;
  98         struct radeon_winsys            *ws;
  99         struct disk_cache               *disk_shader_cache;
 100
 101         struct radeon_info              info;
 102         uint64_t                        debug_flags;
 103         char                            renderer_string[100];
 104
 105         unsigned                        gs_table_depth;
 106         unsigned                        tess_offchip_block_dw_size;
 107         unsigned                        tess_offchip_ring_size;
 108         unsigned                        tess_factor_ring_size;
 109         unsigned                        vgt_hs_offchip_param;
 110         bool                            has_clear_state;
 111         bool                            has_distributed_tess;
 112         bool                            has_draw_indirect_multi;
 113         bool                            has_out_of_order_rast;
 114         bool                            assume_no_z_fights;
 115         bool                            commutative_blend_add;
 116         bool                            clear_db_cache_before_clear;
 117         bool                            has_msaa_sample_loc_bug;
 118         bool                            has_ls_vgpr_init_bug;
 119         bool                            dpbb_allowed;
 120         bool                            dfsm_allowed;
 121         bool                            llvm_has_working_vgpr_indexing;
 122
 123         /* Whether shaders are monolithic (1-part) or separate (3-part). */
 124         bool                            use_monolithic_shaders;
 125         bool                            record_llvm_ir;
 126         bool                            has_rbplus;     /* if RB+ registers exist */
 127         bool                            rbplus_allowed; /* if RB+ is allowed */
 128         bool                            dcc_msaa_allowed;
 129         bool                            cpdma_prefetch_writes_memory;
 130
 131         struct slab_parent_pool         pool_transfers;
 132
 133         /* Texture filter settings. */
 134         int                             force_aniso; /* -1 = disabled */
 135
 136         /* Auxiliary context. Mainly used to initialize resources.
 137          * It must be locked prior to using and flushed before unlocking. */
 138         struct pipe_context             *aux_context;
 139         mtx_t                           aux_context_lock;
 140
 141         /* This must be in the screen, because UE4 uses one context for
 142          * compilation and another one for rendering.
 143          */
 144         unsigned                        num_compilations;
 145         /* Along with ST_DEBUG=precompile, this should show if applications
 146          * are loading shaders on demand. This is a monotonic counter.
 147          */
 148         unsigned                        num_shaders_created;
 149         unsigned                        num_shader_cache_hits;
 150
 151         /* GPU load thread. */
 152         mtx_t                           gpu_load_mutex;
 153         thrd_t                          gpu_load_thread;
 154         union r600_mmio_counters        mmio_counters;
 155         volatile unsigned               gpu_load_stop_thread; /* bool */
 156
 157         /* Performance counters. */
 158         struct r600_perfcounters        *perfcounters;
 159
 160         /* If pipe_screen wants to recompute and re-emit the framebuffer,
 161          * sampler, and image states of all contexts, it should atomically
 162          * increment this.
 163          *
 164          * Each context will compare this with its own last known value of
 165          * the counter before drawing and re-emit the states accordingly.
 166          */
 167         unsigned                        dirty_tex_counter;
 168
 169         /* Atomically increment this counter when an existing texture's
 170          * metadata is enabled or disabled in a way that requires changing
 171          * contexts' compressed texture binding masks.
 172          */
 173         unsigned                        compressed_colortex_counter;
 174
 175         struct {
 176                 /* Context flags to set so that all writes from earlier jobs
 177                  * in the CP are seen by L2 clients.
 178                  */
 179                 unsigned cp_to_L2;
 180
 181                 /* Context flags to set so that all writes from earlier jobs
 182                  * that end in L2 are seen by CP.
 183                  */
 184                 unsigned L2_to_cp;
 185         } barrier_flags;
 186
 187         mtx_t                   shader_parts_mutex;
 188         struct si_shader_part           *vs_prologs;
 189         struct si_shader_part           *tcs_epilogs;
 190         struct si_shader_part           *gs_prologs;
 191         struct si_shader_part           *ps_prologs;
 192         struct si_shader_part           *ps_epilogs;
 193
 194         /* Shader cache in memory.
 195          *
 196          * Design & limitations:
 197          * - The shader cache is per screen (= per process), never saved to
 198          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 199          * - It can only be used with one-variant-per-shader support, in which
 200          *   case only the main (typically middle) part of shaders is cached.
 201          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 202          *   variants of VS and TES are cached, so LS and ES aren't.
 203          * - GS and CS aren't cached, but it's certainly possible to cache
 204          *   those as well.
 205          */
 206         mtx_t                   shader_cache_mutex;
 207         struct hash_table               *shader_cache;
 208
 209         /* Shader compiler queue for multithreaded compilation. */
 210         struct util_queue               shader_compiler_queue;
 211         /* Use at most 3 normal compiler threads on quadcore and better.
 212          * Hyperthreaded CPUs report the number of threads, but we want
 213          * the number of cores. */
 214         LLVMTargetMachineRef            tm[3]; /* used by the queue only */
 215
 216         struct util_queue               shader_compiler_queue_low_priority;
 217         /* Use at most 2 low priority threads on quadcore and better.
 218          * We want to minimize the impact on multithreaded Mesa. */
 219         LLVMTargetMachineRef            tm_low_priority[2]; /* at most 2 threads */
 220 };
 221
 222 struct si_blend_color {
 223         struct r600_atom                atom;
 224         struct pipe_blend_color         state;
 225         bool                            any_nonzeros;
 226 };
 227
 228 struct si_sampler_view {
 229         struct pipe_sampler_view        base;
 230         /* [0..7] = image descriptor
 231          * [4..7] = buffer descriptor */
 232         uint32_t                        state[8];
 233         uint32_t                        fmask_state[8];
 234         const struct legacy_surf_level  *base_level_info;
 235         ubyte                           base_level;
 236         ubyte                           block_width;
 237         bool is_stencil_sampler;
 238         bool is_integer;
 239         bool dcc_incompatible;
 240 };
 241
 242 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
 243
 244 struct si_sampler_state {
 245 #ifdef DEBUG
 246         unsigned                        magic;
 247 #endif
 248         uint32_t                        val[4];
 249         uint32_t                        integer_val[4];
 250         uint32_t                        upgraded_depth_val[4];
 251 };
 252
 253 struct si_cs_shader_state {
 254         struct si_compute               *program;
 255         struct si_compute               *emitted_program;
 256         unsigned                        offset;
 257         bool                            initialized;
 258         bool                            uses_scratch;
 259 };
 260
 261 struct si_samplers {
 262         struct pipe_sampler_view        *views[SI_NUM_SAMPLERS];
 263         struct si_sampler_state         *sampler_states[SI_NUM_SAMPLERS];
 264
 265         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 266         unsigned                        enabled_mask;
 267         uint32_t                        needs_depth_decompress_mask;
 268         uint32_t                        needs_color_decompress_mask;
 269 };
 270
 271 struct si_images {
 272         struct pipe_image_view          views[SI_NUM_IMAGES];
 273         uint32_t                        needs_color_decompress_mask;
 274         unsigned                        enabled_mask;
 275 };
 276
 277 struct si_framebuffer {
 278         struct r600_atom                atom;
 279         struct pipe_framebuffer_state   state;
 280         unsigned                        colorbuf_enabled_4bit;
 281         unsigned                        spi_shader_col_format;
 282         unsigned                        spi_shader_col_format_alpha;
 283         unsigned                        spi_shader_col_format_blend;
 284         unsigned                        spi_shader_col_format_blend_alpha;
 285         ubyte                           nr_samples:5; /* at most 16xAA */
 286         ubyte                           log_samples:3; /* at most 4 = 16xAA */
 287         ubyte                           compressed_cb_mask;
 288         ubyte                           color_is_int8;
 289         ubyte                           color_is_int10;
 290         ubyte                           dirty_cbufs;
 291         bool                            dirty_zsbuf;
 292         bool                            any_dst_linear;
 293         bool                            CB_has_shader_readable_metadata;
 294         bool                            DB_has_shader_readable_metadata;
 295 };
 296
 297 struct si_signed_scissor {
 298         int minx;
 299         int miny;
 300         int maxx;
 301         int maxy;
 302 };
 303
 304 struct si_scissors {
 305         struct r600_atom                atom;
 306         unsigned                        dirty_mask;
 307         struct pipe_scissor_state       states[SI_MAX_VIEWPORTS];
 308 };
 309
 310 struct si_viewports {
 311         struct r600_atom                atom;
 312         unsigned                        dirty_mask;
 313         unsigned                        depth_range_dirty_mask;
 314         struct pipe_viewport_state      states[SI_MAX_VIEWPORTS];
 315         struct si_signed_scissor        as_scissor[SI_MAX_VIEWPORTS];
 316 };
 317
 318 struct si_clip_state {
 319         struct r600_atom                atom;
 320         struct pipe_clip_state          state;
 321         bool                            any_nonzeros;
 322 };
 323
 324 struct si_sample_locs {
 325         struct r600_atom        atom;
 326         unsigned                nr_samples;
 327 };
 328
 329 struct si_sample_mask {
 330         struct r600_atom        atom;
 331         uint16_t                sample_mask;
 332 };
 333
 334 struct si_streamout_target {
 335         struct pipe_stream_output_target b;
 336
 337         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 338         struct r600_resource    *buf_filled_size;
 339         unsigned                buf_filled_size_offset;
 340         bool                    buf_filled_size_valid;
 341
 342         unsigned                stride_in_dw;
 343 };
 344
 345 struct si_streamout {
 346         struct r600_atom                begin_atom;
 347         bool                            begin_emitted;
 348
 349         unsigned                        enabled_mask;
 350         unsigned                        num_targets;
 351         struct si_streamout_target      *targets[PIPE_MAX_SO_BUFFERS];
 352
 353         unsigned                        append_bitmask;
 354         bool                            suspended;
 355
 356         /* External state which comes from the vertex shader,
 357          * it must be set explicitly when binding a shader. */
 358         uint16_t                        *stride_in_dw;
 359         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 360
 361         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 362         unsigned                        hw_enabled_mask;
 363
 364         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 365         struct r600_atom                enable_atom;
 366         bool                            streamout_enabled;
 367         bool                            prims_gen_query_enabled;
 368         int                             num_prims_gen_queries;
 369 };
 370
 371 /* A shader state consists of the shader selector, which is a constant state
 372  * object shared by multiple contexts and shouldn't be modified, and
 373  * the current shader variant selected for this context.
 374  */
 375 struct si_shader_ctx_state {
 376         struct si_shader_selector       *cso;
 377         struct si_shader                *current;
 378 };
 379
 380 #define SI_NUM_VGT_PARAM_KEY_BITS 12
 381 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
 382
 383 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
 384  * Some fields are set by state-change calls, most are set by draw_vbo.
 385  */
 386 union si_vgt_param_key {
 387         struct {
 388                 unsigned prim:4;
 389                 unsigned uses_instancing:1;
 390                 unsigned multi_instances_smaller_than_primgroup:1;
 391                 unsigned primitive_restart:1;
 392                 unsigned count_from_stream_output:1;
 393                 unsigned line_stipple_enabled:1;
 394                 unsigned uses_tess:1;
 395                 unsigned tess_uses_prim_id:1;
 396                 unsigned uses_gs:1;
 397                 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
 398         } u;
 399         uint32_t index;
 400 };
 401
 402 struct si_texture_handle
 403 {
 404         unsigned                        desc_slot;
 405         bool                            desc_dirty;
 406         struct pipe_sampler_view        *view;
 407         struct si_sampler_state         sstate;
 408 };
 409
 410 struct si_image_handle
 411 {
 412         unsigned                        desc_slot;
 413         bool                            desc_dirty;
 414         struct pipe_image_view          view;
 415 };
 416
 417 struct si_saved_cs {
 418         struct pipe_reference   reference;
 419         struct si_context       *ctx;
 420         struct radeon_saved_cs  gfx;
 421         struct r600_resource    *trace_buf;
 422         unsigned                trace_id;
 423
 424         unsigned                gfx_last_dw;
 425         bool                    flushed;
 426         int64_t                 time_flush;
 427 };
 428
 429 struct si_context {
 430         struct r600_common_context      b;
 431         struct blitter_context          *blitter;
 432         void                            *custom_dsa_flush;
 433         void                            *custom_blend_resolve;
 434         void                            *custom_blend_fmask_decompress;
 435         void                            *custom_blend_eliminate_fastclear;
 436         void                            *custom_blend_dcc_decompress;
 437         void                            *vs_blit_pos;
 438         void                            *vs_blit_pos_layered;
 439         void                            *vs_blit_color;
 440         void                            *vs_blit_color_layered;
 441         void                            *vs_blit_texcoord;
 442         struct si_screen                *screen;
 443         struct pipe_debug_callback      debug;
 444         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 445         struct si_shader_ctx_state      fixed_func_tcs_shader;
 446         struct r600_resource            *wait_mem_scratch;
 447         unsigned                        wait_mem_number;
 448         uint16_t                        prefetch_L2_mask;
 449
 450         bool                            gfx_flush_in_progress:1;
 451         bool                            compute_is_busy:1;
 452
 453         /* Atoms (direct states). */
 454         union si_state_atoms            atoms;
 455         unsigned                        dirty_atoms; /* mask */
 456         /* PM4 states (precomputed immutable states) */
 457         unsigned                        dirty_states;
 458         union si_state                  queued;
 459         union si_state                  emitted;
 460
 461         /* Atom declarations. */
 462         struct si_framebuffer           framebuffer;
 463         struct si_sample_locs           msaa_sample_locs;
 464         struct r600_atom                db_render_state;
 465         struct r600_atom                dpbb_state;
 466         struct r600_atom                msaa_config;
 467         struct si_sample_mask           sample_mask;
 468         struct r600_atom                cb_render_state;
 469         unsigned                        last_cb_target_mask;
 470         struct si_blend_color           blend_color;
 471         struct r600_atom                clip_regs;
 472         struct si_clip_state            clip_state;
 473         struct si_shader_data           shader_pointers;
 474         struct si_stencil_ref           stencil_ref;
 475         struct r600_atom                spi_map;
 476         struct si_scissors              scissors;
 477         struct si_streamout             streamout;
 478         struct si_viewports             viewports;
 479
 480         /* Precomputed states. */
 481         struct si_pm4_state             *init_config;
 482         struct si_pm4_state             *init_config_gs_rings;
 483         bool                            init_config_has_vgt_flush;
 484         struct si_pm4_state             *vgt_shader_config[4];
 485
 486         /* shaders */
 487         struct si_shader_ctx_state      ps_shader;
 488         struct si_shader_ctx_state      gs_shader;
 489         struct si_shader_ctx_state      vs_shader;
 490         struct si_shader_ctx_state      tcs_shader;
 491         struct si_shader_ctx_state      tes_shader;
 492         struct si_cs_shader_state       cs_shader_state;
 493
 494         /* shader information */
 495         struct si_vertex_elements       *vertex_elements;
 496         unsigned                        sprite_coord_enable;
 497         bool                            flatshade;
 498         bool                            do_update_shaders;
 499
 500         /* shader descriptors */
 501         struct si_descriptors           vertex_buffers;
 502         struct si_descriptors           descriptors[SI_NUM_DESCS];
 503         unsigned                        descriptors_dirty;
 504         unsigned                        shader_pointers_dirty;
 505         unsigned                        shader_needs_decompress_mask;
 506         struct si_buffer_resources      rw_buffers;
 507         struct si_buffer_resources      const_and_shader_buffers[SI_NUM_SHADERS];
 508         struct si_samplers              samplers[SI_NUM_SHADERS];
 509         struct si_images                images[SI_NUM_SHADERS];
 510
 511         /* other shader resources */
 512         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 513         struct pipe_resource            *esgs_ring;
 514         struct pipe_resource            *gsvs_ring;
 515         struct pipe_resource            *tf_ring;
 516         struct pipe_resource            *tess_offchip_ring;
 517         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 518         struct r600_resource            *border_color_buffer;
 519         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 520         unsigned                        border_color_count;
 521         unsigned                        num_vs_blit_sgprs;
 522         uint32_t                        vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
 523
 524         /* Vertex and index buffers. */
 525         bool                            vertex_buffers_dirty;
 526         bool                            vertex_buffer_pointer_dirty;
 527         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 528
 529         /* MSAA config state. */
 530         int                             ps_iter_samples;
 531         bool                            smoothing_enabled;
 532
 533         /* DB render state. */
 534         unsigned                ps_db_shader_control;
 535         unsigned                dbcb_copy_sample;
 536         bool                    dbcb_depth_copy_enabled:1;
 537         bool                    dbcb_stencil_copy_enabled:1;
 538         bool                    db_flush_depth_inplace:1;
 539         bool                    db_flush_stencil_inplace:1;
 540         bool                    db_depth_clear:1;
 541         bool                    db_depth_disable_expclear:1;
 542         bool                    db_stencil_clear:1;
 543         bool                    db_stencil_disable_expclear:1;
 544         bool                    occlusion_queries_disabled:1;
 545         bool                    generate_mipmap_for_depth:1;
 546
 547         /* Emitted draw state. */
 548         bool                    gs_tri_strip_adj_fix:1;
 549         bool                    ls_vgpr_fix:1;
 550         int                     last_index_size;
 551         int                     last_base_vertex;
 552         int                     last_start_instance;
 553         int                     last_drawid;
 554         int                     last_sh_base_reg;
 555         int                     last_primitive_restart_en;
 556         int                     last_restart_index;
 557         int                     last_gs_out_prim;
 558         int                     last_prim;
 559         int                     last_multi_vgt_param;
 560         int                     last_rast_prim;
 561         unsigned                last_sc_line_stipple;
 562         unsigned                current_vs_state;
 563         unsigned                last_vs_state;
 564         enum pipe_prim_type     current_rast_prim; /* primitive type after TES, GS */
 565
 566         /* Scratch buffer */
 567         struct r600_atom        scratch_state;
 568         struct r600_resource    *scratch_buffer;
 569         unsigned                scratch_waves;
 570         unsigned                spi_tmpring_size;
 571
 572         struct r600_resource    *compute_scratch_buffer;
 573
 574         /* Emitted derived tessellation state. */
 575         /* Local shader (VS), or HS if LS-HS are merged. */
 576         struct si_shader        *last_ls;
 577         struct si_shader_selector *last_tcs;
 578         int                     last_num_tcs_input_cp;
 579         int                     last_tes_sh_base;
 580         bool                    last_tess_uses_primid;
 581         unsigned                last_num_patches;
 582
 583         /* Debug state. */
 584         bool                    is_debug;
 585         struct si_saved_cs      *current_saved_cs;
 586         uint64_t                dmesg_timestamp;
 587         unsigned                apitrace_call_number;
 588
 589         /* Other state */
 590         bool need_check_render_feedback;
 591         bool                    decompression_enabled;
 592
 593         bool                    vs_writes_viewport_index;
 594         bool                    vs_disables_clipping_viewport;
 595
 596         /* Precomputed IA_MULTI_VGT_PARAM */
 597         union si_vgt_param_key  ia_multi_vgt_param_key;
 598         unsigned                ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
 599
 600         /* Bindless descriptors. */
 601         struct si_descriptors   bindless_descriptors;
 602         struct util_idalloc     bindless_used_slots;
 603         unsigned                num_bindless_descriptors;
 604         bool                    bindless_descriptors_dirty;
 605         bool                    graphics_bindless_pointer_dirty;
 606         bool                    compute_bindless_pointer_dirty;
 607
 608         /* Allocated bindless handles */
 609         struct hash_table       *tex_handles;
 610         struct hash_table       *img_handles;
 611
 612         /* Resident bindless handles */
 613         struct util_dynarray    resident_tex_handles;
 614         struct util_dynarray    resident_img_handles;
 615
 616         /* Resident bindless handles which need decompression */
 617         struct util_dynarray    resident_tex_needs_color_decompress;
 618         struct util_dynarray    resident_img_needs_color_decompress;
 619         struct util_dynarray    resident_tex_needs_depth_decompress;
 620
 621         /* Bindless state */
 622         bool                    uses_bindless_samplers;
 623         bool                    uses_bindless_images;
 624
 625         /* MSAA sample locations.
 626          * The first index is the sample index.
 627          * The second index is the coordinate: X, Y. */
 628         float                   sample_locations_1x[1][2];
 629         float                   sample_locations_2x[2][2];
 630         float                   sample_locations_4x[4][2];
 631         float                   sample_locations_8x[8][2];
 632         float                   sample_locations_16x[16][2];
 633 };
 634
 635 /* cik_sdma.c */
 636 void cik_init_sdma_functions(struct si_context *sctx);
 637
 638 /* si_blit.c */
 639 enum si_blitter_op /* bitmask */
 640 {
 641         SI_SAVE_TEXTURES      = 1,
 642         SI_SAVE_FRAMEBUFFER   = 2,
 643         SI_SAVE_FRAGMENT_STATE = 4,
 644         SI_DISABLE_RENDER_COND = 8,
 645 };
 646
 647 void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op);
 648 void si_blitter_end(struct pipe_context *ctx);
 649 void si_init_blit_functions(struct si_context *sctx);
 650 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
 651 void si_resource_copy_region(struct pipe_context *ctx,
 652                              struct pipe_resource *dst,
 653                              unsigned dst_level,
 654                              unsigned dstx, unsigned dsty, unsigned dstz,
 655                              struct pipe_resource *src,
 656                              unsigned src_level,
 657                              const struct pipe_box *src_box);
 658
 659 /* si_clear.c */
 660 void vi_dcc_clear_level(struct si_context *sctx,
 661                         struct r600_texture *rtex,
 662                         unsigned level, unsigned clear_value);
 663 void si_init_clear_functions(struct si_context *sctx);
 664
 665 /* si_cp_dma.c */
 666 #define SI_CPDMA_SKIP_CHECK_CS_SPACE    (1 << 0) /* don't call need_cs_space */
 667 #define SI_CPDMA_SKIP_SYNC_AFTER        (1 << 1) /* don't wait for DMA after the copy */
 668 #define SI_CPDMA_SKIP_SYNC_BEFORE       (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
 669 #define SI_CPDMA_SKIP_GFX_SYNC          (1 << 3) /* don't flush caches and don't wait for PS/CS */
 670 #define SI_CPDMA_SKIP_BO_LIST_UPDATE    (1 << 4) /* don't update the BO list */
 671 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
 672                            SI_CPDMA_SKIP_SYNC_AFTER | \
 673                            SI_CPDMA_SKIP_SYNC_BEFORE | \
 674                            SI_CPDMA_SKIP_GFX_SYNC | \
 675                            SI_CPDMA_SKIP_BO_LIST_UPDATE)
 676
 677 enum r600_coherency {
 678         R600_COHERENCY_NONE, /* no cache flushes needed */
 679         R600_COHERENCY_SHADER,
 680         R600_COHERENCY_CB_META,
 681 };
 682
 683 void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
 684                      uint64_t offset, uint64_t size, unsigned value,
 685                      enum r600_coherency coher);
 686 void si_copy_buffer(struct si_context *sctx,
 687                     struct pipe_resource *dst, struct pipe_resource *src,
 688                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 689                     unsigned user_flags);
 690 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 691                               uint64_t offset, unsigned size);
 692 void cik_emit_prefetch_L2(struct si_context *sctx);
 693 void si_init_cp_dma_functions(struct si_context *sctx);
 694
 695 /* si_debug.c */
 696 void si_auto_log_cs(void *data, struct u_log_context *log);
 697 void si_log_hw_flush(struct si_context *sctx);
 698 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
 699 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
 700 void si_init_debug_functions(struct si_context *sctx);
 701 void si_check_vm_faults(struct r600_common_context *ctx,
 702                         struct radeon_saved_cs *saved, enum ring_type ring);
 703 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
 704
 705 /* si_dma.c */
 706 void si_init_dma_functions(struct si_context *sctx);
 707
 708 /* si_fence.c */
 709 void si_init_fence_functions(struct si_context *ctx);
 710 void si_init_screen_fence_functions(struct si_screen *screen);
 711 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
 712                                           struct tc_unflushed_batch_token *tc_token);
 713
 714 /* si_get.c */
 715 const char *si_get_family_name(const struct si_screen *sscreen);
 716 void si_init_screen_get_functions(struct si_screen *sscreen);
 717
 718 /* si_hw_context.c */
 719 void si_destroy_saved_cs(struct si_saved_cs *scs);
 720 void si_context_gfx_flush(void *context, unsigned flags,
 721                           struct pipe_fence_handle **fence);
 722 void si_begin_new_cs(struct si_context *ctx);
 723 void si_need_cs_space(struct si_context *ctx);
 724
 725 /* si_compute.c */
 726 void si_init_compute_functions(struct si_context *sctx);
 727
 728 /* si_perfcounters.c */
 729 void si_init_perfcounters(struct si_screen *screen);
 730
 731 /* si_test_dma.c */
 732 void si_test_dma(struct si_screen *sscreen);
 733
 734 /* si_uvd.c */
 735 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 736                                                const struct pipe_video_codec *templ);
 737
 738 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 739                                                  const struct pipe_video_buffer *tmpl);
 740
 741 /* si_viewport.c */
 742 void si_update_vs_viewport_state(struct si_context *ctx);
 743 void si_init_viewport_functions(struct si_context *ctx);
 744
 745
 746 /*
 747  * common helpers
 748  */
 749
 750 static inline void
 751 si_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 752 {
 753         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 754         struct r600_resource *res = (struct r600_resource *)r;
 755
 756         if (res) {
 757                 /* Add memory usage for need_gfx_cs_space */
 758                 rctx->vram += res->vram_usage;
 759                 rctx->gtt += res->gart_usage;
 760         }
 761 }
 762
 763 static inline void
 764 si_invalidate_draw_sh_constants(struct si_context *sctx)
 765 {
 766         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 767 }
 768
 769 static inline void
 770 si_set_atom_dirty(struct si_context *sctx,
 771                   struct r600_atom *atom, bool dirty)
 772 {
 773         unsigned bit = 1 << atom->id;
 774
 775         if (dirty)
 776                 sctx->dirty_atoms |= bit;
 777         else
 778                 sctx->dirty_atoms &= ~bit;
 779 }
 780
 781 static inline bool
 782 si_is_atom_dirty(struct si_context *sctx,
 783                   struct r600_atom *atom)
 784 {
 785         unsigned bit = 1 << atom->id;
 786
 787         return sctx->dirty_atoms & bit;
 788 }
 789
 790 static inline void
 791 si_mark_atom_dirty(struct si_context *sctx,
 792                    struct r600_atom *atom)
 793 {
 794         si_set_atom_dirty(sctx, atom, true);
 795 }
 796
 797 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
 798 {
 799         if (sctx->gs_shader.cso)
 800                 return &sctx->gs_shader;
 801         if (sctx->tes_shader.cso)
 802                 return &sctx->tes_shader;
 803
 804         return &sctx->vs_shader;
 805 }
 806
 807 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 808 {
 809         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 810
 811         return vs->cso ? &vs->cso->info : NULL;
 812 }
 813
 814 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 815 {
 816         if (sctx->gs_shader.cso)
 817                 return sctx->gs_shader.cso->gs_copy_shader;
 818
 819         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 820         return vs->current ? vs->current : NULL;
 821 }
 822
 823 static inline bool si_can_dump_shader(struct si_screen *sscreen,
 824                                       unsigned processor)
 825 {
 826         return sscreen->debug_flags & (1 << processor);
 827 }
 828
 829 static inline bool si_extra_shader_checks(struct si_screen *sscreen,
 830                                           unsigned processor)
 831 {
 832         return (sscreen->debug_flags & DBG(CHECK_IR)) ||
 833                si_can_dump_shader(sscreen, processor);
 834 }
 835
 836 static inline bool si_get_strmout_en(struct si_context *sctx)
 837 {
 838         return sctx->streamout.streamout_enabled ||
 839                sctx->streamout.prims_gen_query_enabled;
 840 }
 841
 842 static inline unsigned
 843 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
 844 {
 845         unsigned alignment, tcc_cache_line_size;
 846
 847         /* If the upload size is less than the cache line size (e.g. 16, 32),
 848          * the whole thing will fit into a cache line if we align it to its size.
 849          * The idea is that multiple small uploads can share a cache line.
 850          * If the upload size is greater, align it to the cache line size.
 851          */
 852         alignment = util_next_power_of_two(upload_size);
 853         tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
 854         return MIN2(alignment, tcc_cache_line_size);
 855 }
 856
 857 static inline void
 858 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
 859 {
 860         if (pipe_reference(&(*dst)->reference, &src->reference))
 861                 si_destroy_saved_cs(*dst);
 862
 863         *dst = src;
 864 }
 865
 866 static inline void
 867 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 868                            bool shaders_read_metadata)
 869 {
 870         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
 871                          SI_CONTEXT_INV_VMEM_L1;
 872
 873         if (sctx->b.chip_class >= GFX9) {
 874                 /* Single-sample color is coherent with shaders on GFX9, but
 875                  * L2 metadata must be flushed if shaders read metadata.
 876                  * (DCC, CMASK).
 877                  */
 878                 if (num_samples >= 2)
 879                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 880                 else if (shaders_read_metadata)
 881                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 882         } else {
 883                 /* SI-CI-VI */
 884                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 885         }
 886 }
 887
 888 static inline void
 889 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 890                            bool include_stencil, bool shaders_read_metadata)
 891 {
 892         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
 893                          SI_CONTEXT_INV_VMEM_L1;
 894
 895         if (sctx->b.chip_class >= GFX9) {
 896                 /* Single-sample depth (not stencil) is coherent with shaders
 897                  * on GFX9, but L2 metadata must be flushed if shaders read
 898                  * metadata.
 899                  */
 900                 if (num_samples >= 2 || include_stencil)
 901                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 902                 else if (shaders_read_metadata)
 903                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 904         } else {
 905                 /* SI-CI-VI */
 906                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 907         }
 908 }
 909
 910 static inline bool
 911 si_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
 912 {
 913         return (stencil_sampler && tex->can_sample_s) ||
 914                (!stencil_sampler && tex->can_sample_z);
 915 }
 916
 917 static inline bool
 918 si_htile_enabled(struct r600_texture *tex, unsigned level)
 919 {
 920         return tex->htile_offset && level == 0;
 921 }
 922
 923 static inline bool
 924 vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level)
 925 {
 926         assert(!tex->tc_compatible_htile || tex->htile_offset);
 927         return tex->tc_compatible_htile && level == 0;
 928 }
 929
 930 #endif