2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "si_shader.h"
28 #include "util/u_dynarray.h"
29 #include "util/u_idalloc.h"
31 #ifdef PIPE_ARCH_BIG_ENDIAN
32 #define SI_BIG_ENDIAN 1
34 #define SI_BIG_ENDIAN 0
37 #define ATI_VENDOR_ID 0x1002
39 #define SI_NOT_QUERY 0xffffffff
41 /* The base vertex and primitive restart can be any number, but we must pick
42 * one which will mean "unknown" for the purpose of state tracking and
43 * the number shouldn't be a commonly-used one. */
44 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
45 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
46 #define SI_NUM_SMOOTH_AA_SAMPLES 8
47 #define SI_GS_PER_ES 128
48 /* Alignment for optimal CP DMA performance. */
49 #define SI_CPDMA_ALIGNMENT 32
51 /* Pipeline & streamout query controls. */
52 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
53 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
54 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
55 /* Instruction cache. */
56 #define SI_CONTEXT_INV_ICACHE (1 << 3)
57 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
58 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
59 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
60 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
61 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
62 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
63 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
64 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
65 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
66 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
67 * a CB or DB flush. */
68 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
69 /* Framebuffer caches. */
70 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
71 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
72 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
73 /* Engine synchronization. */
74 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
75 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
76 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
77 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
78 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
80 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
81 #define SI_PREFETCH_LS (1 << 1)
82 #define SI_PREFETCH_HS (1 << 2)
83 #define SI_PREFETCH_ES (1 << 3)
84 #define SI_PREFETCH_GS (1 << 4)
85 #define SI_PREFETCH_VS (1 << 5)
86 #define SI_PREFETCH_PS (1 << 6)
88 #define SI_MAX_BORDER_COLORS 4096
89 #define SI_MAX_VIEWPORTS 16
94 struct u_suballocator
;
98 struct radeon_winsys
*ws
;
99 struct disk_cache
*disk_shader_cache
;
101 struct radeon_info info
;
102 uint64_t debug_flags
;
103 char renderer_string
[100];
105 unsigned gs_table_depth
;
106 unsigned tess_offchip_block_dw_size
;
107 unsigned tess_offchip_ring_size
;
108 unsigned tess_factor_ring_size
;
109 unsigned vgt_hs_offchip_param
;
110 bool has_clear_state
;
111 bool has_distributed_tess
;
112 bool has_draw_indirect_multi
;
113 bool has_out_of_order_rast
;
114 bool assume_no_z_fights
;
115 bool commutative_blend_add
;
116 bool clear_db_cache_before_clear
;
117 bool has_msaa_sample_loc_bug
;
118 bool has_ls_vgpr_init_bug
;
121 bool llvm_has_working_vgpr_indexing
;
123 /* Whether shaders are monolithic (1-part) or separate (3-part). */
124 bool use_monolithic_shaders
;
126 bool has_rbplus
; /* if RB+ registers exist */
127 bool rbplus_allowed
; /* if RB+ is allowed */
128 bool dcc_msaa_allowed
;
129 bool cpdma_prefetch_writes_memory
;
131 struct slab_parent_pool pool_transfers
;
133 /* Texture filter settings. */
134 int force_aniso
; /* -1 = disabled */
136 /* Auxiliary context. Mainly used to initialize resources.
137 * It must be locked prior to using and flushed before unlocking. */
138 struct pipe_context
*aux_context
;
139 mtx_t aux_context_lock
;
141 /* This must be in the screen, because UE4 uses one context for
142 * compilation and another one for rendering.
144 unsigned num_compilations
;
145 /* Along with ST_DEBUG=precompile, this should show if applications
146 * are loading shaders on demand. This is a monotonic counter.
148 unsigned num_shaders_created
;
149 unsigned num_shader_cache_hits
;
151 /* GPU load thread. */
152 mtx_t gpu_load_mutex
;
153 thrd_t gpu_load_thread
;
154 union r600_mmio_counters mmio_counters
;
155 volatile unsigned gpu_load_stop_thread
; /* bool */
157 /* Performance counters. */
158 struct r600_perfcounters
*perfcounters
;
160 /* If pipe_screen wants to recompute and re-emit the framebuffer,
161 * sampler, and image states of all contexts, it should atomically
164 * Each context will compare this with its own last known value of
165 * the counter before drawing and re-emit the states accordingly.
167 unsigned dirty_tex_counter
;
169 /* Atomically increment this counter when an existing texture's
170 * metadata is enabled or disabled in a way that requires changing
171 * contexts' compressed texture binding masks.
173 unsigned compressed_colortex_counter
;
176 /* Context flags to set so that all writes from earlier jobs
177 * in the CP are seen by L2 clients.
181 /* Context flags to set so that all writes from earlier jobs
182 * that end in L2 are seen by CP.
187 mtx_t shader_parts_mutex
;
188 struct si_shader_part
*vs_prologs
;
189 struct si_shader_part
*tcs_epilogs
;
190 struct si_shader_part
*gs_prologs
;
191 struct si_shader_part
*ps_prologs
;
192 struct si_shader_part
*ps_epilogs
;
194 /* Shader cache in memory.
196 * Design & limitations:
197 * - The shader cache is per screen (= per process), never saved to
198 * disk, and skips redundant shader compilations from TGSI to bytecode.
199 * - It can only be used with one-variant-per-shader support, in which
200 * case only the main (typically middle) part of shaders is cached.
201 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
202 * variants of VS and TES are cached, so LS and ES aren't.
203 * - GS and CS aren't cached, but it's certainly possible to cache
206 mtx_t shader_cache_mutex
;
207 struct hash_table
*shader_cache
;
209 /* Shader compiler queue for multithreaded compilation. */
210 struct util_queue shader_compiler_queue
;
211 /* Use at most 3 normal compiler threads on quadcore and better.
212 * Hyperthreaded CPUs report the number of threads, but we want
213 * the number of cores. */
214 LLVMTargetMachineRef tm
[3]; /* used by the queue only */
216 struct util_queue shader_compiler_queue_low_priority
;
217 /* Use at most 2 low priority threads on quadcore and better.
218 * We want to minimize the impact on multithreaded Mesa. */
219 LLVMTargetMachineRef tm_low_priority
[2]; /* at most 2 threads */
222 struct si_blend_color
{
223 struct r600_atom atom
;
224 struct pipe_blend_color state
;
228 struct si_sampler_view
{
229 struct pipe_sampler_view base
;
230 /* [0..7] = image descriptor
231 * [4..7] = buffer descriptor */
233 uint32_t fmask_state
[8];
234 const struct legacy_surf_level
*base_level_info
;
237 bool is_stencil_sampler
;
239 bool dcc_incompatible
;
242 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
244 struct si_sampler_state
{
249 uint32_t integer_val
[4];
250 uint32_t upgraded_depth_val
[4];
253 struct si_cs_shader_state
{
254 struct si_compute
*program
;
255 struct si_compute
*emitted_program
;
262 struct pipe_sampler_view
*views
[SI_NUM_SAMPLERS
];
263 struct si_sampler_state
*sampler_states
[SI_NUM_SAMPLERS
];
265 /* The i-th bit is set if that element is enabled (non-NULL resource). */
266 unsigned enabled_mask
;
267 uint32_t needs_depth_decompress_mask
;
268 uint32_t needs_color_decompress_mask
;
272 struct pipe_image_view views
[SI_NUM_IMAGES
];
273 uint32_t needs_color_decompress_mask
;
274 unsigned enabled_mask
;
277 struct si_framebuffer
{
278 struct r600_atom atom
;
279 struct pipe_framebuffer_state state
;
280 unsigned colorbuf_enabled_4bit
;
281 unsigned spi_shader_col_format
;
282 unsigned spi_shader_col_format_alpha
;
283 unsigned spi_shader_col_format_blend
;
284 unsigned spi_shader_col_format_blend_alpha
;
285 ubyte nr_samples
:5; /* at most 16xAA */
286 ubyte log_samples
:3; /* at most 4 = 16xAA */
287 ubyte compressed_cb_mask
;
289 ubyte color_is_int10
;
293 bool CB_has_shader_readable_metadata
;
294 bool DB_has_shader_readable_metadata
;
297 struct si_signed_scissor
{
305 struct r600_atom atom
;
307 struct pipe_scissor_state states
[SI_MAX_VIEWPORTS
];
310 struct si_viewports
{
311 struct r600_atom atom
;
313 unsigned depth_range_dirty_mask
;
314 struct pipe_viewport_state states
[SI_MAX_VIEWPORTS
];
315 struct si_signed_scissor as_scissor
[SI_MAX_VIEWPORTS
];
318 struct si_clip_state
{
319 struct r600_atom atom
;
320 struct pipe_clip_state state
;
324 struct si_sample_locs
{
325 struct r600_atom atom
;
329 struct si_sample_mask
{
330 struct r600_atom atom
;
331 uint16_t sample_mask
;
334 struct si_streamout_target
{
335 struct pipe_stream_output_target b
;
337 /* The buffer where BUFFER_FILLED_SIZE is stored. */
338 struct r600_resource
*buf_filled_size
;
339 unsigned buf_filled_size_offset
;
340 bool buf_filled_size_valid
;
342 unsigned stride_in_dw
;
345 struct si_streamout
{
346 struct r600_atom begin_atom
;
349 unsigned enabled_mask
;
350 unsigned num_targets
;
351 struct si_streamout_target
*targets
[PIPE_MAX_SO_BUFFERS
];
353 unsigned append_bitmask
;
356 /* External state which comes from the vertex shader,
357 * it must be set explicitly when binding a shader. */
358 uint16_t *stride_in_dw
;
359 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
361 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
362 unsigned hw_enabled_mask
;
364 /* The state of VGT_STRMOUT_(CONFIG|EN). */
365 struct r600_atom enable_atom
;
366 bool streamout_enabled
;
367 bool prims_gen_query_enabled
;
368 int num_prims_gen_queries
;
371 /* A shader state consists of the shader selector, which is a constant state
372 * object shared by multiple contexts and shouldn't be modified, and
373 * the current shader variant selected for this context.
375 struct si_shader_ctx_state
{
376 struct si_shader_selector
*cso
;
377 struct si_shader
*current
;
380 #define SI_NUM_VGT_PARAM_KEY_BITS 12
381 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
383 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
384 * Some fields are set by state-change calls, most are set by draw_vbo.
386 union si_vgt_param_key
{
389 unsigned uses_instancing
:1;
390 unsigned multi_instances_smaller_than_primgroup
:1;
391 unsigned primitive_restart
:1;
392 unsigned count_from_stream_output
:1;
393 unsigned line_stipple_enabled
:1;
394 unsigned uses_tess
:1;
395 unsigned tess_uses_prim_id
:1;
397 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
402 struct si_texture_handle
406 struct pipe_sampler_view
*view
;
407 struct si_sampler_state sstate
;
410 struct si_image_handle
414 struct pipe_image_view view
;
418 struct pipe_reference reference
;
419 struct si_context
*ctx
;
420 struct radeon_saved_cs gfx
;
421 struct r600_resource
*trace_buf
;
424 unsigned gfx_last_dw
;
430 struct r600_common_context b
;
431 struct blitter_context
*blitter
;
432 void *custom_dsa_flush
;
433 void *custom_blend_resolve
;
434 void *custom_blend_fmask_decompress
;
435 void *custom_blend_eliminate_fastclear
;
436 void *custom_blend_dcc_decompress
;
438 void *vs_blit_pos_layered
;
440 void *vs_blit_color_layered
;
441 void *vs_blit_texcoord
;
442 struct si_screen
*screen
;
443 struct pipe_debug_callback debug
;
444 LLVMTargetMachineRef tm
; /* only non-threaded compilation */
445 struct si_shader_ctx_state fixed_func_tcs_shader
;
446 struct r600_resource
*wait_mem_scratch
;
447 unsigned wait_mem_number
;
448 uint16_t prefetch_L2_mask
;
450 bool gfx_flush_in_progress
:1;
451 bool compute_is_busy
:1;
453 /* Atoms (direct states). */
454 union si_state_atoms atoms
;
455 unsigned dirty_atoms
; /* mask */
456 /* PM4 states (precomputed immutable states) */
457 unsigned dirty_states
;
458 union si_state queued
;
459 union si_state emitted
;
461 /* Atom declarations. */
462 struct si_framebuffer framebuffer
;
463 struct si_sample_locs msaa_sample_locs
;
464 struct r600_atom db_render_state
;
465 struct r600_atom dpbb_state
;
466 struct r600_atom msaa_config
;
467 struct si_sample_mask sample_mask
;
468 struct r600_atom cb_render_state
;
469 unsigned last_cb_target_mask
;
470 struct si_blend_color blend_color
;
471 struct r600_atom clip_regs
;
472 struct si_clip_state clip_state
;
473 struct si_shader_data shader_pointers
;
474 struct si_stencil_ref stencil_ref
;
475 struct r600_atom spi_map
;
476 struct si_scissors scissors
;
477 struct si_streamout streamout
;
478 struct si_viewports viewports
;
480 /* Precomputed states. */
481 struct si_pm4_state
*init_config
;
482 struct si_pm4_state
*init_config_gs_rings
;
483 bool init_config_has_vgt_flush
;
484 struct si_pm4_state
*vgt_shader_config
[4];
487 struct si_shader_ctx_state ps_shader
;
488 struct si_shader_ctx_state gs_shader
;
489 struct si_shader_ctx_state vs_shader
;
490 struct si_shader_ctx_state tcs_shader
;
491 struct si_shader_ctx_state tes_shader
;
492 struct si_cs_shader_state cs_shader_state
;
494 /* shader information */
495 struct si_vertex_elements
*vertex_elements
;
496 unsigned sprite_coord_enable
;
498 bool do_update_shaders
;
500 /* shader descriptors */
501 struct si_descriptors vertex_buffers
;
502 struct si_descriptors descriptors
[SI_NUM_DESCS
];
503 unsigned descriptors_dirty
;
504 unsigned shader_pointers_dirty
;
505 unsigned shader_needs_decompress_mask
;
506 struct si_buffer_resources rw_buffers
;
507 struct si_buffer_resources const_and_shader_buffers
[SI_NUM_SHADERS
];
508 struct si_samplers samplers
[SI_NUM_SHADERS
];
509 struct si_images images
[SI_NUM_SHADERS
];
511 /* other shader resources */
512 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on CIK */
513 struct pipe_resource
*esgs_ring
;
514 struct pipe_resource
*gsvs_ring
;
515 struct pipe_resource
*tf_ring
;
516 struct pipe_resource
*tess_offchip_ring
;
517 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
518 struct r600_resource
*border_color_buffer
;
519 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
520 unsigned border_color_count
;
521 unsigned num_vs_blit_sgprs
;
522 uint32_t vs_blit_sh_data
[SI_VS_BLIT_SGPRS_POS_TEXCOORD
];
524 /* Vertex and index buffers. */
525 bool vertex_buffers_dirty
;
526 bool vertex_buffer_pointer_dirty
;
527 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
529 /* MSAA config state. */
531 bool smoothing_enabled
;
533 /* DB render state. */
534 unsigned ps_db_shader_control
;
535 unsigned dbcb_copy_sample
;
536 bool dbcb_depth_copy_enabled
:1;
537 bool dbcb_stencil_copy_enabled
:1;
538 bool db_flush_depth_inplace
:1;
539 bool db_flush_stencil_inplace
:1;
540 bool db_depth_clear
:1;
541 bool db_depth_disable_expclear
:1;
542 bool db_stencil_clear
:1;
543 bool db_stencil_disable_expclear
:1;
544 bool occlusion_queries_disabled
:1;
545 bool generate_mipmap_for_depth
:1;
547 /* Emitted draw state. */
548 bool gs_tri_strip_adj_fix
:1;
551 int last_base_vertex
;
552 int last_start_instance
;
554 int last_sh_base_reg
;
555 int last_primitive_restart_en
;
556 int last_restart_index
;
557 int last_gs_out_prim
;
559 int last_multi_vgt_param
;
561 unsigned last_sc_line_stipple
;
562 unsigned current_vs_state
;
563 unsigned last_vs_state
;
564 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
567 struct r600_atom scratch_state
;
568 struct r600_resource
*scratch_buffer
;
569 unsigned scratch_waves
;
570 unsigned spi_tmpring_size
;
572 struct r600_resource
*compute_scratch_buffer
;
574 /* Emitted derived tessellation state. */
575 /* Local shader (VS), or HS if LS-HS are merged. */
576 struct si_shader
*last_ls
;
577 struct si_shader_selector
*last_tcs
;
578 int last_num_tcs_input_cp
;
579 int last_tes_sh_base
;
580 bool last_tess_uses_primid
;
581 unsigned last_num_patches
;
585 struct si_saved_cs
*current_saved_cs
;
586 uint64_t dmesg_timestamp
;
587 unsigned apitrace_call_number
;
590 bool need_check_render_feedback
;
591 bool decompression_enabled
;
593 bool vs_writes_viewport_index
;
594 bool vs_disables_clipping_viewport
;
596 /* Precomputed IA_MULTI_VGT_PARAM */
597 union si_vgt_param_key ia_multi_vgt_param_key
;
598 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
600 /* Bindless descriptors. */
601 struct si_descriptors bindless_descriptors
;
602 struct util_idalloc bindless_used_slots
;
603 unsigned num_bindless_descriptors
;
604 bool bindless_descriptors_dirty
;
605 bool graphics_bindless_pointer_dirty
;
606 bool compute_bindless_pointer_dirty
;
608 /* Allocated bindless handles */
609 struct hash_table
*tex_handles
;
610 struct hash_table
*img_handles
;
612 /* Resident bindless handles */
613 struct util_dynarray resident_tex_handles
;
614 struct util_dynarray resident_img_handles
;
616 /* Resident bindless handles which need decompression */
617 struct util_dynarray resident_tex_needs_color_decompress
;
618 struct util_dynarray resident_img_needs_color_decompress
;
619 struct util_dynarray resident_tex_needs_depth_decompress
;
622 bool uses_bindless_samplers
;
623 bool uses_bindless_images
;
625 /* MSAA sample locations.
626 * The first index is the sample index.
627 * The second index is the coordinate: X, Y. */
628 float sample_locations_1x
[1][2];
629 float sample_locations_2x
[2][2];
630 float sample_locations_4x
[4][2];
631 float sample_locations_8x
[8][2];
632 float sample_locations_16x
[16][2];
636 void cik_init_sdma_functions(struct si_context
*sctx
);
639 enum si_blitter_op
/* bitmask */
641 SI_SAVE_TEXTURES
= 1,
642 SI_SAVE_FRAMEBUFFER
= 2,
643 SI_SAVE_FRAGMENT_STATE
= 4,
644 SI_DISABLE_RENDER_COND
= 8,
647 void si_blitter_begin(struct pipe_context
*ctx
, enum si_blitter_op op
);
648 void si_blitter_end(struct pipe_context
*ctx
);
649 void si_init_blit_functions(struct si_context
*sctx
);
650 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
);
651 void si_resource_copy_region(struct pipe_context
*ctx
,
652 struct pipe_resource
*dst
,
654 unsigned dstx
, unsigned dsty
, unsigned dstz
,
655 struct pipe_resource
*src
,
657 const struct pipe_box
*src_box
);
660 void vi_dcc_clear_level(struct si_context
*sctx
,
661 struct r600_texture
*rtex
,
662 unsigned level
, unsigned clear_value
);
663 void si_init_clear_functions(struct si_context
*sctx
);
666 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
667 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
668 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
669 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
670 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
671 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
672 SI_CPDMA_SKIP_SYNC_AFTER | \
673 SI_CPDMA_SKIP_SYNC_BEFORE | \
674 SI_CPDMA_SKIP_GFX_SYNC | \
675 SI_CPDMA_SKIP_BO_LIST_UPDATE)
677 enum r600_coherency
{
678 R600_COHERENCY_NONE
, /* no cache flushes needed */
679 R600_COHERENCY_SHADER
,
680 R600_COHERENCY_CB_META
,
683 void si_clear_buffer(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
684 uint64_t offset
, uint64_t size
, unsigned value
,
685 enum r600_coherency coher
);
686 void si_copy_buffer(struct si_context
*sctx
,
687 struct pipe_resource
*dst
, struct pipe_resource
*src
,
688 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
689 unsigned user_flags
);
690 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
691 uint64_t offset
, unsigned size
);
692 void cik_emit_prefetch_L2(struct si_context
*sctx
);
693 void si_init_cp_dma_functions(struct si_context
*sctx
);
696 void si_auto_log_cs(void *data
, struct u_log_context
*log
);
697 void si_log_hw_flush(struct si_context
*sctx
);
698 void si_log_draw_state(struct si_context
*sctx
, struct u_log_context
*log
);
699 void si_log_compute_state(struct si_context
*sctx
, struct u_log_context
*log
);
700 void si_init_debug_functions(struct si_context
*sctx
);
701 void si_check_vm_faults(struct r600_common_context
*ctx
,
702 struct radeon_saved_cs
*saved
, enum ring_type ring
);
703 bool si_replace_shader(unsigned num
, struct ac_shader_binary
*binary
);
706 void si_init_dma_functions(struct si_context
*sctx
);
709 void si_init_fence_functions(struct si_context
*ctx
);
710 void si_init_screen_fence_functions(struct si_screen
*screen
);
711 struct pipe_fence_handle
*si_create_fence(struct pipe_context
*ctx
,
712 struct tc_unflushed_batch_token
*tc_token
);
715 const char *si_get_family_name(const struct si_screen
*sscreen
);
716 void si_init_screen_get_functions(struct si_screen
*sscreen
);
718 /* si_hw_context.c */
719 void si_destroy_saved_cs(struct si_saved_cs
*scs
);
720 void si_context_gfx_flush(void *context
, unsigned flags
,
721 struct pipe_fence_handle
**fence
);
722 void si_begin_new_cs(struct si_context
*ctx
);
723 void si_need_cs_space(struct si_context
*ctx
);
726 void si_init_compute_functions(struct si_context
*sctx
);
728 /* si_perfcounters.c */
729 void si_init_perfcounters(struct si_screen
*screen
);
732 void si_test_dma(struct si_screen
*sscreen
);
735 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
736 const struct pipe_video_codec
*templ
);
738 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
739 const struct pipe_video_buffer
*tmpl
);
742 void si_update_vs_viewport_state(struct si_context
*ctx
);
743 void si_init_viewport_functions(struct si_context
*ctx
);
751 si_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
)
753 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
754 struct r600_resource
*res
= (struct r600_resource
*)r
;
757 /* Add memory usage for need_gfx_cs_space */
758 rctx
->vram
+= res
->vram_usage
;
759 rctx
->gtt
+= res
->gart_usage
;
764 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
766 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
770 si_set_atom_dirty(struct si_context
*sctx
,
771 struct r600_atom
*atom
, bool dirty
)
773 unsigned bit
= 1 << atom
->id
;
776 sctx
->dirty_atoms
|= bit
;
778 sctx
->dirty_atoms
&= ~bit
;
782 si_is_atom_dirty(struct si_context
*sctx
,
783 struct r600_atom
*atom
)
785 unsigned bit
= 1 << atom
->id
;
787 return sctx
->dirty_atoms
& bit
;
791 si_mark_atom_dirty(struct si_context
*sctx
,
792 struct r600_atom
*atom
)
794 si_set_atom_dirty(sctx
, atom
, true);
797 static inline struct si_shader_ctx_state
*si_get_vs(struct si_context
*sctx
)
799 if (sctx
->gs_shader
.cso
)
800 return &sctx
->gs_shader
;
801 if (sctx
->tes_shader
.cso
)
802 return &sctx
->tes_shader
;
804 return &sctx
->vs_shader
;
807 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
809 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
811 return vs
->cso
? &vs
->cso
->info
: NULL
;
814 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
816 if (sctx
->gs_shader
.cso
)
817 return sctx
->gs_shader
.cso
->gs_copy_shader
;
819 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
820 return vs
->current
? vs
->current
: NULL
;
823 static inline bool si_can_dump_shader(struct si_screen
*sscreen
,
826 return sscreen
->debug_flags
& (1 << processor
);
829 static inline bool si_extra_shader_checks(struct si_screen
*sscreen
,
832 return (sscreen
->debug_flags
& DBG(CHECK_IR
)) ||
833 si_can_dump_shader(sscreen
, processor
);
836 static inline bool si_get_strmout_en(struct si_context
*sctx
)
838 return sctx
->streamout
.streamout_enabled
||
839 sctx
->streamout
.prims_gen_query_enabled
;
842 static inline unsigned
843 si_optimal_tcc_alignment(struct si_context
*sctx
, unsigned upload_size
)
845 unsigned alignment
, tcc_cache_line_size
;
847 /* If the upload size is less than the cache line size (e.g. 16, 32),
848 * the whole thing will fit into a cache line if we align it to its size.
849 * The idea is that multiple small uploads can share a cache line.
850 * If the upload size is greater, align it to the cache line size.
852 alignment
= util_next_power_of_two(upload_size
);
853 tcc_cache_line_size
= sctx
->screen
->info
.tcc_cache_line_size
;
854 return MIN2(alignment
, tcc_cache_line_size
);
858 si_saved_cs_reference(struct si_saved_cs
**dst
, struct si_saved_cs
*src
)
860 if (pipe_reference(&(*dst
)->reference
, &src
->reference
))
861 si_destroy_saved_cs(*dst
);
867 si_make_CB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
868 bool shaders_read_metadata
)
870 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
|
871 SI_CONTEXT_INV_VMEM_L1
;
873 if (sctx
->b
.chip_class
>= GFX9
) {
874 /* Single-sample color is coherent with shaders on GFX9, but
875 * L2 metadata must be flushed if shaders read metadata.
878 if (num_samples
>= 2)
879 sctx
->b
.flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
880 else if (shaders_read_metadata
)
881 sctx
->b
.flags
|= SI_CONTEXT_INV_L2_METADATA
;
884 sctx
->b
.flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
889 si_make_DB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
890 bool include_stencil
, bool shaders_read_metadata
)
892 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_DB
|
893 SI_CONTEXT_INV_VMEM_L1
;
895 if (sctx
->b
.chip_class
>= GFX9
) {
896 /* Single-sample depth (not stencil) is coherent with shaders
897 * on GFX9, but L2 metadata must be flushed if shaders read
900 if (num_samples
>= 2 || include_stencil
)
901 sctx
->b
.flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
902 else if (shaders_read_metadata
)
903 sctx
->b
.flags
|= SI_CONTEXT_INV_L2_METADATA
;
906 sctx
->b
.flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
911 si_can_sample_zs(struct r600_texture
*tex
, bool stencil_sampler
)
913 return (stencil_sampler
&& tex
->can_sample_s
) ||
914 (!stencil_sampler
&& tex
->can_sample_z
);
918 si_htile_enabled(struct r600_texture
*tex
, unsigned level
)
920 return tex
->htile_offset
&& level
== 0;
924 vi_tc_compat_htile_enabled(struct r600_texture
*tex
, unsigned level
)
926 assert(!tex
->tc_compatible_htile
|| tex
->htile_offset
);
927 return tex
->tc_compatible_htile
&& level
== 0;