2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "si_shader.h"
30 #include "util/u_dynarray.h"
31 #include "util/u_idalloc.h"
32 #include "util/u_threaded_context.h"
34 #if UTIL_ARCH_BIG_ENDIAN
35 #define SI_BIG_ENDIAN 1
37 #define SI_BIG_ENDIAN 0
40 #define ATI_VENDOR_ID 0x1002
41 #define SI_PRIM_DISCARD_DEBUG 0
42 #define SI_NOT_QUERY 0xffffffff
44 /* The base vertex and primitive restart can be any number, but we must pick
45 * one which will mean "unknown" for the purpose of state tracking and
46 * the number shouldn't be a commonly-used one. */
47 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
48 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
49 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
50 #define SI_NUM_SMOOTH_AA_SAMPLES 8
51 #define SI_MAX_POINT_SIZE 2048
52 #define SI_GS_PER_ES 128
53 /* Alignment for optimal CP DMA performance. */
54 #define SI_CPDMA_ALIGNMENT 32
56 /* Tunables for compute-based clear_buffer and copy_buffer: */
57 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
58 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
59 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
61 /* Pipeline & streamout query controls. */
62 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
63 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
64 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
65 /* Instruction cache. */
66 #define SI_CONTEXT_INV_ICACHE (1 << 3)
67 /* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
68 * GFX10: This also invalidates the L1 shader array cache. */
69 #define SI_CONTEXT_INV_SCACHE (1 << 4)
70 /* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
71 * GFX10: This also invalidates the L1 shader array cache. */
72 #define SI_CONTEXT_INV_VCACHE (1 << 5)
73 /* L2 cache + L2 metadata cache writeback & invalidate.
74 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
75 #define SI_CONTEXT_INV_L2 (1 << 6)
76 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
77 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
78 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
79 #define SI_CONTEXT_WB_L2 (1 << 7)
80 /* Writeback & invalidate the L2 metadata cache only. It can only be coupled with
81 * a CB or DB flush. */
82 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
83 /* Framebuffer caches. */
84 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
85 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
86 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
87 /* Engine synchronization. */
88 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
89 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
90 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
91 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
92 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
94 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
95 #define SI_PREFETCH_LS (1 << 1)
96 #define SI_PREFETCH_HS (1 << 2)
97 #define SI_PREFETCH_ES (1 << 3)
98 #define SI_PREFETCH_GS (1 << 4)
99 #define SI_PREFETCH_VS (1 << 5)
100 #define SI_PREFETCH_PS (1 << 6)
102 #define SI_MAX_BORDER_COLORS 4096
103 #define SI_MAX_VIEWPORTS 16
104 #define SIX_BITS 0x3F
105 #define SI_MAP_BUFFER_ALIGNMENT 64
106 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
108 #define SI_RESOURCE_FLAG_FORCE_LINEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
109 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
110 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
111 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
112 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
113 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
114 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
115 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
116 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
117 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
118 /* Set a micro tile mode: */
119 #define SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE (PIPE_RESOURCE_FLAG_DRV_PRIV << 9)
120 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT (util_logbase2(PIPE_RESOURCE_FLAG_DRV_PRIV) + 10)
121 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_SET(x) \
122 (((x)&0x3) << SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT)
123 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(x) \
124 (((x) >> SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT) & 0x3)
125 #define SI_RESOURCE_FLAG_UNCACHED (PIPE_RESOURCE_FLAG_DRV_PRIV << 12)
129 DCC_CLEAR_COLOR_0000
= 0x00000000,
130 DCC_CLEAR_COLOR_0001
= 0x40404040,
131 DCC_CLEAR_COLOR_1110
= 0x80808080,
132 DCC_CLEAR_COLOR_1111
= 0xC0C0C0C0,
133 DCC_CLEAR_COLOR_REG
= 0x20202020,
134 DCC_UNCOMPRESSED
= 0xFFFFFFFF,
137 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
138 #define SI_IMAGE_ACCESS_DCC_OFF (1 << 8)
143 /* Shader logging options: */
144 DBG_VS
= MESA_SHADER_VERTEX
,
145 DBG_TCS
= MESA_SHADER_TESS_CTRL
,
146 DBG_TES
= MESA_SHADER_TESS_EVAL
,
147 DBG_GS
= MESA_SHADER_GEOMETRY
,
148 DBG_PS
= MESA_SHADER_FRAGMENT
,
149 DBG_CS
= MESA_SHADER_COMPUTE
,
155 /* Shader compiler options the shader cache should be aware of: */
156 DBG_FS_CORRECT_DERIVS_AFTER_KILL
,
164 DBG_KILL_PS_INF_INTERP
,
165 DBG_CLAMP_DIV_BY_ZERO
,
167 /* Shader compiler options (with no effect on the shader cache): */
169 DBG_MONOLITHIC_SHADERS
,
172 /* Information logging options: */
179 /* Driver options: */
183 DBG_NO_SDMA_COPY_IMAGE
,
190 /* 3D engine options: */
193 DBG_ALWAYS_NGG_CULLING_ALL
,
194 DBG_ALWAYS_NGG_CULLING_TESS
,
223 DBG_TEST_VMFAULT_SDMA
,
224 DBG_TEST_VMFAULT_SHADER
,
231 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
232 #define DBG(name) (1ull << DBG_##name)
237 L2_STREAM
, /* same as SLC=1 */
238 L2_LRU
, /* same as SLC=0 */
243 SI_COHERENCY_NONE
, /* no cache flushes needed */
245 SI_COHERENCY_CB_META
,
246 SI_COHERENCY_DB_META
,
251 struct si_shader_context
;
253 struct u_suballocator
;
255 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
259 struct threaded_resource b
;
261 /* Winsys objects. */
262 struct pb_buffer
*buf
;
263 uint64_t gpu_address
;
264 /* Memory usage if the buffer placement is optimal. */
268 /* Resource properties. */
270 unsigned bo_alignment
;
271 enum radeon_bo_domain domains
;
272 enum radeon_bo_flag flags
;
273 unsigned bind_history
;
274 int max_forced_staging_uploads
;
276 /* The buffer range which is initialized (with a write transfer,
277 * streamout, DMA, or as a random access target). The rest of
278 * the buffer is considered invalid and can be mapped unsynchronized.
280 * This allows unsychronized mapping of a buffer range which hasn't
281 * been used yet. It's for applications which forget to use
282 * the unsynchronized map flag and expect the driver to figure it out.
284 struct util_range valid_buffer_range
;
286 /* For buffers only. This indicates that a write operation has been
287 * performed by TC L2, but the cache hasn't been flushed.
288 * Any hw block which doesn't use or bypasses TC L2 should check this
289 * flag and flush the cache before using the buffer.
291 * For example, TC L2 must be flushed if a buffer which has been
292 * modified by a shader store instruction is about to be used as
293 * an index buffer. The reason is that VGT DMA index fetching doesn't
298 /* Whether this resource is referenced by bindless handles. */
299 bool texture_handle_allocated
;
300 bool image_handle_allocated
;
302 /* Whether the resource has been exported via resource_get_handle. */
303 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
307 struct threaded_transfer b
;
308 struct si_resource
*staging
;
313 struct si_resource buffer
;
315 struct radeon_surf surface
;
316 struct si_texture
*flushed_depth_texture
;
318 /* One texture allocation can contain these buffers:
319 * - image (pixel data)
320 * - FMASK buffer (MSAA compression)
321 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
322 * - HTILE buffer (Z/S compression and fast Z/S clear)
323 * - DCC buffer (color compression and new fast color clear)
324 * - displayable DCC buffer (if the DCC buffer is not displayable)
325 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
327 uint64_t cmask_base_address_reg
;
328 struct si_resource
*cmask_buffer
;
329 unsigned cb_color_info
; /* fast clear enable bit */
330 unsigned color_clear_value
[2];
331 unsigned last_msaa_resolve_target_micro_mode
;
332 unsigned num_level0_transfers
;
333 unsigned plane_index
; /* other planes are different pipe_resources */
336 /* Depth buffer compression and fast clear. */
337 float depth_clear_value
;
338 uint16_t dirty_level_mask
; /* each bit says if that mipmap is compressed */
339 uint16_t stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
340 enum pipe_format db_render_format
: 16;
341 uint8_t stencil_clear_value
;
342 bool fmask_is_identity
: 1;
343 bool tc_compatible_htile
: 1;
344 bool enable_tc_compatible_htile_next_clear
: 1;
345 bool htile_stencil_disabled
: 1;
346 bool depth_cleared
: 1; /* if it was cleared at least once */
347 bool stencil_cleared
: 1; /* if it was cleared at least once */
348 bool upgraded_depth
: 1; /* upgraded from unorm to Z32_FLOAT */
350 bool db_compatible
: 1;
351 bool can_sample_z
: 1;
352 bool can_sample_s
: 1;
354 /* We need to track DCC dirtiness, because st/dri usually calls
355 * flush_resource twice per frame (not a bug) and we don't wanna
356 * decompress DCC twice. Also, the dirty tracking must be done even
357 * if DCC isn't used, because it's required by the DCC usage analysis
358 * for a possible future enablement.
360 bool separate_dcc_dirty
: 1;
361 bool displayable_dcc_dirty
: 1;
363 /* Statistics gathering for the DCC enablement heuristic. */
364 bool dcc_gather_statistics
: 1;
365 /* Counter that should be non-zero if the texture is bound to a
368 unsigned framebuffers_bound
;
369 /* Whether the texture is a displayable back buffer and needs DCC
370 * decompression, which is expensive. Therefore, it's enabled only
371 * if statistics suggest that it will pay off and it's allocated
372 * separately. It can't be bound as a sampler by apps. Limited to
373 * target == 2D and last_level == 0. If enabled, dcc_offset contains
374 * the absolute GPUVM address, not the relative one.
376 struct si_resource
*dcc_separate_buffer
;
377 /* When DCC is temporarily disabled, the separate buffer is here. */
378 struct si_resource
*last_dcc_separate_buffer
;
379 /* Estimate of how much this color buffer is written to in units of
380 * full-screen draws: ps_invocations / (width * height)
381 * Shader kills, late Z, and blending with trivial discards make it
382 * inaccurate (we need to count CB updates, not PS invocations).
384 unsigned ps_draw_ratio
;
385 /* The number of clears since the last DCC usage analysis. */
386 unsigned num_slow_clears
;
390 struct pipe_surface base
;
392 /* These can vary with block-compressed textures. */
396 bool color_initialized
: 1;
397 bool depth_initialized
: 1;
399 /* Misc. color flags. */
400 bool color_is_int8
: 1;
401 bool color_is_int10
: 1;
402 bool dcc_incompatible
: 1;
404 /* Color registers. */
405 unsigned cb_color_info
;
406 unsigned cb_color_view
;
407 unsigned cb_color_attrib
;
408 unsigned cb_color_attrib2
; /* GFX9 and later */
409 unsigned cb_color_attrib3
; /* GFX10 and later */
410 unsigned cb_dcc_control
; /* GFX8 and later */
411 unsigned spi_shader_col_format
: 8; /* no blending, no alpha-to-coverage. */
412 unsigned spi_shader_col_format_alpha
: 8; /* alpha-to-coverage */
413 unsigned spi_shader_col_format_blend
: 8; /* blending without alpha. */
414 unsigned spi_shader_col_format_blend_alpha
: 8; /* blending with alpha. */
417 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE */
418 uint64_t db_stencil_base
;
419 uint64_t db_htile_data_base
;
420 unsigned db_depth_info
;
422 unsigned db_z_info2
; /* GFX9 only */
423 unsigned db_depth_view
;
424 unsigned db_depth_size
;
425 unsigned db_depth_slice
;
426 unsigned db_stencil_info
;
427 unsigned db_stencil_info2
; /* GFX9 only */
428 unsigned db_htile_surface
;
431 struct si_mmio_counter
{
436 union si_mmio_counters
{
437 struct si_mmio_counters_named
{
438 /* For global GPU load including SDMA. */
439 struct si_mmio_counter gpu
;
442 struct si_mmio_counter spi
;
443 struct si_mmio_counter gui
;
444 struct si_mmio_counter ta
;
445 struct si_mmio_counter gds
;
446 struct si_mmio_counter vgt
;
447 struct si_mmio_counter ia
;
448 struct si_mmio_counter sx
;
449 struct si_mmio_counter wd
;
450 struct si_mmio_counter bci
;
451 struct si_mmio_counter sc
;
452 struct si_mmio_counter pa
;
453 struct si_mmio_counter db
;
454 struct si_mmio_counter cp
;
455 struct si_mmio_counter cb
;
458 struct si_mmio_counter sdma
;
461 struct si_mmio_counter pfp
;
462 struct si_mmio_counter meq
;
463 struct si_mmio_counter me
;
464 struct si_mmio_counter surf_sync
;
465 struct si_mmio_counter cp_dma
;
466 struct si_mmio_counter scratch_ram
;
469 unsigned array
[sizeof(struct si_mmio_counters_named
) / sizeof(unsigned)];
472 struct si_memory_object
{
473 struct pipe_memory_object b
;
474 struct pb_buffer
*buf
;
478 /* Saved CS data for debugging features. */
479 struct radeon_saved_cs
{
483 struct radeon_bo_list_item
*bo_list
;
488 struct pipe_screen b
;
489 struct radeon_winsys
*ws
;
490 struct disk_cache
*disk_shader_cache
;
492 struct radeon_info info
;
493 struct nir_shader_compiler_options nir_options
;
494 uint64_t debug_flags
;
495 char renderer_string
[183];
497 void (*make_texture_descriptor
)(struct si_screen
*screen
, struct si_texture
*tex
, bool sampler
,
498 enum pipe_texture_target target
, enum pipe_format pipe_format
,
499 const unsigned char state_swizzle
[4], unsigned first_level
,
500 unsigned last_level
, unsigned first_layer
, unsigned last_layer
,
501 unsigned width
, unsigned height
, unsigned depth
, uint32_t *state
,
502 uint32_t *fmask_state
);
504 unsigned num_vbos_in_user_sgprs
;
505 unsigned pa_sc_raster_config
;
506 unsigned pa_sc_raster_config_1
;
507 unsigned se_tile_repeat
;
508 unsigned gs_table_depth
;
509 unsigned tess_offchip_block_dw_size
;
510 unsigned tess_offchip_ring_size
;
511 unsigned tess_factor_ring_size
;
512 unsigned vgt_hs_offchip_param
;
513 unsigned eqaa_force_coverage_samples
;
514 unsigned eqaa_force_z_samples
;
515 unsigned eqaa_force_color_samples
;
516 bool has_draw_indirect_multi
;
517 bool has_out_of_order_rast
;
518 bool assume_no_z_fights
;
519 bool commutative_blend_add
;
522 bool llvm_has_working_vgpr_indexing
;
524 bool use_ngg_culling
;
525 bool always_use_ngg_culling_all
;
526 bool always_use_ngg_culling_tess
;
527 bool use_ngg_streamout
;
530 #define OPT_BOOL(name, dflt, description) bool name : 1;
531 #include "si_debug_options.h"
534 /* Whether shaders are monolithic (1-part) or separate (3-part). */
535 bool use_monolithic_shaders
;
537 bool dcc_msaa_allowed
;
539 struct slab_parent_pool pool_transfers
;
541 /* Texture filter settings. */
542 int force_aniso
; /* -1 = disabled */
544 /* Auxiliary context. Mainly used to initialize resources.
545 * It must be locked prior to using and flushed before unlocking. */
546 struct pipe_context
*aux_context
;
547 simple_mtx_t aux_context_lock
;
549 /* This must be in the screen, because UE4 uses one context for
550 * compilation and another one for rendering.
552 unsigned num_compilations
;
553 /* Along with ST_DEBUG=precompile, this should show if applications
554 * are loading shaders on demand. This is a monotonic counter.
556 unsigned num_shaders_created
;
557 unsigned num_memory_shader_cache_hits
;
558 unsigned num_memory_shader_cache_misses
;
559 unsigned num_disk_shader_cache_hits
;
560 unsigned num_disk_shader_cache_misses
;
562 /* GPU load thread. */
563 simple_mtx_t gpu_load_mutex
;
564 thrd_t gpu_load_thread
;
565 union si_mmio_counters mmio_counters
;
566 volatile unsigned gpu_load_stop_thread
; /* bool */
568 /* Performance counters. */
569 struct si_perfcounters
*perfcounters
;
571 /* If pipe_screen wants to recompute and re-emit the framebuffer,
572 * sampler, and image states of all contexts, it should atomically
575 * Each context will compare this with its own last known value of
576 * the counter before drawing and re-emit the states accordingly.
578 unsigned dirty_tex_counter
;
579 unsigned dirty_buf_counter
;
581 /* Atomically increment this counter when an existing texture's
582 * metadata is enabled or disabled in a way that requires changing
583 * contexts' compressed texture binding masks.
585 unsigned compressed_colortex_counter
;
588 /* Context flags to set so that all writes from earlier jobs
589 * in the CP are seen by L2 clients.
593 /* Context flags to set so that all writes from earlier jobs
594 * that end in L2 are seen by CP.
599 simple_mtx_t shader_parts_mutex
;
600 struct si_shader_part
*vs_prologs
;
601 struct si_shader_part
*tcs_epilogs
;
602 struct si_shader_part
*gs_prologs
;
603 struct si_shader_part
*ps_prologs
;
604 struct si_shader_part
*ps_epilogs
;
606 /* Shader cache in memory.
608 * Design & limitations:
609 * - The shader cache is per screen (= per process), never saved to
610 * disk, and skips redundant shader compilations from NIR to bytecode.
611 * - It can only be used with one-variant-per-shader support, in which
612 * case only the main (typically middle) part of shaders is cached.
613 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
614 * variants of VS and TES are cached, so LS and ES aren't.
615 * - GS and CS aren't cached, but it's certainly possible to cache
618 simple_mtx_t shader_cache_mutex
;
619 struct hash_table
*shader_cache
;
621 /* Shader cache of live shaders. */
622 struct util_live_shader_cache live_shader_cache
;
624 /* Shader compiler queue for multithreaded compilation. */
625 struct util_queue shader_compiler_queue
;
626 /* Use at most 3 normal compiler threads on quadcore and better.
627 * Hyperthreaded CPUs report the number of threads, but we want
628 * the number of cores. We only need this many threads for shader-db. */
629 struct ac_llvm_compiler compiler
[24]; /* used by the queue only */
631 struct util_queue shader_compiler_queue_low_priority
;
632 /* Use at most 2 low priority threads on quadcore and better.
633 * We want to minimize the impact on multithreaded Mesa. */
634 struct ac_llvm_compiler compiler_lowp
[10];
636 unsigned compute_wave_size
;
637 unsigned ps_wave_size
;
638 unsigned ge_wave_size
;
641 struct si_blend_color
{
642 struct pipe_blend_color state
;
646 struct si_sampler_view
{
647 struct pipe_sampler_view base
;
648 /* [0..7] = image descriptor
649 * [4..7] = buffer descriptor */
651 uint32_t fmask_state
[8];
652 const struct legacy_surf_level
*base_level_info
;
655 bool is_stencil_sampler
;
657 bool dcc_incompatible
;
660 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
662 struct si_sampler_state
{
667 uint32_t integer_val
[4];
668 uint32_t upgraded_depth_val
[4];
671 struct si_cs_shader_state
{
672 struct si_compute
*program
;
673 struct si_compute
*emitted_program
;
680 struct pipe_sampler_view
*views
[SI_NUM_SAMPLERS
];
681 struct si_sampler_state
*sampler_states
[SI_NUM_SAMPLERS
];
683 /* The i-th bit is set if that element is enabled (non-NULL resource). */
684 unsigned enabled_mask
;
685 uint32_t needs_depth_decompress_mask
;
686 uint32_t needs_color_decompress_mask
;
690 struct pipe_image_view views
[SI_NUM_IMAGES
];
691 uint32_t needs_color_decompress_mask
;
692 unsigned enabled_mask
;
695 struct si_framebuffer
{
696 struct pipe_framebuffer_state state
;
697 unsigned colorbuf_enabled_4bit
;
698 unsigned spi_shader_col_format
;
699 unsigned spi_shader_col_format_alpha
;
700 unsigned spi_shader_col_format_blend
;
701 unsigned spi_shader_col_format_blend_alpha
;
702 ubyte nr_samples
: 5; /* at most 16xAA */
703 ubyte log_samples
: 3; /* at most 4 = 16xAA */
704 ubyte nr_color_samples
; /* at most 8xAA */
705 ubyte compressed_cb_mask
;
706 ubyte uncompressed_cb_mask
;
707 ubyte displayable_dcc_cb_mask
;
709 ubyte color_is_int10
;
711 ubyte dcc_overwrite_combiner_watermark
;
712 ubyte min_bytes_per_pixel
;
715 bool CB_has_shader_readable_metadata
;
716 bool DB_has_shader_readable_metadata
;
717 bool all_DCC_pipe_aligned
;
724 /* This is the list we want to support. */
725 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH
,
726 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH
,
727 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH
,
730 struct si_signed_scissor
{
735 enum si_quant_mode quant_mode
;
738 struct si_viewports
{
739 struct pipe_viewport_state states
[SI_MAX_VIEWPORTS
];
740 struct si_signed_scissor as_scissor
[SI_MAX_VIEWPORTS
];
744 struct si_clip_state
{
745 struct pipe_clip_state state
;
749 struct si_streamout_target
{
750 struct pipe_stream_output_target b
;
752 /* The buffer where BUFFER_FILLED_SIZE is stored. */
753 struct si_resource
*buf_filled_size
;
754 unsigned buf_filled_size_offset
;
755 bool buf_filled_size_valid
;
757 unsigned stride_in_dw
;
760 struct si_streamout
{
763 unsigned enabled_mask
;
764 unsigned num_targets
;
765 struct si_streamout_target
*targets
[PIPE_MAX_SO_BUFFERS
];
767 unsigned append_bitmask
;
770 /* External state which comes from the vertex shader,
771 * it must be set explicitly when binding a shader. */
772 uint16_t *stride_in_dw
;
773 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
775 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
776 unsigned hw_enabled_mask
;
778 /* The state of VGT_STRMOUT_(CONFIG|EN). */
779 bool streamout_enabled
;
780 bool prims_gen_query_enabled
;
781 int num_prims_gen_queries
;
784 /* A shader state consists of the shader selector, which is a constant state
785 * object shared by multiple contexts and shouldn't be modified, and
786 * the current shader variant selected for this context.
788 struct si_shader_ctx_state
{
789 struct si_shader_selector
*cso
;
790 struct si_shader
*current
;
793 #define SI_NUM_VGT_PARAM_KEY_BITS 12
794 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
796 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
797 * Some fields are set by state-change calls, most are set by draw_vbo.
799 union si_vgt_param_key
{
801 #if UTIL_ARCH_LITTLE_ENDIAN
803 unsigned uses_instancing
: 1;
804 unsigned multi_instances_smaller_than_primgroup
: 1;
805 unsigned primitive_restart
: 1;
806 unsigned count_from_stream_output
: 1;
807 unsigned line_stipple_enabled
: 1;
808 unsigned uses_tess
: 1;
809 unsigned tess_uses_prim_id
: 1;
810 unsigned uses_gs
: 1;
811 unsigned _pad
: 32 - SI_NUM_VGT_PARAM_KEY_BITS
;
812 #else /* UTIL_ARCH_BIG_ENDIAN */
813 unsigned _pad
: 32 - SI_NUM_VGT_PARAM_KEY_BITS
;
814 unsigned uses_gs
: 1;
815 unsigned tess_uses_prim_id
: 1;
816 unsigned uses_tess
: 1;
817 unsigned line_stipple_enabled
: 1;
818 unsigned count_from_stream_output
: 1;
819 unsigned primitive_restart
: 1;
820 unsigned multi_instances_smaller_than_primgroup
: 1;
821 unsigned uses_instancing
: 1;
828 #define SI_NUM_VGT_STAGES_KEY_BITS 6
829 #define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS)
831 /* The VGT_SHADER_STAGES key used to index the table of precomputed values.
832 * Some fields are set by state-change calls, most are set by draw_vbo.
834 union si_vgt_stages_key
{
836 #if UTIL_ARCH_LITTLE_ENDIAN
839 unsigned ngg_gs_fast_launch
: 1;
840 unsigned ngg_passthrough
: 1;
841 unsigned ngg
: 1; /* gfx10+ */
842 unsigned streamout
: 1; /* only used with NGG */
843 unsigned _pad
: 32 - SI_NUM_VGT_STAGES_KEY_BITS
;
844 #else /* UTIL_ARCH_BIG_ENDIAN */
845 unsigned _pad
: 32 - SI_NUM_VGT_STAGES_KEY_BITS
;
846 unsigned streamout
: 1;
848 unsigned ngg_passthrough
: 1;
849 unsigned ngg_gs_fast_launch
: 1;
857 struct si_texture_handle
{
860 struct pipe_sampler_view
*view
;
861 struct si_sampler_state sstate
;
864 struct si_image_handle
{
867 struct pipe_image_view view
;
871 struct pipe_reference reference
;
872 struct si_context
*ctx
;
873 struct radeon_saved_cs gfx
;
874 struct radeon_saved_cs compute
;
875 struct si_resource
*trace_buf
;
878 unsigned gfx_last_dw
;
879 unsigned compute_last_dw
;
884 struct si_sdma_upload
{
885 struct si_resource
*dst
;
886 struct si_resource
*src
;
892 struct si_small_prim_cull_info
{
893 float scale
[2], translate
[2];
897 struct pipe_context b
; /* base class */
899 enum radeon_family family
;
900 enum chip_class chip_class
;
902 struct radeon_winsys
*ws
;
903 struct radeon_winsys_ctx
*ctx
;
904 struct radeon_cmdbuf
*gfx_cs
; /* compute IB if graphics is disabled */
905 struct radeon_cmdbuf
*sdma_cs
;
906 struct pipe_fence_handle
*last_gfx_fence
;
907 struct pipe_fence_handle
*last_sdma_fence
;
908 struct si_resource
*eop_bug_scratch
;
909 struct u_upload_mgr
*cached_gtt_allocator
;
910 struct threaded_context
*tc
;
911 struct u_suballocator
*allocator_zeroed_memory
;
912 struct slab_child_pool pool_transfers
;
913 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
914 struct pipe_device_reset_callback device_reset_callback
;
915 struct u_log_context
*log
;
916 void *query_result_shader
;
917 void *sh_query_result_shader
;
918 struct si_resource
*shadowed_regs
;
920 void (*emit_cache_flush
)(struct si_context
*ctx
);
922 struct blitter_context
*blitter
;
925 void *discard_rasterizer_state
;
926 void *custom_dsa_flush
;
927 void *custom_blend_resolve
;
928 void *custom_blend_fmask_decompress
;
929 void *custom_blend_eliminate_fastclear
;
930 void *custom_blend_dcc_decompress
;
932 void *vs_blit_pos_layered
;
934 void *vs_blit_color_layered
;
935 void *vs_blit_texcoord
;
936 void *cs_clear_buffer
;
937 void *cs_copy_buffer
;
939 void *cs_copy_image_1d_array
;
940 void *cs_clear_render_target
;
941 void *cs_clear_render_target_1d_array
;
942 void *cs_clear_12bytes_buffer
;
943 void *cs_dcc_decompress
;
945 void *cs_fmask_expand
[3][2]; /* [log2(samples)-1][is_array] */
946 struct si_screen
*screen
;
947 struct pipe_debug_callback debug
;
948 struct ac_llvm_compiler compiler
; /* only non-threaded compilation */
949 struct si_shader_ctx_state fixed_func_tcs_shader
;
950 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
951 struct si_resource
*wait_mem_scratch
;
952 unsigned wait_mem_number
;
953 uint16_t prefetch_L2_mask
;
956 bool gfx_flush_in_progress
: 1;
957 bool gfx_last_ib_is_busy
: 1;
958 bool compute_is_busy
: 1;
960 unsigned num_gfx_cs_flushes
;
961 unsigned initial_gfx_cs_size
;
962 unsigned last_dirty_tex_counter
;
963 unsigned last_dirty_buf_counter
;
964 unsigned last_compressed_colortex_counter
;
965 unsigned last_num_draw_calls
;
966 unsigned flags
; /* flush flags */
967 /* Current unaccounted memory usage. */
971 /* Compute-based primitive discard. */
972 unsigned prim_discard_vertex_count_threshold
;
973 struct pb_buffer
*gds
;
974 struct pb_buffer
*gds_oa
;
975 struct radeon_cmdbuf
*prim_discard_compute_cs
;
976 unsigned compute_gds_offset
;
977 struct si_shader
*compute_ib_last_shader
;
978 uint32_t compute_rewind_va
;
979 unsigned compute_num_prims_in_batch
;
980 bool preserve_prim_restart_gds_at_flush
;
981 /* index_ring is divided into 2 halves for doublebuffering. */
982 struct si_resource
*index_ring
;
983 unsigned index_ring_base
; /* offset of a per-IB portion */
984 unsigned index_ring_offset
; /* offset within a per-IB portion */
985 unsigned index_ring_size_per_ib
; /* max available size per IB */
986 bool prim_discard_compute_ib_initialized
;
987 /* For tracking the last execution barrier - it can be either
988 * a WRITE_DATA packet or a fence. */
989 uint32_t *last_pkt3_write_data
;
990 struct si_resource
*barrier_buf
;
991 unsigned barrier_buf_offset
;
992 struct pipe_fence_handle
*last_ib_barrier_fence
;
993 struct si_resource
*last_ib_barrier_buf
;
994 unsigned last_ib_barrier_buf_offset
;
996 /* Atoms (direct states). */
997 union si_state_atoms atoms
;
998 unsigned dirty_atoms
; /* mask */
999 /* PM4 states (precomputed immutable states) */
1000 unsigned dirty_states
;
1001 union si_state queued
;
1002 union si_state emitted
;
1004 /* Atom declarations. */
1005 struct si_framebuffer framebuffer
;
1006 unsigned sample_locs_num_samples
;
1007 uint16_t sample_mask
;
1008 unsigned last_cb_target_mask
;
1009 struct si_blend_color blend_color
;
1010 struct si_clip_state clip_state
;
1011 struct si_shader_data shader_pointers
;
1012 struct si_stencil_ref stencil_ref
;
1013 struct pipe_scissor_state scissors
[SI_MAX_VIEWPORTS
];
1014 struct si_streamout streamout
;
1015 struct si_viewports viewports
;
1016 unsigned num_window_rectangles
;
1017 bool window_rectangles_include
;
1018 struct pipe_scissor_state window_rectangles
[4];
1020 /* Precomputed states. */
1021 struct si_pm4_state
*cs_preamble_state
;
1022 struct si_pm4_state
*cs_preamble_gs_rings
;
1023 bool cs_preamble_has_vgt_flush
;
1024 struct si_pm4_state
*vgt_shader_config
[SI_NUM_VGT_STAGES_STATES
];
1027 struct si_shader_ctx_state ps_shader
;
1028 struct si_shader_ctx_state gs_shader
;
1029 struct si_shader_ctx_state vs_shader
;
1030 struct si_shader_ctx_state tcs_shader
;
1031 struct si_shader_ctx_state tes_shader
;
1032 struct si_shader_ctx_state cs_prim_discard_state
;
1033 struct si_cs_shader_state cs_shader_state
;
1035 /* shader information */
1036 struct si_vertex_elements
*vertex_elements
;
1037 unsigned num_vertex_elements
;
1038 unsigned sprite_coord_enable
;
1039 unsigned cs_max_waves_per_sh
;
1041 bool do_update_shaders
;
1042 bool compute_shaderbuf_sgprs_dirty
;
1043 bool compute_image_sgprs_dirty
;
1045 /* shader descriptors */
1046 struct si_descriptors descriptors
[SI_NUM_DESCS
];
1047 unsigned descriptors_dirty
;
1048 unsigned shader_pointers_dirty
;
1049 unsigned shader_needs_decompress_mask
;
1050 struct si_buffer_resources rw_buffers
;
1051 struct si_buffer_resources const_and_shader_buffers
[SI_NUM_SHADERS
];
1052 struct si_samplers samplers
[SI_NUM_SHADERS
];
1053 struct si_images images
[SI_NUM_SHADERS
];
1054 bool bo_list_add_all_resident_resources
;
1055 bool bo_list_add_all_gfx_resources
;
1056 bool bo_list_add_all_compute_resources
;
1058 /* other shader resources */
1059 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on GFX7 */
1060 struct pipe_resource
*esgs_ring
;
1061 struct pipe_resource
*gsvs_ring
;
1062 struct pipe_resource
*tess_rings
;
1063 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
1064 struct si_resource
*border_color_buffer
;
1065 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
1066 unsigned border_color_count
;
1067 unsigned num_vs_blit_sgprs
;
1068 uint32_t vs_blit_sh_data
[SI_VS_BLIT_SGPRS_POS_TEXCOORD
];
1069 uint32_t cs_user_data
[4];
1071 /* Vertex buffers. */
1072 bool vertex_buffers_dirty
;
1073 bool vertex_buffer_pointer_dirty
;
1074 bool vertex_buffer_user_sgprs_dirty
;
1075 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
1076 uint16_t vertex_buffer_unaligned
; /* bitmask of not dword-aligned buffers */
1077 uint32_t *vb_descriptors_gpu_list
;
1078 struct si_resource
*vb_descriptors_buffer
;
1079 unsigned vb_descriptors_offset
;
1080 unsigned vb_descriptor_user_sgprs
[5 * 4];
1082 /* MSAA config state. */
1083 int ps_iter_samples
;
1084 bool ps_uses_fbfetch
;
1085 bool smoothing_enabled
;
1087 /* DB render state. */
1088 unsigned ps_db_shader_control
;
1089 unsigned dbcb_copy_sample
;
1090 bool dbcb_depth_copy_enabled
: 1;
1091 bool dbcb_stencil_copy_enabled
: 1;
1092 bool db_flush_depth_inplace
: 1;
1093 bool db_flush_stencil_inplace
: 1;
1094 bool db_depth_clear
: 1;
1095 bool db_depth_disable_expclear
: 1;
1096 bool db_stencil_clear
: 1;
1097 bool db_stencil_disable_expclear
: 1;
1098 bool occlusion_queries_disabled
: 1;
1099 bool generate_mipmap_for_depth
: 1;
1101 /* Emitted draw state. */
1102 bool gs_tri_strip_adj_fix
: 1;
1103 bool ls_vgpr_fix
: 1;
1104 bool prim_discard_cs_instancing
: 1;
1106 uint8_t ngg_culling
;
1107 int last_index_size
;
1108 int last_base_vertex
;
1109 int last_start_instance
;
1110 int last_instance_count
;
1112 int last_sh_base_reg
;
1113 int last_primitive_restart_en
;
1114 int last_restart_index
;
1116 int last_multi_vgt_param
;
1117 int last_gs_out_prim
;
1118 int last_binning_enabled
;
1119 unsigned current_vs_state
;
1120 unsigned last_vs_state
;
1121 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
1123 struct si_small_prim_cull_info last_small_prim_cull_info
;
1124 struct si_resource
*small_prim_cull_info_buf
;
1125 uint64_t small_prim_cull_info_address
;
1126 bool small_prim_cull_info_dirty
;
1128 /* Scratch buffer */
1129 struct si_resource
*scratch_buffer
;
1130 unsigned scratch_waves
;
1131 unsigned spi_tmpring_size
;
1132 unsigned max_seen_scratch_bytes_per_wave
;
1133 unsigned max_seen_compute_scratch_bytes_per_wave
;
1135 struct si_resource
*compute_scratch_buffer
;
1137 /* Emitted derived tessellation state. */
1138 /* Local shader (VS), or HS if LS-HS are merged. */
1139 struct si_shader
*last_ls
;
1140 struct si_shader_selector
*last_tcs
;
1141 int last_num_tcs_input_cp
;
1142 int last_tes_sh_base
;
1143 bool last_tess_uses_primid
;
1144 unsigned last_num_patches
;
1145 int last_ls_hs_config
;
1149 struct si_saved_cs
*current_saved_cs
;
1150 uint64_t dmesg_timestamp
;
1151 unsigned apitrace_call_number
;
1154 bool need_check_render_feedback
;
1155 bool decompression_enabled
;
1156 bool dpbb_force_off
;
1157 bool vs_writes_viewport_index
;
1158 bool vs_disables_clipping_viewport
;
1160 /* Precomputed IA_MULTI_VGT_PARAM */
1161 union si_vgt_param_key ia_multi_vgt_param_key
;
1162 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
1164 /* Bindless descriptors. */
1165 struct si_descriptors bindless_descriptors
;
1166 struct util_idalloc bindless_used_slots
;
1167 unsigned num_bindless_descriptors
;
1168 bool bindless_descriptors_dirty
;
1169 bool graphics_bindless_pointer_dirty
;
1170 bool compute_bindless_pointer_dirty
;
1172 /* Allocated bindless handles */
1173 struct hash_table
*tex_handles
;
1174 struct hash_table
*img_handles
;
1176 /* Resident bindless handles */
1177 struct util_dynarray resident_tex_handles
;
1178 struct util_dynarray resident_img_handles
;
1180 /* Resident bindless handles which need decompression */
1181 struct util_dynarray resident_tex_needs_color_decompress
;
1182 struct util_dynarray resident_img_needs_color_decompress
;
1183 struct util_dynarray resident_tex_needs_depth_decompress
;
1185 /* Bindless state */
1186 bool uses_bindless_samplers
;
1187 bool uses_bindless_images
;
1189 /* MSAA sample locations.
1190 * The first index is the sample index.
1191 * The second index is the coordinate: X, Y. */
1199 struct pipe_resource
*sample_pos_buffer
;
1202 unsigned num_draw_calls
;
1203 unsigned num_decompress_calls
;
1204 unsigned num_mrt_draw_calls
;
1205 unsigned num_prim_restart_calls
;
1206 unsigned num_spill_draw_calls
;
1207 unsigned num_compute_calls
;
1208 unsigned num_spill_compute_calls
;
1209 unsigned num_dma_calls
;
1210 unsigned num_cp_dma_calls
;
1211 unsigned num_vs_flushes
;
1212 unsigned num_ps_flushes
;
1213 unsigned num_cs_flushes
;
1214 unsigned num_cb_cache_flushes
;
1215 unsigned num_db_cache_flushes
;
1216 unsigned num_L2_invalidates
;
1217 unsigned num_L2_writebacks
;
1218 unsigned num_resident_handles
;
1219 uint64_t num_alloc_tex_transfer_bytes
;
1220 unsigned last_tex_ps_draw_ratio
; /* for query */
1221 unsigned compute_num_verts_accepted
;
1222 unsigned compute_num_verts_rejected
;
1223 unsigned compute_num_verts_ineligible
; /* due to low vertex count */
1224 unsigned context_roll
;
1227 /* Maintain the list of active queries for pausing between IBs. */
1228 int num_occlusion_queries
;
1229 int num_perfect_occlusion_queries
;
1230 int num_pipeline_stat_queries
;
1231 struct list_head active_queries
;
1232 unsigned num_cs_dw_queries_suspend
;
1234 /* Render condition. */
1235 struct pipe_query
*render_cond
;
1236 unsigned render_cond_mode
;
1237 bool render_cond_invert
;
1238 bool render_cond_force_off
; /* for u_blitter */
1240 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1241 bool sdma_uploads_in_progress
;
1242 struct si_sdma_upload
*sdma_uploads
;
1243 unsigned num_sdma_uploads
;
1244 unsigned max_sdma_uploads
;
1246 /* Shader-based queries. */
1247 struct list_head shader_query_buffers
;
1248 unsigned num_active_shader_queries
;
1250 /* Statistics gathering for the DCC enablement heuristic. It can't be
1251 * in si_texture because si_texture can be shared by multiple
1252 * contexts. This is for back buffers only. We shouldn't get too many
1255 * X11 DRI3 rotates among a finite set of back buffers. They should
1256 * all fit in this array. If they don't, separate DCC might never be
1257 * enabled by DCC stat gathering.
1260 struct si_texture
*tex
;
1261 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1262 struct pipe_query
*ps_stats
[3];
1263 /* If all slots are used and another slot is needed,
1264 * the least recently used slot is evicted based on this. */
1265 int64_t last_use_timestamp
;
1269 /* Copy one resource to another using async DMA. */
1270 void (*dma_copy
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
, unsigned dst_level
,
1271 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
, struct pipe_resource
*src
,
1272 unsigned src_level
, const struct pipe_box
*src_box
);
1274 struct si_tracked_regs tracked_regs
;
1278 void cik_init_sdma_functions(struct si_context
*sctx
);
1281 enum si_blitter_op
/* bitmask */
1283 SI_SAVE_TEXTURES
= 1,
1284 SI_SAVE_FRAMEBUFFER
= 2,
1285 SI_SAVE_FRAGMENT_STATE
= 4,
1286 SI_DISABLE_RENDER_COND
= 8,
1289 void si_blitter_begin(struct si_context
*sctx
, enum si_blitter_op op
);
1290 void si_blitter_end(struct si_context
*sctx
);
1291 void si_init_blit_functions(struct si_context
*sctx
);
1292 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
);
1293 void si_decompress_subresource(struct pipe_context
*ctx
, struct pipe_resource
*tex
, unsigned planes
,
1294 unsigned level
, unsigned first_layer
, unsigned last_layer
);
1295 void si_resource_copy_region(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
1296 unsigned dst_level
, unsigned dstx
, unsigned dsty
, unsigned dstz
,
1297 struct pipe_resource
*src
, unsigned src_level
,
1298 const struct pipe_box
*src_box
);
1299 void si_decompress_dcc(struct si_context
*sctx
, struct si_texture
*tex
);
1302 bool si_rings_is_buffer_referenced(struct si_context
*sctx
, struct pb_buffer
*buf
,
1303 enum radeon_bo_usage usage
);
1304 void *si_buffer_map_sync_with_rings(struct si_context
*sctx
, struct si_resource
*resource
,
1306 void si_init_resource_fields(struct si_screen
*sscreen
, struct si_resource
*res
, uint64_t size
,
1307 unsigned alignment
);
1308 bool si_alloc_resource(struct si_screen
*sscreen
, struct si_resource
*res
);
1309 struct pipe_resource
*pipe_aligned_buffer_create(struct pipe_screen
*screen
, unsigned flags
,
1310 unsigned usage
, unsigned size
, unsigned alignment
);
1311 struct si_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
, unsigned flags
,
1312 unsigned usage
, unsigned size
, unsigned alignment
);
1313 void si_replace_buffer_storage(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
1314 struct pipe_resource
*src
);
1315 void si_init_screen_buffer_functions(struct si_screen
*sscreen
);
1316 void si_init_buffer_functions(struct si_context
*sctx
);
1319 enum pipe_format
si_simplify_cb_format(enum pipe_format format
);
1320 bool vi_alpha_is_on_msb(struct si_screen
*sscreen
, enum pipe_format format
);
1321 bool vi_dcc_clear_level(struct si_context
*sctx
, struct si_texture
*tex
, unsigned level
,
1322 unsigned clear_value
);
1323 void si_init_clear_functions(struct si_context
*sctx
);
1325 /* si_compute_blit.c */
1326 unsigned si_get_flush_flags(struct si_context
*sctx
, enum si_coherency coher
,
1327 enum si_cache_policy cache_policy
);
1328 void si_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
, uint64_t offset
,
1329 uint64_t size
, uint32_t *clear_value
, uint32_t clear_value_size
,
1330 enum si_coherency coher
, bool force_cpdma
);
1331 void si_copy_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
, struct pipe_resource
*src
,
1332 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
);
1333 void si_compute_copy_image(struct si_context
*sctx
, struct pipe_resource
*dst
, unsigned dst_level
,
1334 struct pipe_resource
*src
, unsigned src_level
, unsigned dstx
,
1335 unsigned dsty
, unsigned dstz
, const struct pipe_box
*src_box
,
1336 bool is_dcc_decompress
);
1337 void si_compute_clear_render_target(struct pipe_context
*ctx
, struct pipe_surface
*dstsurf
,
1338 const union pipe_color_union
*color
, unsigned dstx
,
1339 unsigned dsty
, unsigned width
, unsigned height
,
1340 bool render_condition_enabled
);
1341 void si_retile_dcc(struct si_context
*sctx
, struct si_texture
*tex
);
1342 void si_compute_expand_fmask(struct pipe_context
*ctx
, struct pipe_resource
*tex
);
1343 void si_init_compute_blit_functions(struct si_context
*sctx
);
1346 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1347 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1348 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1349 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1350 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1351 #define SI_CPDMA_SKIP_TMZ (1 << 5) /* don't update tmz state */
1352 #define SI_CPDMA_SKIP_ALL \
1353 (SI_CPDMA_SKIP_CHECK_CS_SPACE | SI_CPDMA_SKIP_SYNC_AFTER | SI_CPDMA_SKIP_SYNC_BEFORE | \
1354 SI_CPDMA_SKIP_GFX_SYNC | SI_CPDMA_SKIP_BO_LIST_UPDATE | SI_CPDMA_SKIP_TMZ)
1356 void si_cp_dma_wait_for_idle(struct si_context
*sctx
);
1357 void si_cp_dma_clear_buffer(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
,
1358 struct pipe_resource
*dst
, uint64_t offset
, uint64_t size
,
1359 unsigned value
, unsigned user_flags
, enum si_coherency coher
,
1360 enum si_cache_policy cache_policy
);
1361 void si_cp_dma_copy_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1362 struct pipe_resource
*src
, uint64_t dst_offset
, uint64_t src_offset
,
1363 unsigned size
, unsigned user_flags
, enum si_coherency coher
,
1364 enum si_cache_policy cache_policy
);
1365 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
, uint64_t offset
,
1367 void cik_emit_prefetch_L2(struct si_context
*sctx
, bool vertex_stage_only
);
1368 void si_test_gds(struct si_context
*sctx
);
1369 void si_cp_write_data(struct si_context
*sctx
, struct si_resource
*buf
, unsigned offset
,
1370 unsigned size
, unsigned dst_sel
, unsigned engine
, const void *data
);
1371 void si_cp_copy_data(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
, unsigned dst_sel
,
1372 struct si_resource
*dst
, unsigned dst_offset
, unsigned src_sel
,
1373 struct si_resource
*src
, unsigned src_offset
);
1375 /* si_cp_reg_shadowing.c */
1376 void si_init_cp_reg_shadowing(struct si_context
*sctx
);
1379 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_cmdbuf
*cs
, struct radeon_saved_cs
*saved
,
1380 bool get_buffer_list
);
1381 void si_clear_saved_cs(struct radeon_saved_cs
*saved
);
1382 void si_destroy_saved_cs(struct si_saved_cs
*scs
);
1383 void si_auto_log_cs(void *data
, struct u_log_context
*log
);
1384 void si_log_hw_flush(struct si_context
*sctx
);
1385 void si_log_draw_state(struct si_context
*sctx
, struct u_log_context
*log
);
1386 void si_log_compute_state(struct si_context
*sctx
, struct u_log_context
*log
);
1387 void si_init_debug_functions(struct si_context
*sctx
);
1388 void si_check_vm_faults(struct si_context
*sctx
, struct radeon_saved_cs
*saved
,
1389 enum ring_type ring
);
1390 bool si_replace_shader(unsigned num
, struct si_shader_binary
*binary
);
1393 void si_dma_emit_timestamp(struct si_context
*sctx
, struct si_resource
*dst
, uint64_t offset
);
1394 void si_sdma_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
, uint64_t offset
,
1395 uint64_t size
, unsigned clear_value
);
1396 void si_sdma_copy_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1397 struct pipe_resource
*src
, uint64_t dst_offset
, uint64_t src_offset
,
1399 void si_need_dma_space(struct si_context
*ctx
, unsigned num_dw
, struct si_resource
*dst
,
1400 struct si_resource
*src
);
1401 void si_flush_dma_cs(struct si_context
*ctx
, unsigned flags
, struct pipe_fence_handle
**fence
);
1402 void si_screen_clear_buffer(struct si_screen
*sscreen
, struct pipe_resource
*dst
, uint64_t offset
,
1403 uint64_t size
, unsigned value
);
1406 void si_cp_release_mem(struct si_context
*ctx
, struct radeon_cmdbuf
*cs
, unsigned event
,
1407 unsigned event_flags
, unsigned dst_sel
, unsigned int_sel
, unsigned data_sel
,
1408 struct si_resource
*buf
, uint64_t va
, uint32_t new_fence
,
1409 unsigned query_type
);
1410 unsigned si_cp_write_fence_dwords(struct si_screen
*screen
);
1411 void si_cp_wait_mem(struct si_context
*ctx
, struct radeon_cmdbuf
*cs
, uint64_t va
, uint32_t ref
,
1412 uint32_t mask
, unsigned flags
);
1413 void si_init_fence_functions(struct si_context
*ctx
);
1414 void si_init_screen_fence_functions(struct si_screen
*screen
);
1415 struct pipe_fence_handle
*si_create_fence(struct pipe_context
*ctx
,
1416 struct tc_unflushed_batch_token
*tc_token
);
1419 void si_init_screen_get_functions(struct si_screen
*sscreen
);
1422 void si_flush_gfx_cs(struct si_context
*ctx
, unsigned flags
, struct pipe_fence_handle
**fence
);
1423 void si_allocate_gds(struct si_context
*ctx
);
1424 void si_set_tracked_regs_to_clear_state(struct si_context
*ctx
);
1425 void si_begin_new_gfx_cs(struct si_context
*ctx
, bool first_cs
);
1426 void si_need_gfx_cs_space(struct si_context
*ctx
);
1427 void si_unref_sdma_uploads(struct si_context
*sctx
);
1430 void si_gpu_load_kill_thread(struct si_screen
*sscreen
);
1431 uint64_t si_begin_counter(struct si_screen
*sscreen
, unsigned type
);
1432 unsigned si_end_counter(struct si_screen
*sscreen
, unsigned type
, uint64_t begin
);
1435 void si_emit_initial_compute_regs(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
);
1436 void si_init_compute_functions(struct si_context
*sctx
);
1438 /* si_compute_prim_discard.c */
1439 enum si_prim_discard_outcome
1441 SI_PRIM_DISCARD_ENABLED
,
1442 SI_PRIM_DISCARD_DISABLED
,
1443 SI_PRIM_DISCARD_DRAW_SPLIT
,
1446 void si_build_prim_discard_compute_shader(struct si_shader_context
*ctx
);
1447 enum si_prim_discard_outcome
1448 si_prepare_prim_discard_or_split_draw(struct si_context
*sctx
, const struct pipe_draw_info
*info
,
1449 bool primitive_restart
);
1450 void si_compute_signal_gfx(struct si_context
*sctx
);
1451 void si_dispatch_prim_discard_cs_and_draw(struct si_context
*sctx
,
1452 const struct pipe_draw_info
*info
, unsigned index_size
,
1453 unsigned base_vertex
, uint64_t input_indexbuf_va
,
1454 unsigned input_indexbuf_max_elements
);
1455 void si_initialize_prim_discard_tunables(struct si_screen
*sscreen
, bool is_aux_context
,
1456 unsigned *prim_discard_vertex_count_threshold
,
1457 unsigned *index_ring_size_per_ib
);
1460 void si_init_compiler(struct si_screen
*sscreen
, struct ac_llvm_compiler
*compiler
);
1462 /* si_perfcounters.c */
1463 void si_init_perfcounters(struct si_screen
*screen
);
1464 void si_destroy_perfcounters(struct si_screen
*screen
);
1467 void si_init_screen_query_functions(struct si_screen
*sscreen
);
1468 void si_init_query_functions(struct si_context
*sctx
);
1469 void si_suspend_queries(struct si_context
*sctx
);
1470 void si_resume_queries(struct si_context
*sctx
);
1472 /* si_shaderlib_tgsi.c */
1473 void *si_get_blitter_vs(struct si_context
*sctx
, enum blitter_attrib_type type
,
1474 unsigned num_layers
);
1475 void *si_create_fixed_func_tcs(struct si_context
*sctx
);
1476 void *si_create_dma_compute_shader(struct pipe_context
*ctx
, unsigned num_dwords_per_thread
,
1477 bool dst_stream_cache_policy
, bool is_copy
);
1478 void *si_create_copy_image_compute_shader(struct pipe_context
*ctx
);
1479 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context
*ctx
);
1480 void *si_create_dcc_decompress_cs(struct pipe_context
*ctx
);
1481 void *si_clear_render_target_shader(struct pipe_context
*ctx
);
1482 void *si_clear_render_target_shader_1d_array(struct pipe_context
*ctx
);
1483 void *si_clear_12bytes_buffer_shader(struct pipe_context
*ctx
);
1484 void *si_create_dcc_retile_cs(struct pipe_context
*ctx
);
1485 void *si_create_fmask_expand_cs(struct pipe_context
*ctx
, unsigned num_samples
, bool is_array
);
1486 void *si_create_query_result_cs(struct si_context
*sctx
);
1487 void *gfx10_create_sh_query_result_cs(struct si_context
*sctx
);
1490 void gfx10_init_query(struct si_context
*sctx
);
1491 void gfx10_destroy_query(struct si_context
*sctx
);
1494 void si_test_dma(struct si_screen
*sscreen
);
1496 /* si_test_clearbuffer.c */
1497 void si_test_dma_perf(struct si_screen
*sscreen
);
1500 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
1501 const struct pipe_video_codec
*templ
);
1503 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
1504 const struct pipe_video_buffer
*tmpl
);
1507 void si_update_ngg_small_prim_precision(struct si_context
*ctx
);
1508 void si_get_small_prim_cull_info(struct si_context
*sctx
, struct si_small_prim_cull_info
*out
);
1509 void si_update_vs_viewport_state(struct si_context
*ctx
);
1510 void si_init_viewport_functions(struct si_context
*ctx
);
1513 bool si_prepare_for_dma_blit(struct si_context
*sctx
, struct si_texture
*dst
, unsigned dst_level
,
1514 unsigned dstx
, unsigned dsty
, unsigned dstz
, struct si_texture
*src
,
1515 unsigned src_level
, const struct pipe_box
*src_box
);
1516 void si_eliminate_fast_color_clear(struct si_context
*sctx
, struct si_texture
*tex
,
1518 void si_texture_discard_cmask(struct si_screen
*sscreen
, struct si_texture
*tex
);
1519 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
, struct pipe_resource
*texture
);
1520 void si_print_texture_info(struct si_screen
*sscreen
, struct si_texture
*tex
,
1521 struct u_log_context
*log
);
1522 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1523 const struct pipe_resource
*templ
);
1524 bool vi_dcc_formats_compatible(struct si_screen
*sscreen
, enum pipe_format format1
,
1525 enum pipe_format format2
);
1526 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
, unsigned level
,
1527 enum pipe_format view_format
);
1528 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
, struct pipe_resource
*tex
,
1529 unsigned level
, enum pipe_format view_format
);
1530 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1531 struct pipe_resource
*texture
,
1532 const struct pipe_surface
*templ
, unsigned width0
,
1533 unsigned height0
, unsigned width
, unsigned height
);
1534 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
1535 void vi_separate_dcc_try_enable(struct si_context
*sctx
, struct si_texture
*tex
);
1536 void vi_separate_dcc_start_query(struct si_context
*sctx
, struct si_texture
*tex
);
1537 void vi_separate_dcc_stop_query(struct si_context
*sctx
, struct si_texture
*tex
);
1538 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
, struct si_texture
*tex
);
1539 bool si_texture_disable_dcc(struct si_context
*sctx
, struct si_texture
*tex
);
1540 void si_init_screen_texture_functions(struct si_screen
*sscreen
);
1541 void si_init_context_texture_functions(struct si_context
*sctx
);
1547 static inline struct si_resource
*si_resource(struct pipe_resource
*r
)
1549 return (struct si_resource
*)r
;
1552 static inline void si_resource_reference(struct si_resource
**ptr
, struct si_resource
*res
)
1554 pipe_resource_reference((struct pipe_resource
**)ptr
, (struct pipe_resource
*)res
);
1557 static inline void si_texture_reference(struct si_texture
**ptr
, struct si_texture
*res
)
1559 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->buffer
.b
.b
);
1563 si_shader_selector_reference(struct si_context
*sctx
, /* sctx can optionally be NULL */
1564 struct si_shader_selector
**dst
, struct si_shader_selector
*src
)
1569 struct si_screen
*sscreen
= src
? src
->screen
: (*dst
)->screen
;
1570 util_shader_reference(&sctx
->b
, &sscreen
->live_shader_cache
, (void **)dst
, src
);
1573 static inline bool vi_dcc_enabled(struct si_texture
*tex
, unsigned level
)
1575 return tex
->surface
.dcc_offset
&& level
< tex
->surface
.num_dcc_levels
;
1578 static inline unsigned si_tile_mode_index(struct si_texture
*tex
, unsigned level
, bool stencil
)
1581 return tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
1583 return tex
->surface
.u
.legacy
.tiling_index
[level
];
1586 static inline unsigned si_get_minimum_num_gfx_cs_dwords(struct si_context
*sctx
)
1588 /* Don't count the needed CS space exactly and just use an upper bound.
1590 * Also reserve space for stopping queries at the end of IB, because
1591 * the number of active queries is unlimited in theory.
1593 return 2048 + sctx
->num_cs_dw_queries_suspend
;
1596 static inline void si_context_add_resource_size(struct si_context
*sctx
, struct pipe_resource
*r
)
1599 /* Add memory usage for need_gfx_cs_space */
1600 sctx
->vram
+= si_resource(r
)->vram_usage
;
1601 sctx
->gtt
+= si_resource(r
)->gart_usage
;
1605 static inline void si_invalidate_draw_sh_constants(struct si_context
*sctx
)
1607 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
1608 sctx
->last_instance_count
= SI_INSTANCE_COUNT_UNKNOWN
;
1611 static inline unsigned si_get_atom_bit(struct si_context
*sctx
, struct si_atom
*atom
)
1613 return 1 << (atom
- sctx
->atoms
.array
);
1616 static inline void si_set_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
, bool dirty
)
1618 unsigned bit
= si_get_atom_bit(sctx
, atom
);
1621 sctx
->dirty_atoms
|= bit
;
1623 sctx
->dirty_atoms
&= ~bit
;
1626 static inline bool si_is_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1628 return (sctx
->dirty_atoms
& si_get_atom_bit(sctx
, atom
)) != 0;
1631 static inline void si_mark_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1633 si_set_atom_dirty(sctx
, atom
, true);
1636 static inline struct si_shader_ctx_state
*si_get_vs(struct si_context
*sctx
)
1638 if (sctx
->gs_shader
.cso
)
1639 return &sctx
->gs_shader
;
1640 if (sctx
->tes_shader
.cso
)
1641 return &sctx
->tes_shader
;
1643 return &sctx
->vs_shader
;
1646 static inline struct si_shader_info
*si_get_vs_info(struct si_context
*sctx
)
1648 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1650 return vs
->cso
? &vs
->cso
->info
: NULL
;
1653 static inline struct si_shader
*si_get_vs_state(struct si_context
*sctx
)
1655 if (sctx
->gs_shader
.cso
&& sctx
->gs_shader
.current
&& !sctx
->gs_shader
.current
->key
.as_ngg
)
1656 return sctx
->gs_shader
.cso
->gs_copy_shader
;
1658 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1659 return vs
->current
? vs
->current
: NULL
;
1662 static inline bool si_can_dump_shader(struct si_screen
*sscreen
, gl_shader_stage stage
)
1664 return sscreen
->debug_flags
& (1 << stage
);
1667 static inline bool si_get_strmout_en(struct si_context
*sctx
)
1669 return sctx
->streamout
.streamout_enabled
|| sctx
->streamout
.prims_gen_query_enabled
;
1672 static inline unsigned si_optimal_tcc_alignment(struct si_context
*sctx
, unsigned upload_size
)
1674 unsigned alignment
, tcc_cache_line_size
;
1676 /* If the upload size is less than the cache line size (e.g. 16, 32),
1677 * the whole thing will fit into a cache line if we align it to its size.
1678 * The idea is that multiple small uploads can share a cache line.
1679 * If the upload size is greater, align it to the cache line size.
1681 alignment
= util_next_power_of_two(upload_size
);
1682 tcc_cache_line_size
= sctx
->screen
->info
.tcc_cache_line_size
;
1683 return MIN2(alignment
, tcc_cache_line_size
);
1686 static inline void si_saved_cs_reference(struct si_saved_cs
**dst
, struct si_saved_cs
*src
)
1688 if (pipe_reference(&(*dst
)->reference
, &src
->reference
))
1689 si_destroy_saved_cs(*dst
);
1694 static inline void si_make_CB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1695 bool shaders_read_metadata
, bool dcc_pipe_aligned
)
1697 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
| SI_CONTEXT_INV_VCACHE
;
1699 if (sctx
->chip_class
>= GFX10
) {
1700 if (sctx
->screen
->info
.tcc_harvested
)
1701 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1702 else if (shaders_read_metadata
)
1703 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1704 } else if (sctx
->chip_class
== GFX9
) {
1705 /* Single-sample color is coherent with shaders on GFX9, but
1706 * L2 metadata must be flushed if shaders read metadata.
1709 if (num_samples
>= 2 || (shaders_read_metadata
&& !dcc_pipe_aligned
))
1710 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1711 else if (shaders_read_metadata
)
1712 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1715 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1719 static inline void si_make_DB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1720 bool include_stencil
, bool shaders_read_metadata
)
1722 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB
| SI_CONTEXT_INV_VCACHE
;
1724 if (sctx
->chip_class
>= GFX10
) {
1725 if (sctx
->screen
->info
.tcc_harvested
)
1726 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1727 else if (shaders_read_metadata
)
1728 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1729 } else if (sctx
->chip_class
== GFX9
) {
1730 /* Single-sample depth (not stencil) is coherent with shaders
1731 * on GFX9, but L2 metadata must be flushed if shaders read
1734 if (num_samples
>= 2 || include_stencil
)
1735 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1736 else if (shaders_read_metadata
)
1737 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1740 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1744 static inline bool si_can_sample_zs(struct si_texture
*tex
, bool stencil_sampler
)
1746 return (stencil_sampler
&& tex
->can_sample_s
) || (!stencil_sampler
&& tex
->can_sample_z
);
1749 static inline bool si_htile_enabled(struct si_texture
*tex
, unsigned level
, unsigned zs_mask
)
1751 if (zs_mask
== PIPE_MASK_S
&& tex
->htile_stencil_disabled
)
1754 return tex
->surface
.htile_offset
&& level
== 0;
1757 static inline bool vi_tc_compat_htile_enabled(struct si_texture
*tex
, unsigned level
,
1760 assert(!tex
->tc_compatible_htile
|| tex
->surface
.htile_offset
);
1761 return tex
->tc_compatible_htile
&& si_htile_enabled(tex
, level
, zs_mask
);
1764 static inline unsigned si_get_ps_iter_samples(struct si_context
*sctx
)
1766 if (sctx
->ps_uses_fbfetch
)
1767 return sctx
->framebuffer
.nr_color_samples
;
1769 return MIN2(sctx
->ps_iter_samples
, sctx
->framebuffer
.nr_color_samples
);
1772 static inline unsigned si_get_total_colormask(struct si_context
*sctx
)
1774 if (sctx
->queued
.named
.rasterizer
->rasterizer_discard
)
1777 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1781 unsigned colormask
=
1782 sctx
->framebuffer
.colorbuf_enabled_4bit
& sctx
->queued
.named
.blend
->cb_target_mask
;
1784 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
1785 colormask
&= ps
->colors_written_4bit
;
1786 else if (!ps
->colors_written_4bit
)
1787 colormask
= 0; /* color0 writes all cbufs, but it's not written */
1792 #define UTIL_ALL_PRIM_LINE_MODES \
1793 ((1 << PIPE_PRIM_LINES) | (1 << PIPE_PRIM_LINE_LOOP) | (1 << PIPE_PRIM_LINE_STRIP) | \
1794 (1 << PIPE_PRIM_LINES_ADJACENCY) | (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1796 static inline bool util_prim_is_lines(unsigned prim
)
1798 return ((1 << prim
) & UTIL_ALL_PRIM_LINE_MODES
) != 0;
1801 static inline bool util_prim_is_points_or_lines(unsigned prim
)
1803 return ((1 << prim
) & (UTIL_ALL_PRIM_LINE_MODES
| (1 << PIPE_PRIM_POINTS
))) != 0;
1806 static inline bool util_rast_prim_is_triangles(unsigned prim
)
1808 return ((1 << prim
) &
1809 ((1 << PIPE_PRIM_TRIANGLES
) | (1 << PIPE_PRIM_TRIANGLE_STRIP
) |
1810 (1 << PIPE_PRIM_TRIANGLE_FAN
) | (1 << PIPE_PRIM_QUADS
) | (1 << PIPE_PRIM_QUAD_STRIP
) |
1811 (1 << PIPE_PRIM_POLYGON
) | (1 << PIPE_PRIM_TRIANGLES_ADJACENCY
) |
1812 (1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
)));
1816 * Return true if there is enough memory in VRAM and GTT for the buffers
1819 * \param vram VRAM memory size not added to the buffer list yet
1820 * \param gtt GTT memory size not added to the buffer list yet
1822 static inline bool radeon_cs_memory_below_limit(struct si_screen
*screen
, struct radeon_cmdbuf
*cs
,
1823 uint64_t vram
, uint64_t gtt
)
1825 vram
+= cs
->used_vram
;
1826 gtt
+= cs
->used_gart
;
1828 /* Anything that goes above the VRAM size should go to GTT. */
1829 if (vram
> screen
->info
.vram_size
)
1830 gtt
+= vram
- screen
->info
.vram_size
;
1832 /* Now we just need to check if we have enough GTT. */
1833 return gtt
< screen
->info
.gart_size
* 0.7;
1837 * Add a buffer to the buffer list for the given command stream (CS).
1839 * All buffers used by a CS must be added to the list. This tells the kernel
1840 * driver which buffers are used by GPU commands. Other buffers can
1841 * be swapped out (not accessible) during execution.
1843 * The buffer list becomes empty after every context flush and must be
1846 static inline void radeon_add_to_buffer_list(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
,
1847 struct si_resource
*bo
, enum radeon_bo_usage usage
,
1848 enum radeon_bo_priority priority
)
1851 sctx
->ws
->cs_add_buffer(cs
, bo
->buf
, (enum radeon_bo_usage
)(usage
| RADEON_USAGE_SYNCHRONIZED
),
1852 bo
->domains
, priority
);
1856 * Same as above, but also checks memory usage and flushes the context
1859 * When this SHOULD NOT be used:
1861 * - if si_context_add_resource_size has been called for the buffer
1862 * followed by *_need_cs_space for checking the memory usage
1864 * - if si_need_dma_space has been called for the buffer
1866 * - when emitting state packets and draw packets (because preceding packets
1867 * can't be re-emitted at that point)
1869 * - if shader resource "enabled_mask" is not up-to-date or there is
1870 * a different constraint disallowing a context flush
1872 static inline void radeon_add_to_gfx_buffer_list_check_mem(struct si_context
*sctx
,
1873 struct si_resource
*bo
,
1874 enum radeon_bo_usage usage
,
1875 enum radeon_bo_priority priority
,
1879 !radeon_cs_memory_below_limit(sctx
->screen
, sctx
->gfx_cs
, sctx
->vram
+ bo
->vram_usage
,
1880 sctx
->gtt
+ bo
->gart_usage
))
1881 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1883 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, bo
, usage
, priority
);
1886 static inline bool si_compute_prim_discard_enabled(struct si_context
*sctx
)
1888 return sctx
->prim_discard_vertex_count_threshold
!= UINT_MAX
;
1891 static inline unsigned si_get_wave_size(struct si_screen
*sscreen
,
1892 gl_shader_stage stage
, bool ngg
, bool es
,
1893 bool gs_fast_launch
, bool prim_discard_cs
)
1895 if (stage
== MESA_SHADER_COMPUTE
)
1896 return sscreen
->compute_wave_size
;
1897 else if (stage
== MESA_SHADER_FRAGMENT
)
1898 return sscreen
->ps_wave_size
;
1899 else if (gs_fast_launch
)
1900 return 32; /* GS fast launch hangs with Wave64, so always use Wave32. */
1901 else if ((stage
== MESA_SHADER_VERTEX
&& prim_discard_cs
) || /* only Wave64 implemented */
1902 (stage
== MESA_SHADER_VERTEX
&& es
&& !ngg
) ||
1903 (stage
== MESA_SHADER_TESS_EVAL
&& es
&& !ngg
) ||
1904 (stage
== MESA_SHADER_GEOMETRY
&& !ngg
)) /* legacy GS only supports Wave64 */
1907 return sscreen
->ge_wave_size
;
1910 static inline unsigned si_get_shader_wave_size(struct si_shader
*shader
)
1912 return si_get_wave_size(shader
->selector
->screen
, shader
->selector
->info
.stage
,
1915 shader
->key
.opt
.ngg_culling
& SI_NGG_CULL_GS_FAST_LAUNCH_ALL
,
1916 shader
->key
.opt
.vs_as_prim_discard_cs
);
1919 #define PRINT_ERR(fmt, args...) \
1920 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)