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[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
34
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
37 #else
38 #define SI_BIG_ENDIAN 0
39 #endif
40
41 #define ATI_VENDOR_ID 0x1002
42
43 #define SI_NOT_QUERY 0xffffffff
44
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
56
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
61
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
69 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
70 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
71 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
72 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
73 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
74 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
75 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
76 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
77 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
78 * a CB or DB flush. */
79 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
80 /* Framebuffer caches. */
81 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
82 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
83 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
84 /* Engine synchronization. */
85 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
86 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
87 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
88 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
89 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
90
91 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
92 #define SI_PREFETCH_LS (1 << 1)
93 #define SI_PREFETCH_HS (1 << 2)
94 #define SI_PREFETCH_ES (1 << 3)
95 #define SI_PREFETCH_GS (1 << 4)
96 #define SI_PREFETCH_VS (1 << 5)
97 #define SI_PREFETCH_PS (1 << 6)
98
99 #define SI_MAX_BORDER_COLORS 4096
100 #define SI_MAX_VIEWPORTS 16
101 #define SIX_BITS 0x3F
102 #define SI_MAP_BUFFER_ALIGNMENT 64
103 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
104
105 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
106 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
107 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
108 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
109 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
110 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
111 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
112 #define SI_RESOURCE_FLAG_SO_FILLED_SIZE (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
113
114 /* Debug flags. */
115 enum {
116 /* Shader logging options: */
117 DBG_VS = PIPE_SHADER_VERTEX,
118 DBG_PS = PIPE_SHADER_FRAGMENT,
119 DBG_GS = PIPE_SHADER_GEOMETRY,
120 DBG_TCS = PIPE_SHADER_TESS_CTRL,
121 DBG_TES = PIPE_SHADER_TESS_EVAL,
122 DBG_CS = PIPE_SHADER_COMPUTE,
123 DBG_NO_IR,
124 DBG_NO_TGSI,
125 DBG_NO_ASM,
126 DBG_PREOPT_IR,
127
128 /* Shader compiler options the shader cache should be aware of: */
129 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
130 DBG_UNSAFE_MATH,
131 DBG_SI_SCHED,
132 DBG_GISEL,
133
134 /* Shader compiler options (with no effect on the shader cache): */
135 DBG_CHECK_IR,
136 DBG_NIR,
137 DBG_MONOLITHIC_SHADERS,
138 DBG_NO_OPT_VARIANT,
139
140 /* Information logging options: */
141 DBG_INFO,
142 DBG_TEX,
143 DBG_COMPUTE,
144 DBG_VM,
145
146 /* Driver options: */
147 DBG_FORCE_DMA,
148 DBG_NO_ASYNC_DMA,
149 DBG_NO_WC,
150 DBG_CHECK_VM,
151 DBG_RESERVE_VMID,
152 DBG_ZERO_VRAM,
153
154 /* 3D engine options: */
155 DBG_SWITCH_ON_EOP,
156 DBG_NO_OUT_OF_ORDER,
157 DBG_NO_DPBB,
158 DBG_NO_DFSM,
159 DBG_DPBB,
160 DBG_DFSM,
161 DBG_NO_HYPERZ,
162 DBG_NO_RB_PLUS,
163 DBG_NO_2D_TILING,
164 DBG_NO_TILING,
165 DBG_NO_DCC,
166 DBG_NO_DCC_CLEAR,
167 DBG_NO_DCC_FB,
168 DBG_NO_DCC_MSAA,
169 DBG_NO_FMASK,
170
171 /* Tests: */
172 DBG_TEST_DMA,
173 DBG_TEST_VMFAULT_CP,
174 DBG_TEST_VMFAULT_SDMA,
175 DBG_TEST_VMFAULT_SHADER,
176 DBG_TEST_DMA_PERF,
177 DBG_TEST_GDS,
178 DBG_TEST_GDS_MM,
179 DBG_TEST_GDS_OA_MM,
180 };
181
182 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
183 #define DBG(name) (1ull << DBG_##name)
184
185 enum si_cache_policy {
186 L2_BYPASS,
187 L2_STREAM, /* same as SLC=1 */
188 L2_LRU, /* same as SLC=0 */
189 };
190
191 enum si_coherency {
192 SI_COHERENCY_NONE, /* no cache flushes needed */
193 SI_COHERENCY_SHADER,
194 SI_COHERENCY_CB_META,
195 SI_COHERENCY_CP,
196 };
197
198 struct si_compute;
199 struct hash_table;
200 struct u_suballocator;
201
202 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
203 * at the moment.
204 */
205 struct r600_resource {
206 struct threaded_resource b;
207
208 /* Winsys objects. */
209 struct pb_buffer *buf;
210 uint64_t gpu_address;
211 /* Memory usage if the buffer placement is optimal. */
212 uint64_t vram_usage;
213 uint64_t gart_usage;
214
215 /* Resource properties. */
216 uint64_t bo_size;
217 unsigned bo_alignment;
218 enum radeon_bo_domain domains;
219 enum radeon_bo_flag flags;
220 unsigned bind_history;
221 int max_forced_staging_uploads;
222
223 /* The buffer range which is initialized (with a write transfer,
224 * streamout, DMA, or as a random access target). The rest of
225 * the buffer is considered invalid and can be mapped unsynchronized.
226 *
227 * This allows unsychronized mapping of a buffer range which hasn't
228 * been used yet. It's for applications which forget to use
229 * the unsynchronized map flag and expect the driver to figure it out.
230 */
231 struct util_range valid_buffer_range;
232
233 /* For buffers only. This indicates that a write operation has been
234 * performed by TC L2, but the cache hasn't been flushed.
235 * Any hw block which doesn't use or bypasses TC L2 should check this
236 * flag and flush the cache before using the buffer.
237 *
238 * For example, TC L2 must be flushed if a buffer which has been
239 * modified by a shader store instruction is about to be used as
240 * an index buffer. The reason is that VGT DMA index fetching doesn't
241 * use TC L2.
242 */
243 bool TC_L2_dirty;
244
245 /* Whether this resource is referenced by bindless handles. */
246 bool texture_handle_allocated;
247 bool image_handle_allocated;
248
249 /* Whether the resource has been exported via resource_get_handle. */
250 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
251 };
252
253 struct si_transfer {
254 struct threaded_transfer b;
255 struct r600_resource *staging;
256 unsigned offset;
257 };
258
259 struct si_texture {
260 struct r600_resource buffer;
261
262 struct radeon_surf surface;
263 uint64_t size;
264 struct si_texture *flushed_depth_texture;
265
266 /* Colorbuffer compression and fast clear. */
267 uint64_t fmask_offset;
268 uint64_t cmask_offset;
269 uint64_t cmask_base_address_reg;
270 struct r600_resource *cmask_buffer;
271 uint64_t dcc_offset; /* 0 = disabled */
272 unsigned cb_color_info; /* fast clear enable bit */
273 unsigned color_clear_value[2];
274 unsigned last_msaa_resolve_target_micro_mode;
275 unsigned num_level0_transfers;
276
277 /* Depth buffer compression and fast clear. */
278 uint64_t htile_offset;
279 float depth_clear_value;
280 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
281 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
282 enum pipe_format db_render_format:16;
283 uint8_t stencil_clear_value;
284 bool tc_compatible_htile:1;
285 bool depth_cleared:1; /* if it was cleared at least once */
286 bool stencil_cleared:1; /* if it was cleared at least once */
287 bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
288 bool is_depth:1;
289 bool db_compatible:1;
290 bool can_sample_z:1;
291 bool can_sample_s:1;
292
293 /* We need to track DCC dirtiness, because st/dri usually calls
294 * flush_resource twice per frame (not a bug) and we don't wanna
295 * decompress DCC twice. Also, the dirty tracking must be done even
296 * if DCC isn't used, because it's required by the DCC usage analysis
297 * for a possible future enablement.
298 */
299 bool separate_dcc_dirty:1;
300 /* Statistics gathering for the DCC enablement heuristic. */
301 bool dcc_gather_statistics:1;
302 /* Counter that should be non-zero if the texture is bound to a
303 * framebuffer.
304 */
305 unsigned framebuffers_bound;
306 /* Whether the texture is a displayable back buffer and needs DCC
307 * decompression, which is expensive. Therefore, it's enabled only
308 * if statistics suggest that it will pay off and it's allocated
309 * separately. It can't be bound as a sampler by apps. Limited to
310 * target == 2D and last_level == 0. If enabled, dcc_offset contains
311 * the absolute GPUVM address, not the relative one.
312 */
313 struct r600_resource *dcc_separate_buffer;
314 /* When DCC is temporarily disabled, the separate buffer is here. */
315 struct r600_resource *last_dcc_separate_buffer;
316 /* Estimate of how much this color buffer is written to in units of
317 * full-screen draws: ps_invocations / (width * height)
318 * Shader kills, late Z, and blending with trivial discards make it
319 * inaccurate (we need to count CB updates, not PS invocations).
320 */
321 unsigned ps_draw_ratio;
322 /* The number of clears since the last DCC usage analysis. */
323 unsigned num_slow_clears;
324 };
325
326 struct si_surface {
327 struct pipe_surface base;
328
329 /* These can vary with block-compressed textures. */
330 uint16_t width0;
331 uint16_t height0;
332
333 bool color_initialized:1;
334 bool depth_initialized:1;
335
336 /* Misc. color flags. */
337 bool color_is_int8:1;
338 bool color_is_int10:1;
339 bool dcc_incompatible:1;
340
341 /* Color registers. */
342 unsigned cb_color_info;
343 unsigned cb_color_view;
344 unsigned cb_color_attrib;
345 unsigned cb_color_attrib2; /* GFX9 and later */
346 unsigned cb_dcc_control; /* VI and later */
347 unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */
348 unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
349 unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
350 unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
351
352 /* DB registers. */
353 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
354 uint64_t db_stencil_base;
355 uint64_t db_htile_data_base;
356 unsigned db_depth_info;
357 unsigned db_z_info;
358 unsigned db_z_info2; /* GFX9+ */
359 unsigned db_depth_view;
360 unsigned db_depth_size;
361 unsigned db_depth_slice;
362 unsigned db_stencil_info;
363 unsigned db_stencil_info2; /* GFX9+ */
364 unsigned db_htile_surface;
365 };
366
367 struct si_mmio_counter {
368 unsigned busy;
369 unsigned idle;
370 };
371
372 union si_mmio_counters {
373 struct {
374 /* For global GPU load including SDMA. */
375 struct si_mmio_counter gpu;
376
377 /* GRBM_STATUS */
378 struct si_mmio_counter spi;
379 struct si_mmio_counter gui;
380 struct si_mmio_counter ta;
381 struct si_mmio_counter gds;
382 struct si_mmio_counter vgt;
383 struct si_mmio_counter ia;
384 struct si_mmio_counter sx;
385 struct si_mmio_counter wd;
386 struct si_mmio_counter bci;
387 struct si_mmio_counter sc;
388 struct si_mmio_counter pa;
389 struct si_mmio_counter db;
390 struct si_mmio_counter cp;
391 struct si_mmio_counter cb;
392
393 /* SRBM_STATUS2 */
394 struct si_mmio_counter sdma;
395
396 /* CP_STAT */
397 struct si_mmio_counter pfp;
398 struct si_mmio_counter meq;
399 struct si_mmio_counter me;
400 struct si_mmio_counter surf_sync;
401 struct si_mmio_counter cp_dma;
402 struct si_mmio_counter scratch_ram;
403 } named;
404 unsigned array[0];
405 };
406
407 struct si_memory_object {
408 struct pipe_memory_object b;
409 struct pb_buffer *buf;
410 uint32_t stride;
411 };
412
413 /* Saved CS data for debugging features. */
414 struct radeon_saved_cs {
415 uint32_t *ib;
416 unsigned num_dw;
417
418 struct radeon_bo_list_item *bo_list;
419 unsigned bo_count;
420 };
421
422 struct si_screen {
423 struct pipe_screen b;
424 struct radeon_winsys *ws;
425 struct disk_cache *disk_shader_cache;
426
427 struct radeon_info info;
428 uint64_t debug_flags;
429 char renderer_string[183];
430
431 unsigned pa_sc_raster_config;
432 unsigned pa_sc_raster_config_1;
433 unsigned se_tile_repeat;
434 unsigned gs_table_depth;
435 unsigned tess_offchip_block_dw_size;
436 unsigned tess_offchip_ring_size;
437 unsigned tess_factor_ring_size;
438 unsigned vgt_hs_offchip_param;
439 unsigned eqaa_force_coverage_samples;
440 unsigned eqaa_force_z_samples;
441 unsigned eqaa_force_color_samples;
442 bool has_clear_state;
443 bool has_distributed_tess;
444 bool has_draw_indirect_multi;
445 bool has_out_of_order_rast;
446 bool assume_no_z_fights;
447 bool commutative_blend_add;
448 bool clear_db_cache_before_clear;
449 bool has_msaa_sample_loc_bug;
450 bool has_ls_vgpr_init_bug;
451 bool has_dcc_constant_encode;
452 bool dpbb_allowed;
453 bool dfsm_allowed;
454 bool llvm_has_working_vgpr_indexing;
455
456 /* Whether shaders are monolithic (1-part) or separate (3-part). */
457 bool use_monolithic_shaders;
458 bool record_llvm_ir;
459 bool has_rbplus; /* if RB+ registers exist */
460 bool rbplus_allowed; /* if RB+ is allowed */
461 bool dcc_msaa_allowed;
462 bool cpdma_prefetch_writes_memory;
463
464 struct slab_parent_pool pool_transfers;
465
466 /* Texture filter settings. */
467 int force_aniso; /* -1 = disabled */
468
469 /* Auxiliary context. Mainly used to initialize resources.
470 * It must be locked prior to using and flushed before unlocking. */
471 struct pipe_context *aux_context;
472 mtx_t aux_context_lock;
473
474 /* This must be in the screen, because UE4 uses one context for
475 * compilation and another one for rendering.
476 */
477 unsigned num_compilations;
478 /* Along with ST_DEBUG=precompile, this should show if applications
479 * are loading shaders on demand. This is a monotonic counter.
480 */
481 unsigned num_shaders_created;
482 unsigned num_shader_cache_hits;
483
484 /* GPU load thread. */
485 mtx_t gpu_load_mutex;
486 thrd_t gpu_load_thread;
487 union si_mmio_counters mmio_counters;
488 volatile unsigned gpu_load_stop_thread; /* bool */
489
490 /* Performance counters. */
491 struct si_perfcounters *perfcounters;
492
493 /* If pipe_screen wants to recompute and re-emit the framebuffer,
494 * sampler, and image states of all contexts, it should atomically
495 * increment this.
496 *
497 * Each context will compare this with its own last known value of
498 * the counter before drawing and re-emit the states accordingly.
499 */
500 unsigned dirty_tex_counter;
501
502 /* Atomically increment this counter when an existing texture's
503 * metadata is enabled or disabled in a way that requires changing
504 * contexts' compressed texture binding masks.
505 */
506 unsigned compressed_colortex_counter;
507
508 struct {
509 /* Context flags to set so that all writes from earlier jobs
510 * in the CP are seen by L2 clients.
511 */
512 unsigned cp_to_L2;
513
514 /* Context flags to set so that all writes from earlier jobs
515 * that end in L2 are seen by CP.
516 */
517 unsigned L2_to_cp;
518 } barrier_flags;
519
520 mtx_t shader_parts_mutex;
521 struct si_shader_part *vs_prologs;
522 struct si_shader_part *tcs_epilogs;
523 struct si_shader_part *gs_prologs;
524 struct si_shader_part *ps_prologs;
525 struct si_shader_part *ps_epilogs;
526
527 /* Shader cache in memory.
528 *
529 * Design & limitations:
530 * - The shader cache is per screen (= per process), never saved to
531 * disk, and skips redundant shader compilations from TGSI to bytecode.
532 * - It can only be used with one-variant-per-shader support, in which
533 * case only the main (typically middle) part of shaders is cached.
534 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
535 * variants of VS and TES are cached, so LS and ES aren't.
536 * - GS and CS aren't cached, but it's certainly possible to cache
537 * those as well.
538 */
539 mtx_t shader_cache_mutex;
540 struct hash_table *shader_cache;
541
542 /* Shader compiler queue for multithreaded compilation. */
543 struct util_queue shader_compiler_queue;
544 /* Use at most 3 normal compiler threads on quadcore and better.
545 * Hyperthreaded CPUs report the number of threads, but we want
546 * the number of cores. We only need this many threads for shader-db. */
547 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
548
549 struct util_queue shader_compiler_queue_low_priority;
550 /* Use at most 2 low priority threads on quadcore and better.
551 * We want to minimize the impact on multithreaded Mesa. */
552 struct ac_llvm_compiler compiler_lowp[10];
553 };
554
555 struct si_blend_color {
556 struct pipe_blend_color state;
557 bool any_nonzeros;
558 };
559
560 struct si_sampler_view {
561 struct pipe_sampler_view base;
562 /* [0..7] = image descriptor
563 * [4..7] = buffer descriptor */
564 uint32_t state[8];
565 uint32_t fmask_state[8];
566 const struct legacy_surf_level *base_level_info;
567 ubyte base_level;
568 ubyte block_width;
569 bool is_stencil_sampler;
570 bool is_integer;
571 bool dcc_incompatible;
572 };
573
574 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
575
576 struct si_sampler_state {
577 #ifdef DEBUG
578 unsigned magic;
579 #endif
580 uint32_t val[4];
581 uint32_t integer_val[4];
582 uint32_t upgraded_depth_val[4];
583 };
584
585 struct si_cs_shader_state {
586 struct si_compute *program;
587 struct si_compute *emitted_program;
588 unsigned offset;
589 bool initialized;
590 bool uses_scratch;
591 };
592
593 struct si_samplers {
594 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
595 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
596
597 /* The i-th bit is set if that element is enabled (non-NULL resource). */
598 unsigned enabled_mask;
599 uint32_t needs_depth_decompress_mask;
600 uint32_t needs_color_decompress_mask;
601 };
602
603 struct si_images {
604 struct pipe_image_view views[SI_NUM_IMAGES];
605 uint32_t needs_color_decompress_mask;
606 unsigned enabled_mask;
607 };
608
609 struct si_framebuffer {
610 struct pipe_framebuffer_state state;
611 unsigned colorbuf_enabled_4bit;
612 unsigned spi_shader_col_format;
613 unsigned spi_shader_col_format_alpha;
614 unsigned spi_shader_col_format_blend;
615 unsigned spi_shader_col_format_blend_alpha;
616 ubyte nr_samples:5; /* at most 16xAA */
617 ubyte log_samples:3; /* at most 4 = 16xAA */
618 ubyte nr_color_samples; /* at most 8xAA */
619 ubyte compressed_cb_mask;
620 ubyte uncompressed_cb_mask;
621 ubyte color_is_int8;
622 ubyte color_is_int10;
623 ubyte dirty_cbufs;
624 ubyte dcc_overwrite_combiner_watermark;
625 bool dirty_zsbuf;
626 bool any_dst_linear;
627 bool CB_has_shader_readable_metadata;
628 bool DB_has_shader_readable_metadata;
629 };
630
631 enum si_quant_mode {
632 /* This is the list we want to support. */
633 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
634 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
635 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
636 };
637
638 struct si_signed_scissor {
639 int minx;
640 int miny;
641 int maxx;
642 int maxy;
643 enum si_quant_mode quant_mode;
644 };
645
646 struct si_scissors {
647 unsigned dirty_mask;
648 struct pipe_scissor_state states[SI_MAX_VIEWPORTS];
649 };
650
651 struct si_viewports {
652 unsigned dirty_mask;
653 unsigned depth_range_dirty_mask;
654 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
655 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
656 };
657
658 struct si_clip_state {
659 struct pipe_clip_state state;
660 bool any_nonzeros;
661 };
662
663 struct si_streamout_target {
664 struct pipe_stream_output_target b;
665
666 /* The buffer where BUFFER_FILLED_SIZE is stored. */
667 struct r600_resource *buf_filled_size;
668 unsigned buf_filled_size_offset;
669 bool buf_filled_size_valid;
670
671 unsigned stride_in_dw;
672 };
673
674 struct si_streamout {
675 bool begin_emitted;
676
677 unsigned enabled_mask;
678 unsigned num_targets;
679 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
680
681 unsigned append_bitmask;
682 bool suspended;
683
684 /* External state which comes from the vertex shader,
685 * it must be set explicitly when binding a shader. */
686 uint16_t *stride_in_dw;
687 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
688
689 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
690 unsigned hw_enabled_mask;
691
692 /* The state of VGT_STRMOUT_(CONFIG|EN). */
693 bool streamout_enabled;
694 bool prims_gen_query_enabled;
695 int num_prims_gen_queries;
696 };
697
698 /* A shader state consists of the shader selector, which is a constant state
699 * object shared by multiple contexts and shouldn't be modified, and
700 * the current shader variant selected for this context.
701 */
702 struct si_shader_ctx_state {
703 struct si_shader_selector *cso;
704 struct si_shader *current;
705 };
706
707 #define SI_NUM_VGT_PARAM_KEY_BITS 12
708 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
709
710 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
711 * Some fields are set by state-change calls, most are set by draw_vbo.
712 */
713 union si_vgt_param_key {
714 struct {
715 #ifdef PIPE_ARCH_LITTLE_ENDIAN
716 unsigned prim:4;
717 unsigned uses_instancing:1;
718 unsigned multi_instances_smaller_than_primgroup:1;
719 unsigned primitive_restart:1;
720 unsigned count_from_stream_output:1;
721 unsigned line_stipple_enabled:1;
722 unsigned uses_tess:1;
723 unsigned tess_uses_prim_id:1;
724 unsigned uses_gs:1;
725 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
726 #else /* PIPE_ARCH_BIG_ENDIAN */
727 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
728 unsigned uses_gs:1;
729 unsigned tess_uses_prim_id:1;
730 unsigned uses_tess:1;
731 unsigned line_stipple_enabled:1;
732 unsigned count_from_stream_output:1;
733 unsigned primitive_restart:1;
734 unsigned multi_instances_smaller_than_primgroup:1;
735 unsigned uses_instancing:1;
736 unsigned prim:4;
737 #endif
738 } u;
739 uint32_t index;
740 };
741
742 struct si_texture_handle
743 {
744 unsigned desc_slot;
745 bool desc_dirty;
746 struct pipe_sampler_view *view;
747 struct si_sampler_state sstate;
748 };
749
750 struct si_image_handle
751 {
752 unsigned desc_slot;
753 bool desc_dirty;
754 struct pipe_image_view view;
755 };
756
757 struct si_saved_cs {
758 struct pipe_reference reference;
759 struct si_context *ctx;
760 struct radeon_saved_cs gfx;
761 struct r600_resource *trace_buf;
762 unsigned trace_id;
763
764 unsigned gfx_last_dw;
765 bool flushed;
766 int64_t time_flush;
767 };
768
769 struct si_context {
770 struct pipe_context b; /* base class */
771
772 enum radeon_family family;
773 enum chip_class chip_class;
774
775 struct radeon_winsys *ws;
776 struct radeon_winsys_ctx *ctx;
777 struct radeon_cmdbuf *gfx_cs;
778 struct radeon_cmdbuf *dma_cs;
779 struct pipe_fence_handle *last_gfx_fence;
780 struct pipe_fence_handle *last_sdma_fence;
781 struct r600_resource *eop_bug_scratch;
782 struct u_upload_mgr *cached_gtt_allocator;
783 struct threaded_context *tc;
784 struct u_suballocator *allocator_zeroed_memory;
785 struct slab_child_pool pool_transfers;
786 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
787 struct pipe_device_reset_callback device_reset_callback;
788 struct u_log_context *log;
789 void *query_result_shader;
790 struct blitter_context *blitter;
791 void *custom_dsa_flush;
792 void *custom_blend_resolve;
793 void *custom_blend_fmask_decompress;
794 void *custom_blend_eliminate_fastclear;
795 void *custom_blend_dcc_decompress;
796 void *vs_blit_pos;
797 void *vs_blit_pos_layered;
798 void *vs_blit_color;
799 void *vs_blit_color_layered;
800 void *vs_blit_texcoord;
801 void *cs_clear_buffer;
802 void *cs_copy_buffer;
803 struct si_screen *screen;
804 struct pipe_debug_callback debug;
805 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
806 struct si_shader_ctx_state fixed_func_tcs_shader;
807 struct r600_resource *wait_mem_scratch;
808 unsigned wait_mem_number;
809 uint16_t prefetch_L2_mask;
810
811 bool gfx_flush_in_progress:1;
812 bool gfx_last_ib_is_busy:1;
813 bool compute_is_busy:1;
814
815 unsigned num_gfx_cs_flushes;
816 unsigned initial_gfx_cs_size;
817 unsigned gpu_reset_counter;
818 unsigned last_dirty_tex_counter;
819 unsigned last_compressed_colortex_counter;
820 unsigned last_num_draw_calls;
821 unsigned flags; /* flush flags */
822 /* Current unaccounted memory usage. */
823 uint64_t vram;
824 uint64_t gtt;
825
826 /* Atoms (direct states). */
827 union si_state_atoms atoms;
828 unsigned dirty_atoms; /* mask */
829 /* PM4 states (precomputed immutable states) */
830 unsigned dirty_states;
831 union si_state queued;
832 union si_state emitted;
833
834 /* Atom declarations. */
835 struct si_framebuffer framebuffer;
836 unsigned sample_locs_num_samples;
837 uint16_t sample_mask;
838 unsigned last_cb_target_mask;
839 struct si_blend_color blend_color;
840 struct si_clip_state clip_state;
841 struct si_shader_data shader_pointers;
842 struct si_stencil_ref stencil_ref;
843 struct si_scissors scissors;
844 struct si_streamout streamout;
845 struct si_viewports viewports;
846 unsigned num_window_rectangles;
847 bool window_rectangles_include;
848 struct pipe_scissor_state window_rectangles[4];
849
850 /* Precomputed states. */
851 struct si_pm4_state *init_config;
852 struct si_pm4_state *init_config_gs_rings;
853 bool init_config_has_vgt_flush;
854 struct si_pm4_state *vgt_shader_config[4];
855
856 /* shaders */
857 struct si_shader_ctx_state ps_shader;
858 struct si_shader_ctx_state gs_shader;
859 struct si_shader_ctx_state vs_shader;
860 struct si_shader_ctx_state tcs_shader;
861 struct si_shader_ctx_state tes_shader;
862 struct si_cs_shader_state cs_shader_state;
863
864 /* shader information */
865 struct si_vertex_elements *vertex_elements;
866 unsigned sprite_coord_enable;
867 unsigned cs_max_waves_per_sh;
868 bool flatshade;
869 bool do_update_shaders;
870
871 /* vertex buffer descriptors */
872 uint32_t *vb_descriptors_gpu_list;
873 struct r600_resource *vb_descriptors_buffer;
874 unsigned vb_descriptors_offset;
875
876 /* shader descriptors */
877 struct si_descriptors descriptors[SI_NUM_DESCS];
878 unsigned descriptors_dirty;
879 unsigned shader_pointers_dirty;
880 unsigned shader_needs_decompress_mask;
881 struct si_buffer_resources rw_buffers;
882 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
883 struct si_samplers samplers[SI_NUM_SHADERS];
884 struct si_images images[SI_NUM_SHADERS];
885
886 /* other shader resources */
887 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
888 struct pipe_resource *esgs_ring;
889 struct pipe_resource *gsvs_ring;
890 struct pipe_resource *tess_rings;
891 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
892 struct r600_resource *border_color_buffer;
893 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
894 unsigned border_color_count;
895 unsigned num_vs_blit_sgprs;
896 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
897 uint32_t cs_user_data[4];
898
899 /* Vertex and index buffers. */
900 bool vertex_buffers_dirty;
901 bool vertex_buffer_pointer_dirty;
902 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
903
904 /* MSAA config state. */
905 int ps_iter_samples;
906 bool ps_uses_fbfetch;
907 bool smoothing_enabled;
908
909 /* DB render state. */
910 unsigned ps_db_shader_control;
911 unsigned dbcb_copy_sample;
912 bool dbcb_depth_copy_enabled:1;
913 bool dbcb_stencil_copy_enabled:1;
914 bool db_flush_depth_inplace:1;
915 bool db_flush_stencil_inplace:1;
916 bool db_depth_clear:1;
917 bool db_depth_disable_expclear:1;
918 bool db_stencil_clear:1;
919 bool db_stencil_disable_expclear:1;
920 bool occlusion_queries_disabled:1;
921 bool generate_mipmap_for_depth:1;
922
923 /* Emitted draw state. */
924 bool gs_tri_strip_adj_fix:1;
925 bool ls_vgpr_fix:1;
926 int last_index_size;
927 int last_base_vertex;
928 int last_start_instance;
929 int last_instance_count;
930 int last_drawid;
931 int last_sh_base_reg;
932 int last_primitive_restart_en;
933 int last_restart_index;
934 int last_prim;
935 int last_multi_vgt_param;
936 int last_rast_prim;
937 unsigned last_sc_line_stipple;
938 unsigned current_vs_state;
939 unsigned last_vs_state;
940 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
941
942 /* Scratch buffer */
943 struct r600_resource *scratch_buffer;
944 unsigned scratch_waves;
945 unsigned spi_tmpring_size;
946
947 struct r600_resource *compute_scratch_buffer;
948
949 /* Emitted derived tessellation state. */
950 /* Local shader (VS), or HS if LS-HS are merged. */
951 struct si_shader *last_ls;
952 struct si_shader_selector *last_tcs;
953 int last_num_tcs_input_cp;
954 int last_tes_sh_base;
955 bool last_tess_uses_primid;
956 unsigned last_num_patches;
957 int last_ls_hs_config;
958
959 /* Debug state. */
960 bool is_debug;
961 struct si_saved_cs *current_saved_cs;
962 uint64_t dmesg_timestamp;
963 unsigned apitrace_call_number;
964
965 /* Other state */
966 bool need_check_render_feedback;
967 bool decompression_enabled;
968 bool dpbb_force_off;
969 bool vs_writes_viewport_index;
970 bool vs_disables_clipping_viewport;
971
972 /* Precomputed IA_MULTI_VGT_PARAM */
973 union si_vgt_param_key ia_multi_vgt_param_key;
974 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
975
976 /* Bindless descriptors. */
977 struct si_descriptors bindless_descriptors;
978 struct util_idalloc bindless_used_slots;
979 unsigned num_bindless_descriptors;
980 bool bindless_descriptors_dirty;
981 bool graphics_bindless_pointer_dirty;
982 bool compute_bindless_pointer_dirty;
983
984 /* Allocated bindless handles */
985 struct hash_table *tex_handles;
986 struct hash_table *img_handles;
987
988 /* Resident bindless handles */
989 struct util_dynarray resident_tex_handles;
990 struct util_dynarray resident_img_handles;
991
992 /* Resident bindless handles which need decompression */
993 struct util_dynarray resident_tex_needs_color_decompress;
994 struct util_dynarray resident_img_needs_color_decompress;
995 struct util_dynarray resident_tex_needs_depth_decompress;
996
997 /* Bindless state */
998 bool uses_bindless_samplers;
999 bool uses_bindless_images;
1000
1001 /* MSAA sample locations.
1002 * The first index is the sample index.
1003 * The second index is the coordinate: X, Y. */
1004 struct {
1005 float x1[1][2];
1006 float x2[2][2];
1007 float x4[4][2];
1008 float x8[8][2];
1009 float x16[16][2];
1010 } sample_positions;
1011 struct pipe_resource *sample_pos_buffer;
1012
1013 /* Misc stats. */
1014 unsigned num_draw_calls;
1015 unsigned num_decompress_calls;
1016 unsigned num_mrt_draw_calls;
1017 unsigned num_prim_restart_calls;
1018 unsigned num_spill_draw_calls;
1019 unsigned num_compute_calls;
1020 unsigned num_spill_compute_calls;
1021 unsigned num_dma_calls;
1022 unsigned num_cp_dma_calls;
1023 unsigned num_vs_flushes;
1024 unsigned num_ps_flushes;
1025 unsigned num_cs_flushes;
1026 unsigned num_cb_cache_flushes;
1027 unsigned num_db_cache_flushes;
1028 unsigned num_L2_invalidates;
1029 unsigned num_L2_writebacks;
1030 unsigned num_resident_handles;
1031 uint64_t num_alloc_tex_transfer_bytes;
1032 unsigned last_tex_ps_draw_ratio; /* for query */
1033 unsigned context_roll_counter;
1034
1035 /* Queries. */
1036 /* Maintain the list of active queries for pausing between IBs. */
1037 int num_occlusion_queries;
1038 int num_perfect_occlusion_queries;
1039 struct list_head active_queries;
1040 unsigned num_cs_dw_queries_suspend;
1041
1042 /* Render condition. */
1043 struct pipe_query *render_cond;
1044 unsigned render_cond_mode;
1045 bool render_cond_invert;
1046 bool render_cond_force_off; /* for u_blitter */
1047
1048 /* Statistics gathering for the DCC enablement heuristic. It can't be
1049 * in si_texture because si_texture can be shared by multiple
1050 * contexts. This is for back buffers only. We shouldn't get too many
1051 * of those.
1052 *
1053 * X11 DRI3 rotates among a finite set of back buffers. They should
1054 * all fit in this array. If they don't, separate DCC might never be
1055 * enabled by DCC stat gathering.
1056 */
1057 struct {
1058 struct si_texture *tex;
1059 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1060 struct pipe_query *ps_stats[3];
1061 /* If all slots are used and another slot is needed,
1062 * the least recently used slot is evicted based on this. */
1063 int64_t last_use_timestamp;
1064 bool query_active;
1065 } dcc_stats[5];
1066
1067 /* Copy one resource to another using async DMA. */
1068 void (*dma_copy)(struct pipe_context *ctx,
1069 struct pipe_resource *dst,
1070 unsigned dst_level,
1071 unsigned dst_x, unsigned dst_y, unsigned dst_z,
1072 struct pipe_resource *src,
1073 unsigned src_level,
1074 const struct pipe_box *src_box);
1075
1076 struct si_tracked_regs tracked_regs;
1077 };
1078
1079 /* cik_sdma.c */
1080 void cik_init_sdma_functions(struct si_context *sctx);
1081
1082 /* si_blit.c */
1083 enum si_blitter_op /* bitmask */
1084 {
1085 SI_SAVE_TEXTURES = 1,
1086 SI_SAVE_FRAMEBUFFER = 2,
1087 SI_SAVE_FRAGMENT_STATE = 4,
1088 SI_DISABLE_RENDER_COND = 8,
1089 };
1090
1091 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1092 void si_blitter_end(struct si_context *sctx);
1093 void si_init_blit_functions(struct si_context *sctx);
1094 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1095 void si_resource_copy_region(struct pipe_context *ctx,
1096 struct pipe_resource *dst,
1097 unsigned dst_level,
1098 unsigned dstx, unsigned dsty, unsigned dstz,
1099 struct pipe_resource *src,
1100 unsigned src_level,
1101 const struct pipe_box *src_box);
1102 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1103 void si_blit_decompress_depth(struct pipe_context *ctx,
1104 struct si_texture *texture,
1105 struct si_texture *staging,
1106 unsigned first_level, unsigned last_level,
1107 unsigned first_layer, unsigned last_layer,
1108 unsigned first_sample, unsigned last_sample);
1109
1110 /* si_buffer.c */
1111 bool si_rings_is_buffer_referenced(struct si_context *sctx,
1112 struct pb_buffer *buf,
1113 enum radeon_bo_usage usage);
1114 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
1115 struct r600_resource *resource,
1116 unsigned usage);
1117 void si_init_resource_fields(struct si_screen *sscreen,
1118 struct r600_resource *res,
1119 uint64_t size, unsigned alignment);
1120 bool si_alloc_resource(struct si_screen *sscreen,
1121 struct r600_resource *res);
1122 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
1123 unsigned flags, unsigned usage,
1124 unsigned size, unsigned alignment);
1125 struct r600_resource *si_aligned_buffer_create(struct pipe_screen *screen,
1126 unsigned flags, unsigned usage,
1127 unsigned size, unsigned alignment);
1128 void si_replace_buffer_storage(struct pipe_context *ctx,
1129 struct pipe_resource *dst,
1130 struct pipe_resource *src);
1131 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1132 void si_init_buffer_functions(struct si_context *sctx);
1133
1134 /* si_clear.c */
1135 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1136 bool vi_alpha_is_on_msb(enum pipe_format format);
1137 void vi_dcc_clear_level(struct si_context *sctx,
1138 struct si_texture *tex,
1139 unsigned level, unsigned clear_value);
1140 void si_init_clear_functions(struct si_context *sctx);
1141
1142 /* si_compute_blit.c */
1143 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1144 enum si_cache_policy cache_policy);
1145 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1146 uint64_t offset, uint64_t size, uint32_t *clear_value,
1147 uint32_t clear_value_size, enum si_coherency coher);
1148 void si_copy_buffer(struct si_context *sctx,
1149 struct pipe_resource *dst, struct pipe_resource *src,
1150 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1151 void si_init_compute_blit_functions(struct si_context *sctx);
1152
1153 /* si_cp_dma.c */
1154 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1155 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1156 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1157 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1158 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1159 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1160 SI_CPDMA_SKIP_SYNC_AFTER | \
1161 SI_CPDMA_SKIP_SYNC_BEFORE | \
1162 SI_CPDMA_SKIP_GFX_SYNC | \
1163 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1164
1165 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1166 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1167 struct pipe_resource *dst, uint64_t offset,
1168 uint64_t size, unsigned value, unsigned user_flags,
1169 enum si_coherency coher, enum si_cache_policy cache_policy);
1170 void si_cp_dma_copy_buffer(struct si_context *sctx,
1171 struct pipe_resource *dst, struct pipe_resource *src,
1172 uint64_t dst_offset, uint64_t src_offset, unsigned size,
1173 unsigned user_flags, enum si_coherency coher,
1174 enum si_cache_policy cache_policy);
1175 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
1176 uint64_t offset, unsigned size);
1177 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1178 void si_test_gds(struct si_context *sctx);
1179
1180 /* si_debug.c */
1181 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
1182 struct radeon_saved_cs *saved, bool get_buffer_list);
1183 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1184 void si_destroy_saved_cs(struct si_saved_cs *scs);
1185 void si_auto_log_cs(void *data, struct u_log_context *log);
1186 void si_log_hw_flush(struct si_context *sctx);
1187 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1188 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1189 void si_init_debug_functions(struct si_context *sctx);
1190 void si_check_vm_faults(struct si_context *sctx,
1191 struct radeon_saved_cs *saved, enum ring_type ring);
1192 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
1193
1194 /* si_dma.c */
1195 void si_init_dma_functions(struct si_context *sctx);
1196
1197 /* si_dma_cs.c */
1198 void si_dma_emit_timestamp(struct si_context *sctx, struct r600_resource *dst,
1199 uint64_t offset);
1200 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1201 uint64_t offset, uint64_t size, unsigned clear_value);
1202 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
1203 struct r600_resource *dst, struct r600_resource *src);
1204 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
1205 struct pipe_fence_handle **fence);
1206 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
1207 uint64_t offset, uint64_t size, unsigned value);
1208
1209 /* si_fence.c */
1210 void si_cp_release_mem(struct si_context *ctx,
1211 unsigned event, unsigned event_flags,
1212 unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1213 struct r600_resource *buf, uint64_t va,
1214 uint32_t new_fence, unsigned query_type);
1215 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1216 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1217 uint64_t va, uint32_t ref, uint32_t mask, unsigned flags);
1218 void si_init_fence_functions(struct si_context *ctx);
1219 void si_init_screen_fence_functions(struct si_screen *screen);
1220 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1221 struct tc_unflushed_batch_token *tc_token);
1222
1223 /* si_get.c */
1224 void si_init_screen_get_functions(struct si_screen *sscreen);
1225
1226 /* si_gfx_cs.c */
1227 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
1228 struct pipe_fence_handle **fence);
1229 void si_begin_new_gfx_cs(struct si_context *ctx);
1230 void si_need_gfx_cs_space(struct si_context *ctx);
1231
1232 /* r600_gpu_load.c */
1233 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1234 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1235 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
1236 uint64_t begin);
1237
1238 /* si_compute.c */
1239 void si_init_compute_functions(struct si_context *sctx);
1240
1241 /* si_perfcounters.c */
1242 void si_init_perfcounters(struct si_screen *screen);
1243 void si_destroy_perfcounters(struct si_screen *screen);
1244
1245 /* si_pipe.c */
1246 bool si_check_device_reset(struct si_context *sctx);
1247
1248 /* si_query.c */
1249 void si_init_screen_query_functions(struct si_screen *sscreen);
1250 void si_init_query_functions(struct si_context *sctx);
1251 void si_suspend_queries(struct si_context *sctx);
1252 void si_resume_queries(struct si_context *sctx);
1253
1254 /* si_shaderlib_tgsi.c */
1255 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1256 unsigned num_layers);
1257 void *si_create_fixed_func_tcs(struct si_context *sctx);
1258 void *si_create_dma_compute_shader(struct pipe_context *ctx,
1259 unsigned num_dwords_per_thread,
1260 bool dst_stream_cache_policy, bool is_copy);
1261 void *si_create_query_result_cs(struct si_context *sctx);
1262
1263 /* si_test_dma.c */
1264 void si_test_dma(struct si_screen *sscreen);
1265
1266 /* si_test_clearbuffer.c */
1267 void si_test_dma_perf(struct si_screen *sscreen);
1268
1269 /* si_uvd.c */
1270 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1271 const struct pipe_video_codec *templ);
1272
1273 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1274 const struct pipe_video_buffer *tmpl);
1275
1276 /* si_viewport.c */
1277 void si_update_vs_viewport_state(struct si_context *ctx);
1278 void si_init_viewport_functions(struct si_context *ctx);
1279
1280 /* si_texture.c */
1281 bool si_prepare_for_dma_blit(struct si_context *sctx,
1282 struct si_texture *dst,
1283 unsigned dst_level, unsigned dstx,
1284 unsigned dsty, unsigned dstz,
1285 struct si_texture *src,
1286 unsigned src_level,
1287 const struct pipe_box *src_box);
1288 void si_eliminate_fast_color_clear(struct si_context *sctx,
1289 struct si_texture *tex);
1290 void si_texture_discard_cmask(struct si_screen *sscreen,
1291 struct si_texture *tex);
1292 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1293 struct pipe_resource *texture,
1294 struct si_texture **staging);
1295 void si_print_texture_info(struct si_screen *sscreen,
1296 struct si_texture *tex, struct u_log_context *log);
1297 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1298 const struct pipe_resource *templ);
1299 bool vi_dcc_formats_compatible(enum pipe_format format1,
1300 enum pipe_format format2);
1301 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1302 unsigned level,
1303 enum pipe_format view_format);
1304 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1305 struct pipe_resource *tex,
1306 unsigned level,
1307 enum pipe_format view_format);
1308 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1309 struct pipe_resource *texture,
1310 const struct pipe_surface *templ,
1311 unsigned width0, unsigned height0,
1312 unsigned width, unsigned height);
1313 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1314 void vi_separate_dcc_try_enable(struct si_context *sctx,
1315 struct si_texture *tex);
1316 void vi_separate_dcc_start_query(struct si_context *sctx,
1317 struct si_texture *tex);
1318 void vi_separate_dcc_stop_query(struct si_context *sctx,
1319 struct si_texture *tex);
1320 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1321 struct si_texture *tex);
1322 bool si_texture_disable_dcc(struct si_context *sctx,
1323 struct si_texture *tex);
1324 void si_init_screen_texture_functions(struct si_screen *sscreen);
1325 void si_init_context_texture_functions(struct si_context *sctx);
1326
1327
1328 /*
1329 * common helpers
1330 */
1331
1332 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
1333 {
1334 return (struct r600_resource*)r;
1335 }
1336
1337 static inline void
1338 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
1339 {
1340 pipe_resource_reference((struct pipe_resource **)ptr,
1341 (struct pipe_resource *)res);
1342 }
1343
1344 static inline void
1345 si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1346 {
1347 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1348 }
1349
1350 static inline bool
1351 vi_dcc_enabled(struct si_texture *tex, unsigned level)
1352 {
1353 return tex->dcc_offset && level < tex->surface.num_dcc_levels;
1354 }
1355
1356 static inline unsigned
1357 si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1358 {
1359 if (stencil)
1360 return tex->surface.u.legacy.stencil_tiling_index[level];
1361 else
1362 return tex->surface.u.legacy.tiling_index[level];
1363 }
1364
1365 static inline void
1366 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1367 {
1368 if (r) {
1369 /* Add memory usage for need_gfx_cs_space */
1370 sctx->vram += r600_resource(r)->vram_usage;
1371 sctx->gtt += r600_resource(r)->gart_usage;
1372 }
1373 }
1374
1375 static inline void
1376 si_invalidate_draw_sh_constants(struct si_context *sctx)
1377 {
1378 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1379 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1380 }
1381
1382 static inline unsigned
1383 si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1384 {
1385 return 1 << (atom - sctx->atoms.array);
1386 }
1387
1388 static inline void
1389 si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1390 {
1391 unsigned bit = si_get_atom_bit(sctx, atom);
1392
1393 if (dirty)
1394 sctx->dirty_atoms |= bit;
1395 else
1396 sctx->dirty_atoms &= ~bit;
1397 }
1398
1399 static inline bool
1400 si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1401 {
1402 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1403 }
1404
1405 static inline void
1406 si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1407 {
1408 si_set_atom_dirty(sctx, atom, true);
1409 }
1410
1411 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1412 {
1413 if (sctx->gs_shader.cso)
1414 return &sctx->gs_shader;
1415 if (sctx->tes_shader.cso)
1416 return &sctx->tes_shader;
1417
1418 return &sctx->vs_shader;
1419 }
1420
1421 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1422 {
1423 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1424
1425 return vs->cso ? &vs->cso->info : NULL;
1426 }
1427
1428 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1429 {
1430 if (sctx->gs_shader.cso)
1431 return sctx->gs_shader.cso->gs_copy_shader;
1432
1433 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1434 return vs->current ? vs->current : NULL;
1435 }
1436
1437 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1438 unsigned processor)
1439 {
1440 return sscreen->debug_flags & (1 << processor);
1441 }
1442
1443 static inline bool si_get_strmout_en(struct si_context *sctx)
1444 {
1445 return sctx->streamout.streamout_enabled ||
1446 sctx->streamout.prims_gen_query_enabled;
1447 }
1448
1449 static inline unsigned
1450 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1451 {
1452 unsigned alignment, tcc_cache_line_size;
1453
1454 /* If the upload size is less than the cache line size (e.g. 16, 32),
1455 * the whole thing will fit into a cache line if we align it to its size.
1456 * The idea is that multiple small uploads can share a cache line.
1457 * If the upload size is greater, align it to the cache line size.
1458 */
1459 alignment = util_next_power_of_two(upload_size);
1460 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1461 return MIN2(alignment, tcc_cache_line_size);
1462 }
1463
1464 static inline void
1465 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1466 {
1467 if (pipe_reference(&(*dst)->reference, &src->reference))
1468 si_destroy_saved_cs(*dst);
1469
1470 *dst = src;
1471 }
1472
1473 static inline void
1474 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1475 bool shaders_read_metadata)
1476 {
1477 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1478 SI_CONTEXT_INV_VMEM_L1;
1479
1480 if (sctx->chip_class >= GFX9) {
1481 /* Single-sample color is coherent with shaders on GFX9, but
1482 * L2 metadata must be flushed if shaders read metadata.
1483 * (DCC, CMASK).
1484 */
1485 if (num_samples >= 2)
1486 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1487 else if (shaders_read_metadata)
1488 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1489 } else {
1490 /* SI-CI-VI */
1491 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1492 }
1493 }
1494
1495 static inline void
1496 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1497 bool include_stencil, bool shaders_read_metadata)
1498 {
1499 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1500 SI_CONTEXT_INV_VMEM_L1;
1501
1502 if (sctx->chip_class >= GFX9) {
1503 /* Single-sample depth (not stencil) is coherent with shaders
1504 * on GFX9, but L2 metadata must be flushed if shaders read
1505 * metadata.
1506 */
1507 if (num_samples >= 2 || include_stencil)
1508 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1509 else if (shaders_read_metadata)
1510 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1511 } else {
1512 /* SI-CI-VI */
1513 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1514 }
1515 }
1516
1517 static inline bool
1518 si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1519 {
1520 return (stencil_sampler && tex->can_sample_s) ||
1521 (!stencil_sampler && tex->can_sample_z);
1522 }
1523
1524 static inline bool
1525 si_htile_enabled(struct si_texture *tex, unsigned level)
1526 {
1527 return tex->htile_offset && level == 0;
1528 }
1529
1530 static inline bool
1531 vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level)
1532 {
1533 assert(!tex->tc_compatible_htile || tex->htile_offset);
1534 return tex->tc_compatible_htile && level == 0;
1535 }
1536
1537 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1538 {
1539 if (sctx->ps_uses_fbfetch)
1540 return sctx->framebuffer.nr_color_samples;
1541
1542 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1543 }
1544
1545 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1546 {
1547 if (sctx->queued.named.rasterizer->rasterizer_discard)
1548 return 0;
1549
1550 struct si_shader_selector *ps = sctx->ps_shader.cso;
1551 if (!ps)
1552 return 0;
1553
1554 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1555 sctx->queued.named.blend->cb_target_mask;
1556
1557 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1558 colormask &= ps->colors_written_4bit;
1559 else if (!ps->colors_written_4bit)
1560 colormask = 0; /* color0 writes all cbufs, but it's not written */
1561
1562 return colormask;
1563 }
1564
1565 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1566 (1 << PIPE_PRIM_LINE_LOOP) | \
1567 (1 << PIPE_PRIM_LINE_STRIP) | \
1568 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1569 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1570
1571 static inline bool util_prim_is_lines(unsigned prim)
1572 {
1573 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1574 }
1575
1576 static inline bool util_prim_is_points_or_lines(unsigned prim)
1577 {
1578 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES |
1579 (1 << PIPE_PRIM_POINTS))) != 0;
1580 }
1581
1582 /**
1583 * Return true if there is enough memory in VRAM and GTT for the buffers
1584 * added so far.
1585 *
1586 * \param vram VRAM memory size not added to the buffer list yet
1587 * \param gtt GTT memory size not added to the buffer list yet
1588 */
1589 static inline bool
1590 radeon_cs_memory_below_limit(struct si_screen *screen,
1591 struct radeon_cmdbuf *cs,
1592 uint64_t vram, uint64_t gtt)
1593 {
1594 vram += cs->used_vram;
1595 gtt += cs->used_gart;
1596
1597 /* Anything that goes above the VRAM size should go to GTT. */
1598 if (vram > screen->info.vram_size)
1599 gtt += vram - screen->info.vram_size;
1600
1601 /* Now we just need to check if we have enough GTT. */
1602 return gtt < screen->info.gart_size * 0.7;
1603 }
1604
1605 /**
1606 * Add a buffer to the buffer list for the given command stream (CS).
1607 *
1608 * All buffers used by a CS must be added to the list. This tells the kernel
1609 * driver which buffers are used by GPU commands. Other buffers can
1610 * be swapped out (not accessible) during execution.
1611 *
1612 * The buffer list becomes empty after every context flush and must be
1613 * rebuilt.
1614 */
1615 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1616 struct radeon_cmdbuf *cs,
1617 struct r600_resource *rbo,
1618 enum radeon_bo_usage usage,
1619 enum radeon_bo_priority priority)
1620 {
1621 assert(usage);
1622 sctx->ws->cs_add_buffer(
1623 cs, rbo->buf,
1624 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1625 rbo->domains, priority);
1626 }
1627
1628 /**
1629 * Same as above, but also checks memory usage and flushes the context
1630 * accordingly.
1631 *
1632 * When this SHOULD NOT be used:
1633 *
1634 * - if si_context_add_resource_size has been called for the buffer
1635 * followed by *_need_cs_space for checking the memory usage
1636 *
1637 * - if si_need_dma_space has been called for the buffer
1638 *
1639 * - when emitting state packets and draw packets (because preceding packets
1640 * can't be re-emitted at that point)
1641 *
1642 * - if shader resource "enabled_mask" is not up-to-date or there is
1643 * a different constraint disallowing a context flush
1644 */
1645 static inline void
1646 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1647 struct r600_resource *rbo,
1648 enum radeon_bo_usage usage,
1649 enum radeon_bo_priority priority,
1650 bool check_mem)
1651 {
1652 if (check_mem &&
1653 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1654 sctx->vram + rbo->vram_usage,
1655 sctx->gtt + rbo->gart_usage))
1656 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1657
1658 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, rbo, usage, priority);
1659 }
1660
1661 #define PRINT_ERR(fmt, args...) \
1662 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1663
1664 #endif