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radeonsi: clear allocator_zeroed_memory with SDMA
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
34
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
37 #else
38 #define SI_BIG_ENDIAN 0
39 #endif
40
41 #define ATI_VENDOR_ID 0x1002
42
43 #define SI_NOT_QUERY 0xffffffff
44
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
56
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
61
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
69 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
70 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
71 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
72 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
73 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
74 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
75 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
76 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
77 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
78 * a CB or DB flush. */
79 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
80 /* Framebuffer caches. */
81 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
82 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
83 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
84 /* Engine synchronization. */
85 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
86 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
87 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
88 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
89 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
90
91 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
92 #define SI_PREFETCH_LS (1 << 1)
93 #define SI_PREFETCH_HS (1 << 2)
94 #define SI_PREFETCH_ES (1 << 3)
95 #define SI_PREFETCH_GS (1 << 4)
96 #define SI_PREFETCH_VS (1 << 5)
97 #define SI_PREFETCH_PS (1 << 6)
98
99 #define SI_MAX_BORDER_COLORS 4096
100 #define SI_MAX_VIEWPORTS 16
101 #define SIX_BITS 0x3F
102 #define SI_MAP_BUFFER_ALIGNMENT 64
103 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
104
105 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
106 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
107 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
108 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
109 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
110 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
111 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
112 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
113
114 enum si_clear_code
115 {
116 DCC_CLEAR_COLOR_0000 = 0x00000000,
117 DCC_CLEAR_COLOR_0001 = 0x40404040,
118 DCC_CLEAR_COLOR_1110 = 0x80808080,
119 DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
120 DCC_CLEAR_COLOR_REG = 0x20202020,
121 DCC_UNCOMPRESSED = 0xFFFFFFFF,
122 };
123
124 /* Debug flags. */
125 enum {
126 /* Shader logging options: */
127 DBG_VS = PIPE_SHADER_VERTEX,
128 DBG_PS = PIPE_SHADER_FRAGMENT,
129 DBG_GS = PIPE_SHADER_GEOMETRY,
130 DBG_TCS = PIPE_SHADER_TESS_CTRL,
131 DBG_TES = PIPE_SHADER_TESS_EVAL,
132 DBG_CS = PIPE_SHADER_COMPUTE,
133 DBG_NO_IR,
134 DBG_NO_TGSI,
135 DBG_NO_ASM,
136 DBG_PREOPT_IR,
137
138 /* Shader compiler options the shader cache should be aware of: */
139 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
140 DBG_UNSAFE_MATH,
141 DBG_SI_SCHED,
142 DBG_GISEL,
143
144 /* Shader compiler options (with no effect on the shader cache): */
145 DBG_CHECK_IR,
146 DBG_NIR,
147 DBG_MONOLITHIC_SHADERS,
148 DBG_NO_OPT_VARIANT,
149
150 /* Information logging options: */
151 DBG_INFO,
152 DBG_TEX,
153 DBG_COMPUTE,
154 DBG_VM,
155
156 /* Driver options: */
157 DBG_FORCE_DMA,
158 DBG_NO_ASYNC_DMA,
159 DBG_NO_WC,
160 DBG_CHECK_VM,
161 DBG_RESERVE_VMID,
162 DBG_ZERO_VRAM,
163
164 /* 3D engine options: */
165 DBG_SWITCH_ON_EOP,
166 DBG_NO_OUT_OF_ORDER,
167 DBG_NO_DPBB,
168 DBG_NO_DFSM,
169 DBG_DPBB,
170 DBG_DFSM,
171 DBG_NO_HYPERZ,
172 DBG_NO_RB_PLUS,
173 DBG_NO_2D_TILING,
174 DBG_NO_TILING,
175 DBG_NO_DCC,
176 DBG_NO_DCC_CLEAR,
177 DBG_NO_DCC_FB,
178 DBG_NO_DCC_MSAA,
179 DBG_NO_FMASK,
180
181 /* Tests: */
182 DBG_TEST_DMA,
183 DBG_TEST_VMFAULT_CP,
184 DBG_TEST_VMFAULT_SDMA,
185 DBG_TEST_VMFAULT_SHADER,
186 DBG_TEST_DMA_PERF,
187 DBG_TEST_GDS,
188 DBG_TEST_GDS_MM,
189 DBG_TEST_GDS_OA_MM,
190 };
191
192 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
193 #define DBG(name) (1ull << DBG_##name)
194
195 enum si_cache_policy {
196 L2_BYPASS,
197 L2_STREAM, /* same as SLC=1 */
198 L2_LRU, /* same as SLC=0 */
199 };
200
201 enum si_coherency {
202 SI_COHERENCY_NONE, /* no cache flushes needed */
203 SI_COHERENCY_SHADER,
204 SI_COHERENCY_CB_META,
205 SI_COHERENCY_CP,
206 };
207
208 struct si_compute;
209 struct hash_table;
210 struct u_suballocator;
211
212 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
213 * at the moment.
214 */
215 struct si_resource {
216 struct threaded_resource b;
217
218 /* Winsys objects. */
219 struct pb_buffer *buf;
220 uint64_t gpu_address;
221 /* Memory usage if the buffer placement is optimal. */
222 uint64_t vram_usage;
223 uint64_t gart_usage;
224
225 /* Resource properties. */
226 uint64_t bo_size;
227 unsigned bo_alignment;
228 enum radeon_bo_domain domains;
229 enum radeon_bo_flag flags;
230 unsigned bind_history;
231 int max_forced_staging_uploads;
232
233 /* The buffer range which is initialized (with a write transfer,
234 * streamout, DMA, or as a random access target). The rest of
235 * the buffer is considered invalid and can be mapped unsynchronized.
236 *
237 * This allows unsychronized mapping of a buffer range which hasn't
238 * been used yet. It's for applications which forget to use
239 * the unsynchronized map flag and expect the driver to figure it out.
240 */
241 struct util_range valid_buffer_range;
242
243 /* For buffers only. This indicates that a write operation has been
244 * performed by TC L2, but the cache hasn't been flushed.
245 * Any hw block which doesn't use or bypasses TC L2 should check this
246 * flag and flush the cache before using the buffer.
247 *
248 * For example, TC L2 must be flushed if a buffer which has been
249 * modified by a shader store instruction is about to be used as
250 * an index buffer. The reason is that VGT DMA index fetching doesn't
251 * use TC L2.
252 */
253 bool TC_L2_dirty;
254
255 /* Whether this resource is referenced by bindless handles. */
256 bool texture_handle_allocated;
257 bool image_handle_allocated;
258
259 /* Whether the resource has been exported via resource_get_handle. */
260 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
261 };
262
263 struct si_transfer {
264 struct threaded_transfer b;
265 struct si_resource *staging;
266 unsigned offset;
267 };
268
269 struct si_texture {
270 struct si_resource buffer;
271
272 struct radeon_surf surface;
273 uint64_t size;
274 struct si_texture *flushed_depth_texture;
275
276 /* Colorbuffer compression and fast clear. */
277 uint64_t fmask_offset;
278 uint64_t cmask_offset;
279 uint64_t cmask_base_address_reg;
280 struct si_resource *cmask_buffer;
281 uint64_t dcc_offset; /* 0 = disabled */
282 unsigned cb_color_info; /* fast clear enable bit */
283 unsigned color_clear_value[2];
284 unsigned last_msaa_resolve_target_micro_mode;
285 unsigned num_level0_transfers;
286
287 /* Depth buffer compression and fast clear. */
288 uint64_t htile_offset;
289 float depth_clear_value;
290 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
291 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
292 enum pipe_format db_render_format:16;
293 uint8_t stencil_clear_value;
294 bool tc_compatible_htile:1;
295 bool depth_cleared:1; /* if it was cleared at least once */
296 bool stencil_cleared:1; /* if it was cleared at least once */
297 bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
298 bool is_depth:1;
299 bool db_compatible:1;
300 bool can_sample_z:1;
301 bool can_sample_s:1;
302
303 /* We need to track DCC dirtiness, because st/dri usually calls
304 * flush_resource twice per frame (not a bug) and we don't wanna
305 * decompress DCC twice. Also, the dirty tracking must be done even
306 * if DCC isn't used, because it's required by the DCC usage analysis
307 * for a possible future enablement.
308 */
309 bool separate_dcc_dirty:1;
310 /* Statistics gathering for the DCC enablement heuristic. */
311 bool dcc_gather_statistics:1;
312 /* Counter that should be non-zero if the texture is bound to a
313 * framebuffer.
314 */
315 unsigned framebuffers_bound;
316 /* Whether the texture is a displayable back buffer and needs DCC
317 * decompression, which is expensive. Therefore, it's enabled only
318 * if statistics suggest that it will pay off and it's allocated
319 * separately. It can't be bound as a sampler by apps. Limited to
320 * target == 2D and last_level == 0. If enabled, dcc_offset contains
321 * the absolute GPUVM address, not the relative one.
322 */
323 struct si_resource *dcc_separate_buffer;
324 /* When DCC is temporarily disabled, the separate buffer is here. */
325 struct si_resource *last_dcc_separate_buffer;
326 /* Estimate of how much this color buffer is written to in units of
327 * full-screen draws: ps_invocations / (width * height)
328 * Shader kills, late Z, and blending with trivial discards make it
329 * inaccurate (we need to count CB updates, not PS invocations).
330 */
331 unsigned ps_draw_ratio;
332 /* The number of clears since the last DCC usage analysis. */
333 unsigned num_slow_clears;
334 };
335
336 struct si_surface {
337 struct pipe_surface base;
338
339 /* These can vary with block-compressed textures. */
340 uint16_t width0;
341 uint16_t height0;
342
343 bool color_initialized:1;
344 bool depth_initialized:1;
345
346 /* Misc. color flags. */
347 bool color_is_int8:1;
348 bool color_is_int10:1;
349 bool dcc_incompatible:1;
350
351 /* Color registers. */
352 unsigned cb_color_info;
353 unsigned cb_color_view;
354 unsigned cb_color_attrib;
355 unsigned cb_color_attrib2; /* GFX9 and later */
356 unsigned cb_dcc_control; /* VI and later */
357 unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */
358 unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
359 unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
360 unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
361
362 /* DB registers. */
363 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
364 uint64_t db_stencil_base;
365 uint64_t db_htile_data_base;
366 unsigned db_depth_info;
367 unsigned db_z_info;
368 unsigned db_z_info2; /* GFX9+ */
369 unsigned db_depth_view;
370 unsigned db_depth_size;
371 unsigned db_depth_slice;
372 unsigned db_stencil_info;
373 unsigned db_stencil_info2; /* GFX9+ */
374 unsigned db_htile_surface;
375 };
376
377 struct si_mmio_counter {
378 unsigned busy;
379 unsigned idle;
380 };
381
382 union si_mmio_counters {
383 struct {
384 /* For global GPU load including SDMA. */
385 struct si_mmio_counter gpu;
386
387 /* GRBM_STATUS */
388 struct si_mmio_counter spi;
389 struct si_mmio_counter gui;
390 struct si_mmio_counter ta;
391 struct si_mmio_counter gds;
392 struct si_mmio_counter vgt;
393 struct si_mmio_counter ia;
394 struct si_mmio_counter sx;
395 struct si_mmio_counter wd;
396 struct si_mmio_counter bci;
397 struct si_mmio_counter sc;
398 struct si_mmio_counter pa;
399 struct si_mmio_counter db;
400 struct si_mmio_counter cp;
401 struct si_mmio_counter cb;
402
403 /* SRBM_STATUS2 */
404 struct si_mmio_counter sdma;
405
406 /* CP_STAT */
407 struct si_mmio_counter pfp;
408 struct si_mmio_counter meq;
409 struct si_mmio_counter me;
410 struct si_mmio_counter surf_sync;
411 struct si_mmio_counter cp_dma;
412 struct si_mmio_counter scratch_ram;
413 } named;
414 unsigned array[0];
415 };
416
417 struct si_memory_object {
418 struct pipe_memory_object b;
419 struct pb_buffer *buf;
420 uint32_t stride;
421 };
422
423 /* Saved CS data for debugging features. */
424 struct radeon_saved_cs {
425 uint32_t *ib;
426 unsigned num_dw;
427
428 struct radeon_bo_list_item *bo_list;
429 unsigned bo_count;
430 };
431
432 struct si_screen {
433 struct pipe_screen b;
434 struct radeon_winsys *ws;
435 struct disk_cache *disk_shader_cache;
436
437 struct radeon_info info;
438 uint64_t debug_flags;
439 char renderer_string[183];
440
441 unsigned pa_sc_raster_config;
442 unsigned pa_sc_raster_config_1;
443 unsigned se_tile_repeat;
444 unsigned gs_table_depth;
445 unsigned tess_offchip_block_dw_size;
446 unsigned tess_offchip_ring_size;
447 unsigned tess_factor_ring_size;
448 unsigned vgt_hs_offchip_param;
449 unsigned eqaa_force_coverage_samples;
450 unsigned eqaa_force_z_samples;
451 unsigned eqaa_force_color_samples;
452 bool has_clear_state;
453 bool has_distributed_tess;
454 bool has_draw_indirect_multi;
455 bool has_out_of_order_rast;
456 bool assume_no_z_fights;
457 bool commutative_blend_add;
458 bool clear_db_cache_before_clear;
459 bool has_msaa_sample_loc_bug;
460 bool has_ls_vgpr_init_bug;
461 bool has_dcc_constant_encode;
462 bool dpbb_allowed;
463 bool dfsm_allowed;
464 bool llvm_has_working_vgpr_indexing;
465
466 /* Whether shaders are monolithic (1-part) or separate (3-part). */
467 bool use_monolithic_shaders;
468 bool record_llvm_ir;
469 bool has_rbplus; /* if RB+ registers exist */
470 bool rbplus_allowed; /* if RB+ is allowed */
471 bool dcc_msaa_allowed;
472 bool cpdma_prefetch_writes_memory;
473
474 struct slab_parent_pool pool_transfers;
475
476 /* Texture filter settings. */
477 int force_aniso; /* -1 = disabled */
478
479 /* Auxiliary context. Mainly used to initialize resources.
480 * It must be locked prior to using and flushed before unlocking. */
481 struct pipe_context *aux_context;
482 mtx_t aux_context_lock;
483
484 /* This must be in the screen, because UE4 uses one context for
485 * compilation and another one for rendering.
486 */
487 unsigned num_compilations;
488 /* Along with ST_DEBUG=precompile, this should show if applications
489 * are loading shaders on demand. This is a monotonic counter.
490 */
491 unsigned num_shaders_created;
492 unsigned num_shader_cache_hits;
493
494 /* GPU load thread. */
495 mtx_t gpu_load_mutex;
496 thrd_t gpu_load_thread;
497 union si_mmio_counters mmio_counters;
498 volatile unsigned gpu_load_stop_thread; /* bool */
499
500 /* Performance counters. */
501 struct si_perfcounters *perfcounters;
502
503 /* If pipe_screen wants to recompute and re-emit the framebuffer,
504 * sampler, and image states of all contexts, it should atomically
505 * increment this.
506 *
507 * Each context will compare this with its own last known value of
508 * the counter before drawing and re-emit the states accordingly.
509 */
510 unsigned dirty_tex_counter;
511
512 /* Atomically increment this counter when an existing texture's
513 * metadata is enabled or disabled in a way that requires changing
514 * contexts' compressed texture binding masks.
515 */
516 unsigned compressed_colortex_counter;
517
518 struct {
519 /* Context flags to set so that all writes from earlier jobs
520 * in the CP are seen by L2 clients.
521 */
522 unsigned cp_to_L2;
523
524 /* Context flags to set so that all writes from earlier jobs
525 * that end in L2 are seen by CP.
526 */
527 unsigned L2_to_cp;
528 } barrier_flags;
529
530 mtx_t shader_parts_mutex;
531 struct si_shader_part *vs_prologs;
532 struct si_shader_part *tcs_epilogs;
533 struct si_shader_part *gs_prologs;
534 struct si_shader_part *ps_prologs;
535 struct si_shader_part *ps_epilogs;
536
537 /* Shader cache in memory.
538 *
539 * Design & limitations:
540 * - The shader cache is per screen (= per process), never saved to
541 * disk, and skips redundant shader compilations from TGSI to bytecode.
542 * - It can only be used with one-variant-per-shader support, in which
543 * case only the main (typically middle) part of shaders is cached.
544 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
545 * variants of VS and TES are cached, so LS and ES aren't.
546 * - GS and CS aren't cached, but it's certainly possible to cache
547 * those as well.
548 */
549 mtx_t shader_cache_mutex;
550 struct hash_table *shader_cache;
551
552 /* Shader compiler queue for multithreaded compilation. */
553 struct util_queue shader_compiler_queue;
554 /* Use at most 3 normal compiler threads on quadcore and better.
555 * Hyperthreaded CPUs report the number of threads, but we want
556 * the number of cores. We only need this many threads for shader-db. */
557 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
558
559 struct util_queue shader_compiler_queue_low_priority;
560 /* Use at most 2 low priority threads on quadcore and better.
561 * We want to minimize the impact on multithreaded Mesa. */
562 struct ac_llvm_compiler compiler_lowp[10];
563 };
564
565 struct si_blend_color {
566 struct pipe_blend_color state;
567 bool any_nonzeros;
568 };
569
570 struct si_sampler_view {
571 struct pipe_sampler_view base;
572 /* [0..7] = image descriptor
573 * [4..7] = buffer descriptor */
574 uint32_t state[8];
575 uint32_t fmask_state[8];
576 const struct legacy_surf_level *base_level_info;
577 ubyte base_level;
578 ubyte block_width;
579 bool is_stencil_sampler;
580 bool is_integer;
581 bool dcc_incompatible;
582 };
583
584 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
585
586 struct si_sampler_state {
587 #ifdef DEBUG
588 unsigned magic;
589 #endif
590 uint32_t val[4];
591 uint32_t integer_val[4];
592 uint32_t upgraded_depth_val[4];
593 };
594
595 struct si_cs_shader_state {
596 struct si_compute *program;
597 struct si_compute *emitted_program;
598 unsigned offset;
599 bool initialized;
600 bool uses_scratch;
601 };
602
603 struct si_samplers {
604 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
605 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
606
607 /* The i-th bit is set if that element is enabled (non-NULL resource). */
608 unsigned enabled_mask;
609 uint32_t needs_depth_decompress_mask;
610 uint32_t needs_color_decompress_mask;
611 };
612
613 struct si_images {
614 struct pipe_image_view views[SI_NUM_IMAGES];
615 uint32_t needs_color_decompress_mask;
616 unsigned enabled_mask;
617 };
618
619 struct si_framebuffer {
620 struct pipe_framebuffer_state state;
621 unsigned colorbuf_enabled_4bit;
622 unsigned spi_shader_col_format;
623 unsigned spi_shader_col_format_alpha;
624 unsigned spi_shader_col_format_blend;
625 unsigned spi_shader_col_format_blend_alpha;
626 ubyte nr_samples:5; /* at most 16xAA */
627 ubyte log_samples:3; /* at most 4 = 16xAA */
628 ubyte nr_color_samples; /* at most 8xAA */
629 ubyte compressed_cb_mask;
630 ubyte uncompressed_cb_mask;
631 ubyte color_is_int8;
632 ubyte color_is_int10;
633 ubyte dirty_cbufs;
634 ubyte dcc_overwrite_combiner_watermark;
635 bool dirty_zsbuf;
636 bool any_dst_linear;
637 bool CB_has_shader_readable_metadata;
638 bool DB_has_shader_readable_metadata;
639 };
640
641 enum si_quant_mode {
642 /* This is the list we want to support. */
643 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
644 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
645 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
646 };
647
648 struct si_signed_scissor {
649 int minx;
650 int miny;
651 int maxx;
652 int maxy;
653 enum si_quant_mode quant_mode;
654 };
655
656 struct si_scissors {
657 unsigned dirty_mask;
658 struct pipe_scissor_state states[SI_MAX_VIEWPORTS];
659 };
660
661 struct si_viewports {
662 unsigned dirty_mask;
663 unsigned depth_range_dirty_mask;
664 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
665 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
666 };
667
668 struct si_clip_state {
669 struct pipe_clip_state state;
670 bool any_nonzeros;
671 };
672
673 struct si_streamout_target {
674 struct pipe_stream_output_target b;
675
676 /* The buffer where BUFFER_FILLED_SIZE is stored. */
677 struct si_resource *buf_filled_size;
678 unsigned buf_filled_size_offset;
679 bool buf_filled_size_valid;
680
681 unsigned stride_in_dw;
682 };
683
684 struct si_streamout {
685 bool begin_emitted;
686
687 unsigned enabled_mask;
688 unsigned num_targets;
689 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
690
691 unsigned append_bitmask;
692 bool suspended;
693
694 /* External state which comes from the vertex shader,
695 * it must be set explicitly when binding a shader. */
696 uint16_t *stride_in_dw;
697 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
698
699 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
700 unsigned hw_enabled_mask;
701
702 /* The state of VGT_STRMOUT_(CONFIG|EN). */
703 bool streamout_enabled;
704 bool prims_gen_query_enabled;
705 int num_prims_gen_queries;
706 };
707
708 /* A shader state consists of the shader selector, which is a constant state
709 * object shared by multiple contexts and shouldn't be modified, and
710 * the current shader variant selected for this context.
711 */
712 struct si_shader_ctx_state {
713 struct si_shader_selector *cso;
714 struct si_shader *current;
715 };
716
717 #define SI_NUM_VGT_PARAM_KEY_BITS 12
718 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
719
720 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
721 * Some fields are set by state-change calls, most are set by draw_vbo.
722 */
723 union si_vgt_param_key {
724 struct {
725 #ifdef PIPE_ARCH_LITTLE_ENDIAN
726 unsigned prim:4;
727 unsigned uses_instancing:1;
728 unsigned multi_instances_smaller_than_primgroup:1;
729 unsigned primitive_restart:1;
730 unsigned count_from_stream_output:1;
731 unsigned line_stipple_enabled:1;
732 unsigned uses_tess:1;
733 unsigned tess_uses_prim_id:1;
734 unsigned uses_gs:1;
735 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
736 #else /* PIPE_ARCH_BIG_ENDIAN */
737 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
738 unsigned uses_gs:1;
739 unsigned tess_uses_prim_id:1;
740 unsigned uses_tess:1;
741 unsigned line_stipple_enabled:1;
742 unsigned count_from_stream_output:1;
743 unsigned primitive_restart:1;
744 unsigned multi_instances_smaller_than_primgroup:1;
745 unsigned uses_instancing:1;
746 unsigned prim:4;
747 #endif
748 } u;
749 uint32_t index;
750 };
751
752 struct si_texture_handle
753 {
754 unsigned desc_slot;
755 bool desc_dirty;
756 struct pipe_sampler_view *view;
757 struct si_sampler_state sstate;
758 };
759
760 struct si_image_handle
761 {
762 unsigned desc_slot;
763 bool desc_dirty;
764 struct pipe_image_view view;
765 };
766
767 struct si_saved_cs {
768 struct pipe_reference reference;
769 struct si_context *ctx;
770 struct radeon_saved_cs gfx;
771 struct si_resource *trace_buf;
772 unsigned trace_id;
773
774 unsigned gfx_last_dw;
775 bool flushed;
776 int64_t time_flush;
777 };
778
779 struct si_context {
780 struct pipe_context b; /* base class */
781
782 enum radeon_family family;
783 enum chip_class chip_class;
784
785 struct radeon_winsys *ws;
786 struct radeon_winsys_ctx *ctx;
787 struct radeon_cmdbuf *gfx_cs;
788 struct radeon_cmdbuf *dma_cs;
789 struct pipe_fence_handle *last_gfx_fence;
790 struct pipe_fence_handle *last_sdma_fence;
791 struct si_resource *eop_bug_scratch;
792 struct u_upload_mgr *cached_gtt_allocator;
793 struct threaded_context *tc;
794 struct u_suballocator *allocator_zeroed_memory;
795 struct slab_child_pool pool_transfers;
796 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
797 struct pipe_device_reset_callback device_reset_callback;
798 struct u_log_context *log;
799 void *query_result_shader;
800 struct blitter_context *blitter;
801 void *custom_dsa_flush;
802 void *custom_blend_resolve;
803 void *custom_blend_fmask_decompress;
804 void *custom_blend_eliminate_fastclear;
805 void *custom_blend_dcc_decompress;
806 void *vs_blit_pos;
807 void *vs_blit_pos_layered;
808 void *vs_blit_color;
809 void *vs_blit_color_layered;
810 void *vs_blit_texcoord;
811 void *cs_clear_buffer;
812 void *cs_copy_buffer;
813 void *cs_copy_image;
814 void *cs_copy_image_1d_array;
815 void *cs_clear_render_target;
816 void *cs_clear_render_target_1d_array;
817 struct si_screen *screen;
818 struct pipe_debug_callback debug;
819 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
820 struct si_shader_ctx_state fixed_func_tcs_shader;
821 struct si_resource *wait_mem_scratch;
822 unsigned wait_mem_number;
823 uint16_t prefetch_L2_mask;
824
825 bool gfx_flush_in_progress:1;
826 bool gfx_last_ib_is_busy:1;
827 bool compute_is_busy:1;
828
829 unsigned num_gfx_cs_flushes;
830 unsigned initial_gfx_cs_size;
831 unsigned gpu_reset_counter;
832 unsigned last_dirty_tex_counter;
833 unsigned last_compressed_colortex_counter;
834 unsigned last_num_draw_calls;
835 unsigned flags; /* flush flags */
836 /* Current unaccounted memory usage. */
837 uint64_t vram;
838 uint64_t gtt;
839
840 /* Atoms (direct states). */
841 union si_state_atoms atoms;
842 unsigned dirty_atoms; /* mask */
843 /* PM4 states (precomputed immutable states) */
844 unsigned dirty_states;
845 union si_state queued;
846 union si_state emitted;
847
848 /* Atom declarations. */
849 struct si_framebuffer framebuffer;
850 unsigned sample_locs_num_samples;
851 uint16_t sample_mask;
852 unsigned last_cb_target_mask;
853 struct si_blend_color blend_color;
854 struct si_clip_state clip_state;
855 struct si_shader_data shader_pointers;
856 struct si_stencil_ref stencil_ref;
857 struct si_scissors scissors;
858 struct si_streamout streamout;
859 struct si_viewports viewports;
860 unsigned num_window_rectangles;
861 bool window_rectangles_include;
862 struct pipe_scissor_state window_rectangles[4];
863
864 /* Precomputed states. */
865 struct si_pm4_state *init_config;
866 struct si_pm4_state *init_config_gs_rings;
867 bool init_config_has_vgt_flush;
868 struct si_pm4_state *vgt_shader_config[4];
869
870 /* shaders */
871 struct si_shader_ctx_state ps_shader;
872 struct si_shader_ctx_state gs_shader;
873 struct si_shader_ctx_state vs_shader;
874 struct si_shader_ctx_state tcs_shader;
875 struct si_shader_ctx_state tes_shader;
876 struct si_cs_shader_state cs_shader_state;
877
878 /* shader information */
879 struct si_vertex_elements *vertex_elements;
880 unsigned sprite_coord_enable;
881 unsigned cs_max_waves_per_sh;
882 bool flatshade;
883 bool do_update_shaders;
884
885 /* vertex buffer descriptors */
886 uint32_t *vb_descriptors_gpu_list;
887 struct si_resource *vb_descriptors_buffer;
888 unsigned vb_descriptors_offset;
889
890 /* shader descriptors */
891 struct si_descriptors descriptors[SI_NUM_DESCS];
892 unsigned descriptors_dirty;
893 unsigned shader_pointers_dirty;
894 unsigned shader_needs_decompress_mask;
895 struct si_buffer_resources rw_buffers;
896 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
897 struct si_samplers samplers[SI_NUM_SHADERS];
898 struct si_images images[SI_NUM_SHADERS];
899
900 /* other shader resources */
901 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
902 struct pipe_resource *esgs_ring;
903 struct pipe_resource *gsvs_ring;
904 struct pipe_resource *tess_rings;
905 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
906 struct si_resource *border_color_buffer;
907 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
908 unsigned border_color_count;
909 unsigned num_vs_blit_sgprs;
910 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
911 uint32_t cs_user_data[4];
912
913 /**
914 * last_block allows disabling threads at the farthermost grid boundary.
915 * Full blocks as specified by "block" are launched, but the threads
916 * outside of "last_block" dimensions are disabled.
917 *
918 * If a block touches the grid boundary in the i-th axis, threads with
919 * THREAD_ID[i] >= last_block[i] are disabled.
920 *
921 * If last_block[i] is 0, it has the same behavior as last_block[i] = block[i],
922 * meaning no effect.
923 *
924 * It's equivalent to doing this at the beginning of the compute shader:
925 *
926 * for (i = 0; i < 3; i++) {
927 * if (block_id[i] == grid[i] - 1 &&
928 * last_block[i] && last_block[i] >= thread_id[i])
929 * return;
930 * }
931 * (this could be moved into pipe_grid_info)
932 */
933 uint compute_last_block[3];
934
935 /* Vertex and index buffers. */
936 bool vertex_buffers_dirty;
937 bool vertex_buffer_pointer_dirty;
938 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
939
940 /* MSAA config state. */
941 int ps_iter_samples;
942 bool ps_uses_fbfetch;
943 bool smoothing_enabled;
944
945 /* DB render state. */
946 unsigned ps_db_shader_control;
947 unsigned dbcb_copy_sample;
948 bool dbcb_depth_copy_enabled:1;
949 bool dbcb_stencil_copy_enabled:1;
950 bool db_flush_depth_inplace:1;
951 bool db_flush_stencil_inplace:1;
952 bool db_depth_clear:1;
953 bool db_depth_disable_expclear:1;
954 bool db_stencil_clear:1;
955 bool db_stencil_disable_expclear:1;
956 bool occlusion_queries_disabled:1;
957 bool generate_mipmap_for_depth:1;
958
959 /* Emitted draw state. */
960 bool gs_tri_strip_adj_fix:1;
961 bool ls_vgpr_fix:1;
962 int last_index_size;
963 int last_base_vertex;
964 int last_start_instance;
965 int last_instance_count;
966 int last_drawid;
967 int last_sh_base_reg;
968 int last_primitive_restart_en;
969 int last_restart_index;
970 int last_prim;
971 int last_multi_vgt_param;
972 int last_rast_prim;
973 unsigned last_sc_line_stipple;
974 unsigned current_vs_state;
975 unsigned last_vs_state;
976 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
977
978 /* Scratch buffer */
979 struct si_resource *scratch_buffer;
980 unsigned scratch_waves;
981 unsigned spi_tmpring_size;
982
983 struct si_resource *compute_scratch_buffer;
984
985 /* Emitted derived tessellation state. */
986 /* Local shader (VS), or HS if LS-HS are merged. */
987 struct si_shader *last_ls;
988 struct si_shader_selector *last_tcs;
989 int last_num_tcs_input_cp;
990 int last_tes_sh_base;
991 bool last_tess_uses_primid;
992 unsigned last_num_patches;
993 int last_ls_hs_config;
994
995 /* Debug state. */
996 bool is_debug;
997 struct si_saved_cs *current_saved_cs;
998 uint64_t dmesg_timestamp;
999 unsigned apitrace_call_number;
1000
1001 /* Other state */
1002 bool need_check_render_feedback;
1003 bool decompression_enabled;
1004 bool dpbb_force_off;
1005 bool vs_writes_viewport_index;
1006 bool vs_disables_clipping_viewport;
1007
1008 /* Precomputed IA_MULTI_VGT_PARAM */
1009 union si_vgt_param_key ia_multi_vgt_param_key;
1010 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1011
1012 /* Bindless descriptors. */
1013 struct si_descriptors bindless_descriptors;
1014 struct util_idalloc bindless_used_slots;
1015 unsigned num_bindless_descriptors;
1016 bool bindless_descriptors_dirty;
1017 bool graphics_bindless_pointer_dirty;
1018 bool compute_bindless_pointer_dirty;
1019
1020 /* Allocated bindless handles */
1021 struct hash_table *tex_handles;
1022 struct hash_table *img_handles;
1023
1024 /* Resident bindless handles */
1025 struct util_dynarray resident_tex_handles;
1026 struct util_dynarray resident_img_handles;
1027
1028 /* Resident bindless handles which need decompression */
1029 struct util_dynarray resident_tex_needs_color_decompress;
1030 struct util_dynarray resident_img_needs_color_decompress;
1031 struct util_dynarray resident_tex_needs_depth_decompress;
1032
1033 /* Bindless state */
1034 bool uses_bindless_samplers;
1035 bool uses_bindless_images;
1036
1037 /* MSAA sample locations.
1038 * The first index is the sample index.
1039 * The second index is the coordinate: X, Y. */
1040 struct {
1041 float x1[1][2];
1042 float x2[2][2];
1043 float x4[4][2];
1044 float x8[8][2];
1045 float x16[16][2];
1046 } sample_positions;
1047 struct pipe_resource *sample_pos_buffer;
1048
1049 /* Misc stats. */
1050 unsigned num_draw_calls;
1051 unsigned num_decompress_calls;
1052 unsigned num_mrt_draw_calls;
1053 unsigned num_prim_restart_calls;
1054 unsigned num_spill_draw_calls;
1055 unsigned num_compute_calls;
1056 unsigned num_spill_compute_calls;
1057 unsigned num_dma_calls;
1058 unsigned num_cp_dma_calls;
1059 unsigned num_vs_flushes;
1060 unsigned num_ps_flushes;
1061 unsigned num_cs_flushes;
1062 unsigned num_cb_cache_flushes;
1063 unsigned num_db_cache_flushes;
1064 unsigned num_L2_invalidates;
1065 unsigned num_L2_writebacks;
1066 unsigned num_resident_handles;
1067 uint64_t num_alloc_tex_transfer_bytes;
1068 unsigned last_tex_ps_draw_ratio; /* for query */
1069 unsigned context_roll_counter;
1070
1071 /* Queries. */
1072 /* Maintain the list of active queries for pausing between IBs. */
1073 int num_occlusion_queries;
1074 int num_perfect_occlusion_queries;
1075 struct list_head active_queries;
1076 unsigned num_cs_dw_queries_suspend;
1077
1078 /* Render condition. */
1079 struct pipe_query *render_cond;
1080 unsigned render_cond_mode;
1081 bool render_cond_invert;
1082 bool render_cond_force_off; /* for u_blitter */
1083
1084 /* Statistics gathering for the DCC enablement heuristic. It can't be
1085 * in si_texture because si_texture can be shared by multiple
1086 * contexts. This is for back buffers only. We shouldn't get too many
1087 * of those.
1088 *
1089 * X11 DRI3 rotates among a finite set of back buffers. They should
1090 * all fit in this array. If they don't, separate DCC might never be
1091 * enabled by DCC stat gathering.
1092 */
1093 struct {
1094 struct si_texture *tex;
1095 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1096 struct pipe_query *ps_stats[3];
1097 /* If all slots are used and another slot is needed,
1098 * the least recently used slot is evicted based on this. */
1099 int64_t last_use_timestamp;
1100 bool query_active;
1101 } dcc_stats[5];
1102
1103 /* Copy one resource to another using async DMA. */
1104 void (*dma_copy)(struct pipe_context *ctx,
1105 struct pipe_resource *dst,
1106 unsigned dst_level,
1107 unsigned dst_x, unsigned dst_y, unsigned dst_z,
1108 struct pipe_resource *src,
1109 unsigned src_level,
1110 const struct pipe_box *src_box);
1111
1112 struct si_tracked_regs tracked_regs;
1113 };
1114
1115 /* cik_sdma.c */
1116 void cik_init_sdma_functions(struct si_context *sctx);
1117
1118 /* si_blit.c */
1119 enum si_blitter_op /* bitmask */
1120 {
1121 SI_SAVE_TEXTURES = 1,
1122 SI_SAVE_FRAMEBUFFER = 2,
1123 SI_SAVE_FRAGMENT_STATE = 4,
1124 SI_DISABLE_RENDER_COND = 8,
1125 };
1126
1127 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1128 void si_blitter_end(struct si_context *sctx);
1129 void si_init_blit_functions(struct si_context *sctx);
1130 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1131 void si_resource_copy_region(struct pipe_context *ctx,
1132 struct pipe_resource *dst,
1133 unsigned dst_level,
1134 unsigned dstx, unsigned dsty, unsigned dstz,
1135 struct pipe_resource *src,
1136 unsigned src_level,
1137 const struct pipe_box *src_box);
1138 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1139 void si_blit_decompress_depth(struct pipe_context *ctx,
1140 struct si_texture *texture,
1141 struct si_texture *staging,
1142 unsigned first_level, unsigned last_level,
1143 unsigned first_layer, unsigned last_layer,
1144 unsigned first_sample, unsigned last_sample);
1145
1146 /* si_buffer.c */
1147 bool si_rings_is_buffer_referenced(struct si_context *sctx,
1148 struct pb_buffer *buf,
1149 enum radeon_bo_usage usage);
1150 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
1151 struct si_resource *resource,
1152 unsigned usage);
1153 void si_init_resource_fields(struct si_screen *sscreen,
1154 struct si_resource *res,
1155 uint64_t size, unsigned alignment);
1156 bool si_alloc_resource(struct si_screen *sscreen,
1157 struct si_resource *res);
1158 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
1159 unsigned flags, unsigned usage,
1160 unsigned size, unsigned alignment);
1161 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen,
1162 unsigned flags, unsigned usage,
1163 unsigned size, unsigned alignment);
1164 void si_replace_buffer_storage(struct pipe_context *ctx,
1165 struct pipe_resource *dst,
1166 struct pipe_resource *src);
1167 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1168 void si_init_buffer_functions(struct si_context *sctx);
1169
1170 /* si_clear.c */
1171 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1172 bool vi_alpha_is_on_msb(enum pipe_format format);
1173 void vi_dcc_clear_level(struct si_context *sctx,
1174 struct si_texture *tex,
1175 unsigned level, unsigned clear_value);
1176 void si_init_clear_functions(struct si_context *sctx);
1177
1178 /* si_compute_blit.c */
1179 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1180 enum si_cache_policy cache_policy);
1181 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1182 uint64_t offset, uint64_t size, uint32_t *clear_value,
1183 uint32_t clear_value_size, enum si_coherency coher);
1184 void si_copy_buffer(struct si_context *sctx,
1185 struct pipe_resource *dst, struct pipe_resource *src,
1186 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1187 void si_compute_copy_image(struct si_context *sctx,
1188 struct pipe_resource *dst,
1189 unsigned dst_level,
1190 struct pipe_resource *src,
1191 unsigned src_level,
1192 unsigned dstx, unsigned dsty, unsigned dstz,
1193 const struct pipe_box *src_box);
1194 void si_compute_clear_render_target(struct pipe_context *ctx,
1195 struct pipe_surface *dstsurf,
1196 const union pipe_color_union *color,
1197 unsigned dstx, unsigned dsty,
1198 unsigned width, unsigned height,
1199 bool render_condition_enabled);
1200 void si_init_compute_blit_functions(struct si_context *sctx);
1201
1202 /* si_cp_dma.c */
1203 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1204 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1205 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1206 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1207 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1208 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1209 SI_CPDMA_SKIP_SYNC_AFTER | \
1210 SI_CPDMA_SKIP_SYNC_BEFORE | \
1211 SI_CPDMA_SKIP_GFX_SYNC | \
1212 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1213
1214 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1215 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1216 struct pipe_resource *dst, uint64_t offset,
1217 uint64_t size, unsigned value, unsigned user_flags,
1218 enum si_coherency coher, enum si_cache_policy cache_policy);
1219 void si_cp_dma_copy_buffer(struct si_context *sctx,
1220 struct pipe_resource *dst, struct pipe_resource *src,
1221 uint64_t dst_offset, uint64_t src_offset, unsigned size,
1222 unsigned user_flags, enum si_coherency coher,
1223 enum si_cache_policy cache_policy);
1224 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
1225 uint64_t offset, unsigned size);
1226 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1227 void si_test_gds(struct si_context *sctx);
1228 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf,
1229 unsigned offset, unsigned size, unsigned dst_sel,
1230 unsigned engine, const void *data);
1231
1232 /* si_debug.c */
1233 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
1234 struct radeon_saved_cs *saved, bool get_buffer_list);
1235 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1236 void si_destroy_saved_cs(struct si_saved_cs *scs);
1237 void si_auto_log_cs(void *data, struct u_log_context *log);
1238 void si_log_hw_flush(struct si_context *sctx);
1239 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1240 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1241 void si_init_debug_functions(struct si_context *sctx);
1242 void si_check_vm_faults(struct si_context *sctx,
1243 struct radeon_saved_cs *saved, enum ring_type ring);
1244 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
1245
1246 /* si_dma.c */
1247 void si_init_dma_functions(struct si_context *sctx);
1248
1249 /* si_dma_cs.c */
1250 void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst,
1251 uint64_t offset);
1252 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1253 uint64_t offset, uint64_t size, unsigned clear_value);
1254 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
1255 struct si_resource *dst, struct si_resource *src);
1256 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
1257 struct pipe_fence_handle **fence);
1258 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
1259 uint64_t offset, uint64_t size, unsigned value);
1260
1261 /* si_fence.c */
1262 void si_cp_release_mem(struct si_context *ctx,
1263 unsigned event, unsigned event_flags,
1264 unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1265 struct si_resource *buf, uint64_t va,
1266 uint32_t new_fence, unsigned query_type);
1267 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1268 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1269 uint64_t va, uint32_t ref, uint32_t mask, unsigned flags);
1270 void si_init_fence_functions(struct si_context *ctx);
1271 void si_init_screen_fence_functions(struct si_screen *screen);
1272 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1273 struct tc_unflushed_batch_token *tc_token);
1274
1275 /* si_get.c */
1276 void si_init_screen_get_functions(struct si_screen *sscreen);
1277
1278 /* si_gfx_cs.c */
1279 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
1280 struct pipe_fence_handle **fence);
1281 void si_begin_new_gfx_cs(struct si_context *ctx);
1282 void si_need_gfx_cs_space(struct si_context *ctx);
1283
1284 /* si_gpu_load.c */
1285 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1286 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1287 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
1288 uint64_t begin);
1289
1290 /* si_compute.c */
1291 void si_init_compute_functions(struct si_context *sctx);
1292
1293 /* si_perfcounters.c */
1294 void si_init_perfcounters(struct si_screen *screen);
1295 void si_destroy_perfcounters(struct si_screen *screen);
1296
1297 /* si_pipe.c */
1298 bool si_check_device_reset(struct si_context *sctx);
1299
1300 /* si_query.c */
1301 void si_init_screen_query_functions(struct si_screen *sscreen);
1302 void si_init_query_functions(struct si_context *sctx);
1303 void si_suspend_queries(struct si_context *sctx);
1304 void si_resume_queries(struct si_context *sctx);
1305
1306 /* si_shaderlib_tgsi.c */
1307 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1308 unsigned num_layers);
1309 void *si_create_fixed_func_tcs(struct si_context *sctx);
1310 void *si_create_dma_compute_shader(struct pipe_context *ctx,
1311 unsigned num_dwords_per_thread,
1312 bool dst_stream_cache_policy, bool is_copy);
1313 void *si_create_copy_image_compute_shader(struct pipe_context *ctx);
1314 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx);
1315 void *si_clear_render_target_shader(struct pipe_context *ctx);
1316 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
1317 void *si_create_query_result_cs(struct si_context *sctx);
1318
1319 /* si_test_dma.c */
1320 void si_test_dma(struct si_screen *sscreen);
1321
1322 /* si_test_clearbuffer.c */
1323 void si_test_dma_perf(struct si_screen *sscreen);
1324
1325 /* si_uvd.c */
1326 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1327 const struct pipe_video_codec *templ);
1328
1329 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1330 const struct pipe_video_buffer *tmpl);
1331
1332 /* si_viewport.c */
1333 void si_update_vs_viewport_state(struct si_context *ctx);
1334 void si_init_viewport_functions(struct si_context *ctx);
1335
1336 /* si_texture.c */
1337 bool si_prepare_for_dma_blit(struct si_context *sctx,
1338 struct si_texture *dst,
1339 unsigned dst_level, unsigned dstx,
1340 unsigned dsty, unsigned dstz,
1341 struct si_texture *src,
1342 unsigned src_level,
1343 const struct pipe_box *src_box);
1344 void si_eliminate_fast_color_clear(struct si_context *sctx,
1345 struct si_texture *tex);
1346 void si_texture_discard_cmask(struct si_screen *sscreen,
1347 struct si_texture *tex);
1348 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1349 struct pipe_resource *texture,
1350 struct si_texture **staging);
1351 void si_print_texture_info(struct si_screen *sscreen,
1352 struct si_texture *tex, struct u_log_context *log);
1353 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1354 const struct pipe_resource *templ);
1355 bool vi_dcc_formats_compatible(enum pipe_format format1,
1356 enum pipe_format format2);
1357 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1358 unsigned level,
1359 enum pipe_format view_format);
1360 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1361 struct pipe_resource *tex,
1362 unsigned level,
1363 enum pipe_format view_format);
1364 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1365 struct pipe_resource *texture,
1366 const struct pipe_surface *templ,
1367 unsigned width0, unsigned height0,
1368 unsigned width, unsigned height);
1369 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1370 void vi_separate_dcc_try_enable(struct si_context *sctx,
1371 struct si_texture *tex);
1372 void vi_separate_dcc_start_query(struct si_context *sctx,
1373 struct si_texture *tex);
1374 void vi_separate_dcc_stop_query(struct si_context *sctx,
1375 struct si_texture *tex);
1376 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1377 struct si_texture *tex);
1378 bool si_texture_disable_dcc(struct si_context *sctx,
1379 struct si_texture *tex);
1380 void si_init_screen_texture_functions(struct si_screen *sscreen);
1381 void si_init_context_texture_functions(struct si_context *sctx);
1382
1383
1384 /*
1385 * common helpers
1386 */
1387
1388 static inline struct si_resource *si_resource(struct pipe_resource *r)
1389 {
1390 return (struct si_resource*)r;
1391 }
1392
1393 static inline void
1394 si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1395 {
1396 pipe_resource_reference((struct pipe_resource **)ptr,
1397 (struct pipe_resource *)res);
1398 }
1399
1400 static inline void
1401 si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1402 {
1403 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1404 }
1405
1406 static inline bool
1407 vi_dcc_enabled(struct si_texture *tex, unsigned level)
1408 {
1409 return tex->dcc_offset && level < tex->surface.num_dcc_levels;
1410 }
1411
1412 static inline unsigned
1413 si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1414 {
1415 if (stencil)
1416 return tex->surface.u.legacy.stencil_tiling_index[level];
1417 else
1418 return tex->surface.u.legacy.tiling_index[level];
1419 }
1420
1421 static inline void
1422 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1423 {
1424 if (r) {
1425 /* Add memory usage for need_gfx_cs_space */
1426 sctx->vram += si_resource(r)->vram_usage;
1427 sctx->gtt += si_resource(r)->gart_usage;
1428 }
1429 }
1430
1431 static inline void
1432 si_invalidate_draw_sh_constants(struct si_context *sctx)
1433 {
1434 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1435 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1436 }
1437
1438 static inline unsigned
1439 si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1440 {
1441 return 1 << (atom - sctx->atoms.array);
1442 }
1443
1444 static inline void
1445 si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1446 {
1447 unsigned bit = si_get_atom_bit(sctx, atom);
1448
1449 if (dirty)
1450 sctx->dirty_atoms |= bit;
1451 else
1452 sctx->dirty_atoms &= ~bit;
1453 }
1454
1455 static inline bool
1456 si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1457 {
1458 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1459 }
1460
1461 static inline void
1462 si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1463 {
1464 si_set_atom_dirty(sctx, atom, true);
1465 }
1466
1467 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1468 {
1469 if (sctx->gs_shader.cso)
1470 return &sctx->gs_shader;
1471 if (sctx->tes_shader.cso)
1472 return &sctx->tes_shader;
1473
1474 return &sctx->vs_shader;
1475 }
1476
1477 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1478 {
1479 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1480
1481 return vs->cso ? &vs->cso->info : NULL;
1482 }
1483
1484 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1485 {
1486 if (sctx->gs_shader.cso)
1487 return sctx->gs_shader.cso->gs_copy_shader;
1488
1489 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1490 return vs->current ? vs->current : NULL;
1491 }
1492
1493 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1494 unsigned processor)
1495 {
1496 return sscreen->debug_flags & (1 << processor);
1497 }
1498
1499 static inline bool si_get_strmout_en(struct si_context *sctx)
1500 {
1501 return sctx->streamout.streamout_enabled ||
1502 sctx->streamout.prims_gen_query_enabled;
1503 }
1504
1505 static inline unsigned
1506 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1507 {
1508 unsigned alignment, tcc_cache_line_size;
1509
1510 /* If the upload size is less than the cache line size (e.g. 16, 32),
1511 * the whole thing will fit into a cache line if we align it to its size.
1512 * The idea is that multiple small uploads can share a cache line.
1513 * If the upload size is greater, align it to the cache line size.
1514 */
1515 alignment = util_next_power_of_two(upload_size);
1516 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1517 return MIN2(alignment, tcc_cache_line_size);
1518 }
1519
1520 static inline void
1521 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1522 {
1523 if (pipe_reference(&(*dst)->reference, &src->reference))
1524 si_destroy_saved_cs(*dst);
1525
1526 *dst = src;
1527 }
1528
1529 static inline void
1530 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1531 bool shaders_read_metadata)
1532 {
1533 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1534 SI_CONTEXT_INV_VMEM_L1;
1535
1536 if (sctx->chip_class >= GFX9) {
1537 /* Single-sample color is coherent with shaders on GFX9, but
1538 * L2 metadata must be flushed if shaders read metadata.
1539 * (DCC, CMASK).
1540 */
1541 if (num_samples >= 2)
1542 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1543 else if (shaders_read_metadata)
1544 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1545 } else {
1546 /* SI-CI-VI */
1547 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1548 }
1549 }
1550
1551 static inline void
1552 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1553 bool include_stencil, bool shaders_read_metadata)
1554 {
1555 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1556 SI_CONTEXT_INV_VMEM_L1;
1557
1558 if (sctx->chip_class >= GFX9) {
1559 /* Single-sample depth (not stencil) is coherent with shaders
1560 * on GFX9, but L2 metadata must be flushed if shaders read
1561 * metadata.
1562 */
1563 if (num_samples >= 2 || include_stencil)
1564 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1565 else if (shaders_read_metadata)
1566 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1567 } else {
1568 /* SI-CI-VI */
1569 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1570 }
1571 }
1572
1573 static inline bool
1574 si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1575 {
1576 return (stencil_sampler && tex->can_sample_s) ||
1577 (!stencil_sampler && tex->can_sample_z);
1578 }
1579
1580 static inline bool
1581 si_htile_enabled(struct si_texture *tex, unsigned level)
1582 {
1583 return tex->htile_offset && level == 0;
1584 }
1585
1586 static inline bool
1587 vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level)
1588 {
1589 assert(!tex->tc_compatible_htile || tex->htile_offset);
1590 return tex->tc_compatible_htile && level == 0;
1591 }
1592
1593 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1594 {
1595 if (sctx->ps_uses_fbfetch)
1596 return sctx->framebuffer.nr_color_samples;
1597
1598 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1599 }
1600
1601 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1602 {
1603 if (sctx->queued.named.rasterizer->rasterizer_discard)
1604 return 0;
1605
1606 struct si_shader_selector *ps = sctx->ps_shader.cso;
1607 if (!ps)
1608 return 0;
1609
1610 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1611 sctx->queued.named.blend->cb_target_mask;
1612
1613 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1614 colormask &= ps->colors_written_4bit;
1615 else if (!ps->colors_written_4bit)
1616 colormask = 0; /* color0 writes all cbufs, but it's not written */
1617
1618 return colormask;
1619 }
1620
1621 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1622 (1 << PIPE_PRIM_LINE_LOOP) | \
1623 (1 << PIPE_PRIM_LINE_STRIP) | \
1624 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1625 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1626
1627 static inline bool util_prim_is_lines(unsigned prim)
1628 {
1629 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1630 }
1631
1632 static inline bool util_prim_is_points_or_lines(unsigned prim)
1633 {
1634 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES |
1635 (1 << PIPE_PRIM_POINTS))) != 0;
1636 }
1637
1638 /**
1639 * Return true if there is enough memory in VRAM and GTT for the buffers
1640 * added so far.
1641 *
1642 * \param vram VRAM memory size not added to the buffer list yet
1643 * \param gtt GTT memory size not added to the buffer list yet
1644 */
1645 static inline bool
1646 radeon_cs_memory_below_limit(struct si_screen *screen,
1647 struct radeon_cmdbuf *cs,
1648 uint64_t vram, uint64_t gtt)
1649 {
1650 vram += cs->used_vram;
1651 gtt += cs->used_gart;
1652
1653 /* Anything that goes above the VRAM size should go to GTT. */
1654 if (vram > screen->info.vram_size)
1655 gtt += vram - screen->info.vram_size;
1656
1657 /* Now we just need to check if we have enough GTT. */
1658 return gtt < screen->info.gart_size * 0.7;
1659 }
1660
1661 /**
1662 * Add a buffer to the buffer list for the given command stream (CS).
1663 *
1664 * All buffers used by a CS must be added to the list. This tells the kernel
1665 * driver which buffers are used by GPU commands. Other buffers can
1666 * be swapped out (not accessible) during execution.
1667 *
1668 * The buffer list becomes empty after every context flush and must be
1669 * rebuilt.
1670 */
1671 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1672 struct radeon_cmdbuf *cs,
1673 struct si_resource *bo,
1674 enum radeon_bo_usage usage,
1675 enum radeon_bo_priority priority)
1676 {
1677 assert(usage);
1678 sctx->ws->cs_add_buffer(
1679 cs, bo->buf,
1680 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1681 bo->domains, priority);
1682 }
1683
1684 /**
1685 * Same as above, but also checks memory usage and flushes the context
1686 * accordingly.
1687 *
1688 * When this SHOULD NOT be used:
1689 *
1690 * - if si_context_add_resource_size has been called for the buffer
1691 * followed by *_need_cs_space for checking the memory usage
1692 *
1693 * - if si_need_dma_space has been called for the buffer
1694 *
1695 * - when emitting state packets and draw packets (because preceding packets
1696 * can't be re-emitted at that point)
1697 *
1698 * - if shader resource "enabled_mask" is not up-to-date or there is
1699 * a different constraint disallowing a context flush
1700 */
1701 static inline void
1702 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1703 struct si_resource *bo,
1704 enum radeon_bo_usage usage,
1705 enum radeon_bo_priority priority,
1706 bool check_mem)
1707 {
1708 if (check_mem &&
1709 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1710 sctx->vram + bo->vram_usage,
1711 sctx->gtt + bo->gart_usage))
1712 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1713
1714 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority);
1715 }
1716
1717 #define PRINT_ERR(fmt, args...) \
1718 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1719
1720 #endif