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[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
34
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
37 #else
38 #define SI_BIG_ENDIAN 0
39 #endif
40
41 #define ATI_VENDOR_ID 0x1002
42 #define SI_PRIM_DISCARD_DEBUG 0
43 #define SI_NOT_QUERY 0xffffffff
44
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
56
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
61
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
69 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
70 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
71 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
72 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
73 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
74 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
75 * invalidate L2. GFX6-GFX7 can't do it, so they will do complete invalidation. */
76 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
77 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
78 * a CB or DB flush. */
79 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
80 /* Framebuffer caches. */
81 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
82 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
83 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
84 /* Engine synchronization. */
85 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
86 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
87 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
88 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
89 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
90
91 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
92 #define SI_PREFETCH_LS (1 << 1)
93 #define SI_PREFETCH_HS (1 << 2)
94 #define SI_PREFETCH_ES (1 << 3)
95 #define SI_PREFETCH_GS (1 << 4)
96 #define SI_PREFETCH_VS (1 << 5)
97 #define SI_PREFETCH_PS (1 << 6)
98
99 #define SI_MAX_BORDER_COLORS 4096
100 #define SI_MAX_VIEWPORTS 16
101 #define SIX_BITS 0x3F
102 #define SI_MAP_BUFFER_ALIGNMENT 64
103 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
104
105 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
106 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
107 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
108 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
109 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
110 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
111 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
112 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
113 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
114 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
115
116 enum si_clear_code
117 {
118 DCC_CLEAR_COLOR_0000 = 0x00000000,
119 DCC_CLEAR_COLOR_0001 = 0x40404040,
120 DCC_CLEAR_COLOR_1110 = 0x80808080,
121 DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
122 DCC_CLEAR_COLOR_REG = 0x20202020,
123 DCC_UNCOMPRESSED = 0xFFFFFFFF,
124 };
125
126 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
127
128 /* Debug flags. */
129 enum {
130 /* Shader logging options: */
131 DBG_VS = PIPE_SHADER_VERTEX,
132 DBG_PS = PIPE_SHADER_FRAGMENT,
133 DBG_GS = PIPE_SHADER_GEOMETRY,
134 DBG_TCS = PIPE_SHADER_TESS_CTRL,
135 DBG_TES = PIPE_SHADER_TESS_EVAL,
136 DBG_CS = PIPE_SHADER_COMPUTE,
137 DBG_NO_IR,
138 DBG_NO_TGSI,
139 DBG_NO_ASM,
140 DBG_PREOPT_IR,
141
142 /* Shader compiler options the shader cache should be aware of: */
143 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
144 DBG_UNSAFE_MATH,
145 DBG_SI_SCHED,
146 DBG_GISEL,
147
148 /* Shader compiler options (with no effect on the shader cache): */
149 DBG_CHECK_IR,
150 DBG_MONOLITHIC_SHADERS,
151 DBG_NO_OPT_VARIANT,
152
153 /* Information logging options: */
154 DBG_INFO,
155 DBG_TEX,
156 DBG_COMPUTE,
157 DBG_VM,
158
159 /* Driver options: */
160 DBG_FORCE_DMA,
161 DBG_NO_ASYNC_DMA,
162 DBG_NO_WC,
163 DBG_CHECK_VM,
164 DBG_RESERVE_VMID,
165 DBG_ZERO_VRAM,
166
167 /* 3D engine options: */
168 DBG_ALWAYS_PD,
169 DBG_PD,
170 DBG_NO_PD,
171 DBG_SWITCH_ON_EOP,
172 DBG_NO_OUT_OF_ORDER,
173 DBG_NO_DPBB,
174 DBG_NO_DFSM,
175 DBG_DPBB,
176 DBG_DFSM,
177 DBG_NO_HYPERZ,
178 DBG_NO_RB_PLUS,
179 DBG_NO_2D_TILING,
180 DBG_NO_TILING,
181 DBG_NO_DCC,
182 DBG_NO_DCC_CLEAR,
183 DBG_NO_DCC_FB,
184 DBG_NO_DCC_MSAA,
185 DBG_NO_FMASK,
186
187 /* Tests: */
188 DBG_TEST_DMA,
189 DBG_TEST_VMFAULT_CP,
190 DBG_TEST_VMFAULT_SDMA,
191 DBG_TEST_VMFAULT_SHADER,
192 DBG_TEST_DMA_PERF,
193 DBG_TEST_GDS,
194 DBG_TEST_GDS_MM,
195 DBG_TEST_GDS_OA_MM,
196 };
197
198 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
199 #define DBG(name) (1ull << DBG_##name)
200
201 enum si_cache_policy {
202 L2_BYPASS,
203 L2_STREAM, /* same as SLC=1 */
204 L2_LRU, /* same as SLC=0 */
205 };
206
207 enum si_coherency {
208 SI_COHERENCY_NONE, /* no cache flushes needed */
209 SI_COHERENCY_SHADER,
210 SI_COHERENCY_CB_META,
211 SI_COHERENCY_CP,
212 };
213
214 struct si_compute;
215 struct si_shader_context;
216 struct hash_table;
217 struct u_suballocator;
218
219 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
220 * at the moment.
221 */
222 struct si_resource {
223 struct threaded_resource b;
224
225 /* Winsys objects. */
226 struct pb_buffer *buf;
227 uint64_t gpu_address;
228 /* Memory usage if the buffer placement is optimal. */
229 uint64_t vram_usage;
230 uint64_t gart_usage;
231
232 /* Resource properties. */
233 uint64_t bo_size;
234 unsigned bo_alignment;
235 enum radeon_bo_domain domains;
236 enum radeon_bo_flag flags;
237 unsigned bind_history;
238 int max_forced_staging_uploads;
239
240 /* The buffer range which is initialized (with a write transfer,
241 * streamout, DMA, or as a random access target). The rest of
242 * the buffer is considered invalid and can be mapped unsynchronized.
243 *
244 * This allows unsychronized mapping of a buffer range which hasn't
245 * been used yet. It's for applications which forget to use
246 * the unsynchronized map flag and expect the driver to figure it out.
247 */
248 struct util_range valid_buffer_range;
249
250 /* For buffers only. This indicates that a write operation has been
251 * performed by TC L2, but the cache hasn't been flushed.
252 * Any hw block which doesn't use or bypasses TC L2 should check this
253 * flag and flush the cache before using the buffer.
254 *
255 * For example, TC L2 must be flushed if a buffer which has been
256 * modified by a shader store instruction is about to be used as
257 * an index buffer. The reason is that VGT DMA index fetching doesn't
258 * use TC L2.
259 */
260 bool TC_L2_dirty;
261
262 /* Whether this resource is referenced by bindless handles. */
263 bool texture_handle_allocated;
264 bool image_handle_allocated;
265
266 /* Whether the resource has been exported via resource_get_handle. */
267 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
268 };
269
270 struct si_transfer {
271 struct threaded_transfer b;
272 struct si_resource *staging;
273 unsigned offset;
274 };
275
276 struct si_texture {
277 struct si_resource buffer;
278
279 struct radeon_surf surface;
280 uint64_t size;
281 struct si_texture *flushed_depth_texture;
282
283 /* One texture allocation can contain these buffers:
284 * - image (pixel data)
285 * - FMASK buffer (MSAA compression)
286 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
287 * - HTILE buffer (Z/S compression and fast Z/S clear)
288 * - DCC buffer (color compression and new fast color clear)
289 * - displayable DCC buffer (if the DCC buffer is not displayable)
290 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
291 */
292 uint64_t fmask_offset;
293 uint64_t cmask_offset;
294 uint64_t cmask_base_address_reg;
295 struct si_resource *cmask_buffer;
296 uint64_t dcc_offset; /* 0 = disabled */
297 uint64_t display_dcc_offset;
298 uint64_t dcc_retile_map_offset;
299 unsigned cb_color_info; /* fast clear enable bit */
300 unsigned color_clear_value[2];
301 unsigned last_msaa_resolve_target_micro_mode;
302 unsigned num_level0_transfers;
303
304 /* Depth buffer compression and fast clear. */
305 uint64_t htile_offset;
306 float depth_clear_value;
307 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
308 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
309 enum pipe_format db_render_format:16;
310 uint8_t stencil_clear_value;
311 bool tc_compatible_htile:1;
312 bool depth_cleared:1; /* if it was cleared at least once */
313 bool stencil_cleared:1; /* if it was cleared at least once */
314 bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
315 bool is_depth:1;
316 bool db_compatible:1;
317 bool can_sample_z:1;
318 bool can_sample_s:1;
319
320 /* We need to track DCC dirtiness, because st/dri usually calls
321 * flush_resource twice per frame (not a bug) and we don't wanna
322 * decompress DCC twice. Also, the dirty tracking must be done even
323 * if DCC isn't used, because it's required by the DCC usage analysis
324 * for a possible future enablement.
325 */
326 bool separate_dcc_dirty:1;
327 /* Statistics gathering for the DCC enablement heuristic. */
328 bool dcc_gather_statistics:1;
329 /* Counter that should be non-zero if the texture is bound to a
330 * framebuffer.
331 */
332 unsigned framebuffers_bound;
333 /* Whether the texture is a displayable back buffer and needs DCC
334 * decompression, which is expensive. Therefore, it's enabled only
335 * if statistics suggest that it will pay off and it's allocated
336 * separately. It can't be bound as a sampler by apps. Limited to
337 * target == 2D and last_level == 0. If enabled, dcc_offset contains
338 * the absolute GPUVM address, not the relative one.
339 */
340 struct si_resource *dcc_separate_buffer;
341 /* When DCC is temporarily disabled, the separate buffer is here. */
342 struct si_resource *last_dcc_separate_buffer;
343 /* Estimate of how much this color buffer is written to in units of
344 * full-screen draws: ps_invocations / (width * height)
345 * Shader kills, late Z, and blending with trivial discards make it
346 * inaccurate (we need to count CB updates, not PS invocations).
347 */
348 unsigned ps_draw_ratio;
349 /* The number of clears since the last DCC usage analysis. */
350 unsigned num_slow_clears;
351 };
352
353 struct si_surface {
354 struct pipe_surface base;
355
356 /* These can vary with block-compressed textures. */
357 uint16_t width0;
358 uint16_t height0;
359
360 bool color_initialized:1;
361 bool depth_initialized:1;
362
363 /* Misc. color flags. */
364 bool color_is_int8:1;
365 bool color_is_int10:1;
366 bool dcc_incompatible:1;
367
368 /* Color registers. */
369 unsigned cb_color_info;
370 unsigned cb_color_view;
371 unsigned cb_color_attrib;
372 unsigned cb_color_attrib2; /* GFX9 and later */
373 unsigned cb_dcc_control; /* GFX8 and later */
374 unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */
375 unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
376 unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
377 unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
378
379 /* DB registers. */
380 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
381 uint64_t db_stencil_base;
382 uint64_t db_htile_data_base;
383 unsigned db_depth_info;
384 unsigned db_z_info;
385 unsigned db_z_info2; /* GFX9+ */
386 unsigned db_depth_view;
387 unsigned db_depth_size;
388 unsigned db_depth_slice;
389 unsigned db_stencil_info;
390 unsigned db_stencil_info2; /* GFX9+ */
391 unsigned db_htile_surface;
392 };
393
394 struct si_mmio_counter {
395 unsigned busy;
396 unsigned idle;
397 };
398
399 union si_mmio_counters {
400 struct {
401 /* For global GPU load including SDMA. */
402 struct si_mmio_counter gpu;
403
404 /* GRBM_STATUS */
405 struct si_mmio_counter spi;
406 struct si_mmio_counter gui;
407 struct si_mmio_counter ta;
408 struct si_mmio_counter gds;
409 struct si_mmio_counter vgt;
410 struct si_mmio_counter ia;
411 struct si_mmio_counter sx;
412 struct si_mmio_counter wd;
413 struct si_mmio_counter bci;
414 struct si_mmio_counter sc;
415 struct si_mmio_counter pa;
416 struct si_mmio_counter db;
417 struct si_mmio_counter cp;
418 struct si_mmio_counter cb;
419
420 /* SRBM_STATUS2 */
421 struct si_mmio_counter sdma;
422
423 /* CP_STAT */
424 struct si_mmio_counter pfp;
425 struct si_mmio_counter meq;
426 struct si_mmio_counter me;
427 struct si_mmio_counter surf_sync;
428 struct si_mmio_counter cp_dma;
429 struct si_mmio_counter scratch_ram;
430 } named;
431 unsigned array[0];
432 };
433
434 struct si_memory_object {
435 struct pipe_memory_object b;
436 struct pb_buffer *buf;
437 uint32_t stride;
438 };
439
440 /* Saved CS data for debugging features. */
441 struct radeon_saved_cs {
442 uint32_t *ib;
443 unsigned num_dw;
444
445 struct radeon_bo_list_item *bo_list;
446 unsigned bo_count;
447 };
448
449 struct si_screen {
450 struct pipe_screen b;
451 struct radeon_winsys *ws;
452 struct disk_cache *disk_shader_cache;
453
454 struct radeon_info info;
455 uint64_t debug_flags;
456 char renderer_string[183];
457
458 unsigned pa_sc_raster_config;
459 unsigned pa_sc_raster_config_1;
460 unsigned se_tile_repeat;
461 unsigned gs_table_depth;
462 unsigned tess_offchip_block_dw_size;
463 unsigned tess_offchip_ring_size;
464 unsigned tess_factor_ring_size;
465 unsigned vgt_hs_offchip_param;
466 unsigned eqaa_force_coverage_samples;
467 unsigned eqaa_force_z_samples;
468 unsigned eqaa_force_color_samples;
469 bool has_clear_state;
470 bool has_distributed_tess;
471 bool has_draw_indirect_multi;
472 bool has_out_of_order_rast;
473 bool assume_no_z_fights;
474 bool commutative_blend_add;
475 bool has_gfx9_scissor_bug;
476 bool has_msaa_sample_loc_bug;
477 bool has_ls_vgpr_init_bug;
478 bool has_dcc_constant_encode;
479 bool dpbb_allowed;
480 bool dfsm_allowed;
481 bool llvm_has_working_vgpr_indexing;
482
483 struct {
484 #define OPT_BOOL(name, dflt, description) bool name:1;
485 #include "si_debug_options.h"
486 } options;
487
488 /* Whether shaders are monolithic (1-part) or separate (3-part). */
489 bool use_monolithic_shaders;
490 bool record_llvm_ir;
491 bool has_rbplus; /* if RB+ registers exist */
492 bool rbplus_allowed; /* if RB+ is allowed */
493 bool dcc_msaa_allowed;
494 bool cpdma_prefetch_writes_memory;
495
496 struct slab_parent_pool pool_transfers;
497
498 /* Texture filter settings. */
499 int force_aniso; /* -1 = disabled */
500
501 /* Auxiliary context. Mainly used to initialize resources.
502 * It must be locked prior to using and flushed before unlocking. */
503 struct pipe_context *aux_context;
504 mtx_t aux_context_lock;
505
506 /* This must be in the screen, because UE4 uses one context for
507 * compilation and another one for rendering.
508 */
509 unsigned num_compilations;
510 /* Along with ST_DEBUG=precompile, this should show if applications
511 * are loading shaders on demand. This is a monotonic counter.
512 */
513 unsigned num_shaders_created;
514 unsigned num_shader_cache_hits;
515
516 /* GPU load thread. */
517 mtx_t gpu_load_mutex;
518 thrd_t gpu_load_thread;
519 union si_mmio_counters mmio_counters;
520 volatile unsigned gpu_load_stop_thread; /* bool */
521
522 /* Performance counters. */
523 struct si_perfcounters *perfcounters;
524
525 /* If pipe_screen wants to recompute and re-emit the framebuffer,
526 * sampler, and image states of all contexts, it should atomically
527 * increment this.
528 *
529 * Each context will compare this with its own last known value of
530 * the counter before drawing and re-emit the states accordingly.
531 */
532 unsigned dirty_tex_counter;
533
534 /* Atomically increment this counter when an existing texture's
535 * metadata is enabled or disabled in a way that requires changing
536 * contexts' compressed texture binding masks.
537 */
538 unsigned compressed_colortex_counter;
539
540 struct {
541 /* Context flags to set so that all writes from earlier jobs
542 * in the CP are seen by L2 clients.
543 */
544 unsigned cp_to_L2;
545
546 /* Context flags to set so that all writes from earlier jobs
547 * that end in L2 are seen by CP.
548 */
549 unsigned L2_to_cp;
550 } barrier_flags;
551
552 mtx_t shader_parts_mutex;
553 struct si_shader_part *vs_prologs;
554 struct si_shader_part *tcs_epilogs;
555 struct si_shader_part *gs_prologs;
556 struct si_shader_part *ps_prologs;
557 struct si_shader_part *ps_epilogs;
558
559 /* Shader cache in memory.
560 *
561 * Design & limitations:
562 * - The shader cache is per screen (= per process), never saved to
563 * disk, and skips redundant shader compilations from TGSI to bytecode.
564 * - It can only be used with one-variant-per-shader support, in which
565 * case only the main (typically middle) part of shaders is cached.
566 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
567 * variants of VS and TES are cached, so LS and ES aren't.
568 * - GS and CS aren't cached, but it's certainly possible to cache
569 * those as well.
570 */
571 mtx_t shader_cache_mutex;
572 struct hash_table *shader_cache;
573
574 /* Shader compiler queue for multithreaded compilation. */
575 struct util_queue shader_compiler_queue;
576 /* Use at most 3 normal compiler threads on quadcore and better.
577 * Hyperthreaded CPUs report the number of threads, but we want
578 * the number of cores. We only need this many threads for shader-db. */
579 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
580
581 struct util_queue shader_compiler_queue_low_priority;
582 /* Use at most 2 low priority threads on quadcore and better.
583 * We want to minimize the impact on multithreaded Mesa. */
584 struct ac_llvm_compiler compiler_lowp[10];
585 };
586
587 struct si_blend_color {
588 struct pipe_blend_color state;
589 bool any_nonzeros;
590 };
591
592 struct si_sampler_view {
593 struct pipe_sampler_view base;
594 /* [0..7] = image descriptor
595 * [4..7] = buffer descriptor */
596 uint32_t state[8];
597 uint32_t fmask_state[8];
598 const struct legacy_surf_level *base_level_info;
599 ubyte base_level;
600 ubyte block_width;
601 bool is_stencil_sampler;
602 bool is_integer;
603 bool dcc_incompatible;
604 };
605
606 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
607
608 struct si_sampler_state {
609 #ifdef DEBUG
610 unsigned magic;
611 #endif
612 uint32_t val[4];
613 uint32_t integer_val[4];
614 uint32_t upgraded_depth_val[4];
615 };
616
617 struct si_cs_shader_state {
618 struct si_compute *program;
619 struct si_compute *emitted_program;
620 unsigned offset;
621 bool initialized;
622 bool uses_scratch;
623 };
624
625 struct si_samplers {
626 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
627 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
628
629 /* The i-th bit is set if that element is enabled (non-NULL resource). */
630 unsigned enabled_mask;
631 uint32_t needs_depth_decompress_mask;
632 uint32_t needs_color_decompress_mask;
633 };
634
635 struct si_images {
636 struct pipe_image_view views[SI_NUM_IMAGES];
637 uint32_t needs_color_decompress_mask;
638 unsigned enabled_mask;
639 };
640
641 struct si_framebuffer {
642 struct pipe_framebuffer_state state;
643 unsigned colorbuf_enabled_4bit;
644 unsigned spi_shader_col_format;
645 unsigned spi_shader_col_format_alpha;
646 unsigned spi_shader_col_format_blend;
647 unsigned spi_shader_col_format_blend_alpha;
648 ubyte nr_samples:5; /* at most 16xAA */
649 ubyte log_samples:3; /* at most 4 = 16xAA */
650 ubyte nr_color_samples; /* at most 8xAA */
651 ubyte compressed_cb_mask;
652 ubyte uncompressed_cb_mask;
653 ubyte color_is_int8;
654 ubyte color_is_int10;
655 ubyte dirty_cbufs;
656 ubyte dcc_overwrite_combiner_watermark;
657 bool dirty_zsbuf;
658 bool any_dst_linear;
659 bool CB_has_shader_readable_metadata;
660 bool DB_has_shader_readable_metadata;
661 bool all_DCC_pipe_aligned;
662 };
663
664 enum si_quant_mode {
665 /* This is the list we want to support. */
666 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
667 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
668 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
669 };
670
671 struct si_signed_scissor {
672 int minx;
673 int miny;
674 int maxx;
675 int maxy;
676 enum si_quant_mode quant_mode;
677 };
678
679 struct si_viewports {
680 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
681 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
682 bool y_inverted;
683 };
684
685 struct si_clip_state {
686 struct pipe_clip_state state;
687 bool any_nonzeros;
688 };
689
690 struct si_streamout_target {
691 struct pipe_stream_output_target b;
692
693 /* The buffer where BUFFER_FILLED_SIZE is stored. */
694 struct si_resource *buf_filled_size;
695 unsigned buf_filled_size_offset;
696 bool buf_filled_size_valid;
697
698 unsigned stride_in_dw;
699 };
700
701 struct si_streamout {
702 bool begin_emitted;
703
704 unsigned enabled_mask;
705 unsigned num_targets;
706 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
707
708 unsigned append_bitmask;
709 bool suspended;
710
711 /* External state which comes from the vertex shader,
712 * it must be set explicitly when binding a shader. */
713 uint16_t *stride_in_dw;
714 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
715
716 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
717 unsigned hw_enabled_mask;
718
719 /* The state of VGT_STRMOUT_(CONFIG|EN). */
720 bool streamout_enabled;
721 bool prims_gen_query_enabled;
722 int num_prims_gen_queries;
723 };
724
725 /* A shader state consists of the shader selector, which is a constant state
726 * object shared by multiple contexts and shouldn't be modified, and
727 * the current shader variant selected for this context.
728 */
729 struct si_shader_ctx_state {
730 struct si_shader_selector *cso;
731 struct si_shader *current;
732 };
733
734 #define SI_NUM_VGT_PARAM_KEY_BITS 12
735 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
736
737 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
738 * Some fields are set by state-change calls, most are set by draw_vbo.
739 */
740 union si_vgt_param_key {
741 struct {
742 #ifdef PIPE_ARCH_LITTLE_ENDIAN
743 unsigned prim:4;
744 unsigned uses_instancing:1;
745 unsigned multi_instances_smaller_than_primgroup:1;
746 unsigned primitive_restart:1;
747 unsigned count_from_stream_output:1;
748 unsigned line_stipple_enabled:1;
749 unsigned uses_tess:1;
750 unsigned tess_uses_prim_id:1;
751 unsigned uses_gs:1;
752 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
753 #else /* PIPE_ARCH_BIG_ENDIAN */
754 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
755 unsigned uses_gs:1;
756 unsigned tess_uses_prim_id:1;
757 unsigned uses_tess:1;
758 unsigned line_stipple_enabled:1;
759 unsigned count_from_stream_output:1;
760 unsigned primitive_restart:1;
761 unsigned multi_instances_smaller_than_primgroup:1;
762 unsigned uses_instancing:1;
763 unsigned prim:4;
764 #endif
765 } u;
766 uint32_t index;
767 };
768
769 struct si_texture_handle
770 {
771 unsigned desc_slot;
772 bool desc_dirty;
773 struct pipe_sampler_view *view;
774 struct si_sampler_state sstate;
775 };
776
777 struct si_image_handle
778 {
779 unsigned desc_slot;
780 bool desc_dirty;
781 struct pipe_image_view view;
782 };
783
784 struct si_saved_cs {
785 struct pipe_reference reference;
786 struct si_context *ctx;
787 struct radeon_saved_cs gfx;
788 struct radeon_saved_cs compute;
789 struct si_resource *trace_buf;
790 unsigned trace_id;
791
792 unsigned gfx_last_dw;
793 unsigned compute_last_dw;
794 bool flushed;
795 int64_t time_flush;
796 };
797
798 struct si_sdma_upload {
799 struct si_resource *dst;
800 struct si_resource *src;
801 unsigned src_offset;
802 unsigned dst_offset;
803 unsigned size;
804 };
805
806 struct si_context {
807 struct pipe_context b; /* base class */
808
809 enum radeon_family family;
810 enum chip_class chip_class;
811
812 struct radeon_winsys *ws;
813 struct radeon_winsys_ctx *ctx;
814 struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
815 struct radeon_cmdbuf *dma_cs;
816 struct pipe_fence_handle *last_gfx_fence;
817 struct pipe_fence_handle *last_sdma_fence;
818 struct si_resource *eop_bug_scratch;
819 struct u_upload_mgr *cached_gtt_allocator;
820 struct threaded_context *tc;
821 struct u_suballocator *allocator_zeroed_memory;
822 struct slab_child_pool pool_transfers;
823 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
824 struct pipe_device_reset_callback device_reset_callback;
825 struct u_log_context *log;
826 void *query_result_shader;
827 struct blitter_context *blitter;
828 void *custom_dsa_flush;
829 void *custom_blend_resolve;
830 void *custom_blend_fmask_decompress;
831 void *custom_blend_eliminate_fastclear;
832 void *custom_blend_dcc_decompress;
833 void *vs_blit_pos;
834 void *vs_blit_pos_layered;
835 void *vs_blit_color;
836 void *vs_blit_color_layered;
837 void *vs_blit_texcoord;
838 void *cs_clear_buffer;
839 void *cs_copy_buffer;
840 void *cs_copy_image;
841 void *cs_copy_image_1d_array;
842 void *cs_clear_render_target;
843 void *cs_clear_render_target_1d_array;
844 void *cs_dcc_retile;
845 struct si_screen *screen;
846 struct pipe_debug_callback debug;
847 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
848 struct si_shader_ctx_state fixed_func_tcs_shader;
849 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
850 struct si_resource *wait_mem_scratch;
851 unsigned wait_mem_number;
852 uint16_t prefetch_L2_mask;
853
854 bool has_graphics;
855 bool gfx_flush_in_progress:1;
856 bool gfx_last_ib_is_busy:1;
857 bool compute_is_busy:1;
858
859 unsigned num_gfx_cs_flushes;
860 unsigned initial_gfx_cs_size;
861 unsigned gpu_reset_counter;
862 unsigned last_dirty_tex_counter;
863 unsigned last_compressed_colortex_counter;
864 unsigned last_num_draw_calls;
865 unsigned flags; /* flush flags */
866 /* Current unaccounted memory usage. */
867 uint64_t vram;
868 uint64_t gtt;
869
870 /* Compute-based primitive discard. */
871 unsigned prim_discard_vertex_count_threshold;
872 struct pb_buffer *gds;
873 struct pb_buffer *gds_oa;
874 struct radeon_cmdbuf *prim_discard_compute_cs;
875 unsigned compute_gds_offset;
876 struct si_shader *compute_ib_last_shader;
877 uint32_t compute_rewind_va;
878 unsigned compute_num_prims_in_batch;
879 bool preserve_prim_restart_gds_at_flush;
880 /* index_ring is divided into 2 halves for doublebuffering. */
881 struct si_resource *index_ring;
882 unsigned index_ring_base; /* offset of a per-IB portion */
883 unsigned index_ring_offset; /* offset within a per-IB portion */
884 unsigned index_ring_size_per_ib; /* max available size per IB */
885 bool prim_discard_compute_ib_initialized;
886 /* For tracking the last execution barrier - it can be either
887 * a WRITE_DATA packet or a fence. */
888 uint32_t *last_pkt3_write_data;
889 struct si_resource *barrier_buf;
890 unsigned barrier_buf_offset;
891 struct pipe_fence_handle *last_ib_barrier_fence;
892 struct si_resource *last_ib_barrier_buf;
893 unsigned last_ib_barrier_buf_offset;
894
895 /* Atoms (direct states). */
896 union si_state_atoms atoms;
897 unsigned dirty_atoms; /* mask */
898 /* PM4 states (precomputed immutable states) */
899 unsigned dirty_states;
900 union si_state queued;
901 union si_state emitted;
902
903 /* Atom declarations. */
904 struct si_framebuffer framebuffer;
905 unsigned sample_locs_num_samples;
906 uint16_t sample_mask;
907 unsigned last_cb_target_mask;
908 struct si_blend_color blend_color;
909 struct si_clip_state clip_state;
910 struct si_shader_data shader_pointers;
911 struct si_stencil_ref stencil_ref;
912 struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
913 struct si_streamout streamout;
914 struct si_viewports viewports;
915 unsigned num_window_rectangles;
916 bool window_rectangles_include;
917 struct pipe_scissor_state window_rectangles[4];
918
919 /* Precomputed states. */
920 struct si_pm4_state *init_config;
921 struct si_pm4_state *init_config_gs_rings;
922 bool init_config_has_vgt_flush;
923 struct si_pm4_state *vgt_shader_config[4];
924
925 /* shaders */
926 struct si_shader_ctx_state ps_shader;
927 struct si_shader_ctx_state gs_shader;
928 struct si_shader_ctx_state vs_shader;
929 struct si_shader_ctx_state tcs_shader;
930 struct si_shader_ctx_state tes_shader;
931 struct si_shader_ctx_state cs_prim_discard_state;
932 struct si_cs_shader_state cs_shader_state;
933
934 /* shader information */
935 struct si_vertex_elements *vertex_elements;
936 unsigned sprite_coord_enable;
937 unsigned cs_max_waves_per_sh;
938 bool flatshade;
939 bool do_update_shaders;
940
941 /* vertex buffer descriptors */
942 uint32_t *vb_descriptors_gpu_list;
943 struct si_resource *vb_descriptors_buffer;
944 unsigned vb_descriptors_offset;
945
946 /* shader descriptors */
947 struct si_descriptors descriptors[SI_NUM_DESCS];
948 unsigned descriptors_dirty;
949 unsigned shader_pointers_dirty;
950 unsigned shader_needs_decompress_mask;
951 struct si_buffer_resources rw_buffers;
952 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
953 struct si_samplers samplers[SI_NUM_SHADERS];
954 struct si_images images[SI_NUM_SHADERS];
955 bool bo_list_add_all_resident_resources;
956 bool bo_list_add_all_gfx_resources;
957 bool bo_list_add_all_compute_resources;
958
959 /* other shader resources */
960 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */
961 struct pipe_resource *esgs_ring;
962 struct pipe_resource *gsvs_ring;
963 struct pipe_resource *tess_rings;
964 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
965 struct si_resource *border_color_buffer;
966 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
967 unsigned border_color_count;
968 unsigned num_vs_blit_sgprs;
969 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
970 uint32_t cs_user_data[4];
971
972 /* Vertex and index buffers. */
973 bool vertex_buffers_dirty;
974 bool vertex_buffer_pointer_dirty;
975 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
976 uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
977
978 /* MSAA config state. */
979 int ps_iter_samples;
980 bool ps_uses_fbfetch;
981 bool smoothing_enabled;
982
983 /* DB render state. */
984 unsigned ps_db_shader_control;
985 unsigned dbcb_copy_sample;
986 bool dbcb_depth_copy_enabled:1;
987 bool dbcb_stencil_copy_enabled:1;
988 bool db_flush_depth_inplace:1;
989 bool db_flush_stencil_inplace:1;
990 bool db_depth_clear:1;
991 bool db_depth_disable_expclear:1;
992 bool db_stencil_clear:1;
993 bool db_stencil_disable_expclear:1;
994 bool occlusion_queries_disabled:1;
995 bool generate_mipmap_for_depth:1;
996
997 /* Emitted draw state. */
998 bool gs_tri_strip_adj_fix:1;
999 bool ls_vgpr_fix:1;
1000 bool prim_discard_cs_instancing:1;
1001 int last_index_size;
1002 int last_base_vertex;
1003 int last_start_instance;
1004 int last_instance_count;
1005 int last_drawid;
1006 int last_sh_base_reg;
1007 int last_primitive_restart_en;
1008 int last_restart_index;
1009 int last_prim;
1010 int last_multi_vgt_param;
1011 int last_rast_prim;
1012 unsigned last_sc_line_stipple;
1013 unsigned current_vs_state;
1014 unsigned last_vs_state;
1015 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
1016
1017 /* Scratch buffer */
1018 struct si_resource *scratch_buffer;
1019 unsigned scratch_waves;
1020 unsigned spi_tmpring_size;
1021
1022 struct si_resource *compute_scratch_buffer;
1023
1024 /* Emitted derived tessellation state. */
1025 /* Local shader (VS), or HS if LS-HS are merged. */
1026 struct si_shader *last_ls;
1027 struct si_shader_selector *last_tcs;
1028 int last_num_tcs_input_cp;
1029 int last_tes_sh_base;
1030 bool last_tess_uses_primid;
1031 unsigned last_num_patches;
1032 int last_ls_hs_config;
1033
1034 /* Debug state. */
1035 bool is_debug;
1036 struct si_saved_cs *current_saved_cs;
1037 uint64_t dmesg_timestamp;
1038 unsigned apitrace_call_number;
1039
1040 /* Other state */
1041 bool need_check_render_feedback;
1042 bool decompression_enabled;
1043 bool dpbb_force_off;
1044 bool vs_writes_viewport_index;
1045 bool vs_disables_clipping_viewport;
1046
1047 /* Precomputed IA_MULTI_VGT_PARAM */
1048 union si_vgt_param_key ia_multi_vgt_param_key;
1049 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1050
1051 /* Bindless descriptors. */
1052 struct si_descriptors bindless_descriptors;
1053 struct util_idalloc bindless_used_slots;
1054 unsigned num_bindless_descriptors;
1055 bool bindless_descriptors_dirty;
1056 bool graphics_bindless_pointer_dirty;
1057 bool compute_bindless_pointer_dirty;
1058
1059 /* Allocated bindless handles */
1060 struct hash_table *tex_handles;
1061 struct hash_table *img_handles;
1062
1063 /* Resident bindless handles */
1064 struct util_dynarray resident_tex_handles;
1065 struct util_dynarray resident_img_handles;
1066
1067 /* Resident bindless handles which need decompression */
1068 struct util_dynarray resident_tex_needs_color_decompress;
1069 struct util_dynarray resident_img_needs_color_decompress;
1070 struct util_dynarray resident_tex_needs_depth_decompress;
1071
1072 /* Bindless state */
1073 bool uses_bindless_samplers;
1074 bool uses_bindless_images;
1075
1076 /* MSAA sample locations.
1077 * The first index is the sample index.
1078 * The second index is the coordinate: X, Y. */
1079 struct {
1080 float x1[1][2];
1081 float x2[2][2];
1082 float x4[4][2];
1083 float x8[8][2];
1084 float x16[16][2];
1085 } sample_positions;
1086 struct pipe_resource *sample_pos_buffer;
1087
1088 /* Misc stats. */
1089 unsigned num_draw_calls;
1090 unsigned num_decompress_calls;
1091 unsigned num_mrt_draw_calls;
1092 unsigned num_prim_restart_calls;
1093 unsigned num_spill_draw_calls;
1094 unsigned num_compute_calls;
1095 unsigned num_spill_compute_calls;
1096 unsigned num_dma_calls;
1097 unsigned num_cp_dma_calls;
1098 unsigned num_vs_flushes;
1099 unsigned num_ps_flushes;
1100 unsigned num_cs_flushes;
1101 unsigned num_cb_cache_flushes;
1102 unsigned num_db_cache_flushes;
1103 unsigned num_L2_invalidates;
1104 unsigned num_L2_writebacks;
1105 unsigned num_resident_handles;
1106 uint64_t num_alloc_tex_transfer_bytes;
1107 unsigned last_tex_ps_draw_ratio; /* for query */
1108 unsigned compute_num_verts_accepted;
1109 unsigned compute_num_verts_rejected;
1110 unsigned compute_num_verts_ineligible; /* due to low vertex count */
1111 unsigned context_roll;
1112
1113 /* Queries. */
1114 /* Maintain the list of active queries for pausing between IBs. */
1115 int num_occlusion_queries;
1116 int num_perfect_occlusion_queries;
1117 int num_pipeline_stat_queries;
1118 struct list_head active_queries;
1119 unsigned num_cs_dw_queries_suspend;
1120
1121 /* Render condition. */
1122 struct pipe_query *render_cond;
1123 unsigned render_cond_mode;
1124 bool render_cond_invert;
1125 bool render_cond_force_off; /* for u_blitter */
1126
1127 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1128 bool sdma_uploads_in_progress;
1129 struct si_sdma_upload *sdma_uploads;
1130 unsigned num_sdma_uploads;
1131 unsigned max_sdma_uploads;
1132
1133 /* Statistics gathering for the DCC enablement heuristic. It can't be
1134 * in si_texture because si_texture can be shared by multiple
1135 * contexts. This is for back buffers only. We shouldn't get too many
1136 * of those.
1137 *
1138 * X11 DRI3 rotates among a finite set of back buffers. They should
1139 * all fit in this array. If they don't, separate DCC might never be
1140 * enabled by DCC stat gathering.
1141 */
1142 struct {
1143 struct si_texture *tex;
1144 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1145 struct pipe_query *ps_stats[3];
1146 /* If all slots are used and another slot is needed,
1147 * the least recently used slot is evicted based on this. */
1148 int64_t last_use_timestamp;
1149 bool query_active;
1150 } dcc_stats[5];
1151
1152 /* Copy one resource to another using async DMA. */
1153 void (*dma_copy)(struct pipe_context *ctx,
1154 struct pipe_resource *dst,
1155 unsigned dst_level,
1156 unsigned dst_x, unsigned dst_y, unsigned dst_z,
1157 struct pipe_resource *src,
1158 unsigned src_level,
1159 const struct pipe_box *src_box);
1160
1161 struct si_tracked_regs tracked_regs;
1162 };
1163
1164 /* cik_sdma.c */
1165 void cik_init_sdma_functions(struct si_context *sctx);
1166
1167 /* si_blit.c */
1168 enum si_blitter_op /* bitmask */
1169 {
1170 SI_SAVE_TEXTURES = 1,
1171 SI_SAVE_FRAMEBUFFER = 2,
1172 SI_SAVE_FRAGMENT_STATE = 4,
1173 SI_DISABLE_RENDER_COND = 8,
1174 };
1175
1176 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1177 void si_blitter_end(struct si_context *sctx);
1178 void si_init_blit_functions(struct si_context *sctx);
1179 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1180 void si_resource_copy_region(struct pipe_context *ctx,
1181 struct pipe_resource *dst,
1182 unsigned dst_level,
1183 unsigned dstx, unsigned dsty, unsigned dstz,
1184 struct pipe_resource *src,
1185 unsigned src_level,
1186 const struct pipe_box *src_box);
1187 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1188 void si_blit_decompress_depth(struct pipe_context *ctx,
1189 struct si_texture *texture,
1190 struct si_texture *staging,
1191 unsigned first_level, unsigned last_level,
1192 unsigned first_layer, unsigned last_layer,
1193 unsigned first_sample, unsigned last_sample);
1194
1195 /* si_buffer.c */
1196 bool si_rings_is_buffer_referenced(struct si_context *sctx,
1197 struct pb_buffer *buf,
1198 enum radeon_bo_usage usage);
1199 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
1200 struct si_resource *resource,
1201 unsigned usage);
1202 void si_init_resource_fields(struct si_screen *sscreen,
1203 struct si_resource *res,
1204 uint64_t size, unsigned alignment);
1205 bool si_alloc_resource(struct si_screen *sscreen,
1206 struct si_resource *res);
1207 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
1208 unsigned flags, unsigned usage,
1209 unsigned size, unsigned alignment);
1210 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen,
1211 unsigned flags, unsigned usage,
1212 unsigned size, unsigned alignment);
1213 void si_replace_buffer_storage(struct pipe_context *ctx,
1214 struct pipe_resource *dst,
1215 struct pipe_resource *src);
1216 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1217 void si_init_buffer_functions(struct si_context *sctx);
1218
1219 /* si_clear.c */
1220 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1221 bool vi_alpha_is_on_msb(enum pipe_format format);
1222 void vi_dcc_clear_level(struct si_context *sctx,
1223 struct si_texture *tex,
1224 unsigned level, unsigned clear_value);
1225 void si_init_clear_functions(struct si_context *sctx);
1226
1227 /* si_compute_blit.c */
1228 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1229 enum si_cache_policy cache_policy);
1230 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1231 uint64_t offset, uint64_t size, uint32_t *clear_value,
1232 uint32_t clear_value_size, enum si_coherency coher,
1233 bool force_cpdma);
1234 void si_copy_buffer(struct si_context *sctx,
1235 struct pipe_resource *dst, struct pipe_resource *src,
1236 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1237 void si_compute_copy_image(struct si_context *sctx,
1238 struct pipe_resource *dst,
1239 unsigned dst_level,
1240 struct pipe_resource *src,
1241 unsigned src_level,
1242 unsigned dstx, unsigned dsty, unsigned dstz,
1243 const struct pipe_box *src_box);
1244 void si_compute_clear_render_target(struct pipe_context *ctx,
1245 struct pipe_surface *dstsurf,
1246 const union pipe_color_union *color,
1247 unsigned dstx, unsigned dsty,
1248 unsigned width, unsigned height,
1249 bool render_condition_enabled);
1250 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1251 void si_init_compute_blit_functions(struct si_context *sctx);
1252
1253 /* si_cp_dma.c */
1254 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1255 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1256 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1257 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1258 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1259 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1260 SI_CPDMA_SKIP_SYNC_AFTER | \
1261 SI_CPDMA_SKIP_SYNC_BEFORE | \
1262 SI_CPDMA_SKIP_GFX_SYNC | \
1263 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1264
1265 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1266 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1267 struct pipe_resource *dst, uint64_t offset,
1268 uint64_t size, unsigned value, unsigned user_flags,
1269 enum si_coherency coher, enum si_cache_policy cache_policy);
1270 void si_cp_dma_copy_buffer(struct si_context *sctx,
1271 struct pipe_resource *dst, struct pipe_resource *src,
1272 uint64_t dst_offset, uint64_t src_offset, unsigned size,
1273 unsigned user_flags, enum si_coherency coher,
1274 enum si_cache_policy cache_policy);
1275 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
1276 uint64_t offset, unsigned size);
1277 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1278 void si_test_gds(struct si_context *sctx);
1279 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf,
1280 unsigned offset, unsigned size, unsigned dst_sel,
1281 unsigned engine, const void *data);
1282 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs,
1283 unsigned dst_sel, struct si_resource *dst, unsigned dst_offset,
1284 unsigned src_sel, struct si_resource *src, unsigned src_offset);
1285
1286 /* si_debug.c */
1287 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
1288 struct radeon_saved_cs *saved, bool get_buffer_list);
1289 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1290 void si_destroy_saved_cs(struct si_saved_cs *scs);
1291 void si_auto_log_cs(void *data, struct u_log_context *log);
1292 void si_log_hw_flush(struct si_context *sctx);
1293 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1294 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1295 void si_init_debug_functions(struct si_context *sctx);
1296 void si_check_vm_faults(struct si_context *sctx,
1297 struct radeon_saved_cs *saved, enum ring_type ring);
1298 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
1299
1300 /* si_dma.c */
1301 void si_init_dma_functions(struct si_context *sctx);
1302
1303 /* si_dma_cs.c */
1304 void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst,
1305 uint64_t offset);
1306 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1307 uint64_t offset, uint64_t size, unsigned clear_value);
1308 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
1309 struct si_resource *dst, struct si_resource *src);
1310 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
1311 struct pipe_fence_handle **fence);
1312 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
1313 uint64_t offset, uint64_t size, unsigned value);
1314
1315 /* si_fence.c */
1316 void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1317 unsigned event, unsigned event_flags,
1318 unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1319 struct si_resource *buf, uint64_t va,
1320 uint32_t new_fence, unsigned query_type);
1321 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1322 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1323 uint64_t va, uint32_t ref, uint32_t mask, unsigned flags);
1324 void si_init_fence_functions(struct si_context *ctx);
1325 void si_init_screen_fence_functions(struct si_screen *screen);
1326 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1327 struct tc_unflushed_batch_token *tc_token);
1328
1329 /* si_get.c */
1330 void si_init_screen_get_functions(struct si_screen *sscreen);
1331
1332 /* si_gfx_cs.c */
1333 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
1334 struct pipe_fence_handle **fence);
1335 void si_begin_new_gfx_cs(struct si_context *ctx);
1336 void si_need_gfx_cs_space(struct si_context *ctx);
1337 void si_unref_sdma_uploads(struct si_context *sctx);
1338
1339 /* si_gpu_load.c */
1340 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1341 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1342 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
1343 uint64_t begin);
1344
1345 /* si_compute.c */
1346 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
1347 unsigned si_get_compute_resource_limits(struct si_screen *sscreen,
1348 unsigned waves_per_threadgroup,
1349 unsigned max_waves_per_sh,
1350 unsigned threadgroups_per_cu);
1351 void si_init_compute_functions(struct si_context *sctx);
1352
1353 /* si_compute_prim_discard.c */
1354 enum si_prim_discard_outcome {
1355 SI_PRIM_DISCARD_ENABLED,
1356 SI_PRIM_DISCARD_DISABLED,
1357 SI_PRIM_DISCARD_DRAW_SPLIT,
1358 };
1359
1360 void si_build_prim_discard_compute_shader(struct si_shader_context *ctx);
1361 enum si_prim_discard_outcome
1362 si_prepare_prim_discard_or_split_draw(struct si_context *sctx,
1363 const struct pipe_draw_info *info,
1364 bool primitive_restart);
1365 void si_compute_signal_gfx(struct si_context *sctx);
1366 void si_dispatch_prim_discard_cs_and_draw(struct si_context *sctx,
1367 const struct pipe_draw_info *info,
1368 unsigned index_size,
1369 unsigned base_vertex,
1370 uint64_t input_indexbuf_va,
1371 unsigned input_indexbuf_max_elements);
1372 void si_initialize_prim_discard_tunables(struct si_context *sctx);
1373
1374 /* si_perfcounters.c */
1375 void si_init_perfcounters(struct si_screen *screen);
1376 void si_destroy_perfcounters(struct si_screen *screen);
1377
1378 /* si_pipe.c */
1379 bool si_check_device_reset(struct si_context *sctx);
1380
1381 /* si_query.c */
1382 void si_init_screen_query_functions(struct si_screen *sscreen);
1383 void si_init_query_functions(struct si_context *sctx);
1384 void si_suspend_queries(struct si_context *sctx);
1385 void si_resume_queries(struct si_context *sctx);
1386
1387 /* si_shaderlib_tgsi.c */
1388 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1389 unsigned num_layers);
1390 void *si_create_fixed_func_tcs(struct si_context *sctx);
1391 void *si_create_dma_compute_shader(struct pipe_context *ctx,
1392 unsigned num_dwords_per_thread,
1393 bool dst_stream_cache_policy, bool is_copy);
1394 void *si_create_copy_image_compute_shader(struct pipe_context *ctx);
1395 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx);
1396 void *si_clear_render_target_shader(struct pipe_context *ctx);
1397 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
1398 void *si_create_dcc_retile_cs(struct pipe_context *ctx);
1399 void *si_create_query_result_cs(struct si_context *sctx);
1400
1401 /* si_test_dma.c */
1402 void si_test_dma(struct si_screen *sscreen);
1403
1404 /* si_test_clearbuffer.c */
1405 void si_test_dma_perf(struct si_screen *sscreen);
1406
1407 /* si_uvd.c */
1408 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1409 const struct pipe_video_codec *templ);
1410
1411 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1412 const struct pipe_video_buffer *tmpl);
1413
1414 /* si_viewport.c */
1415 void si_update_vs_viewport_state(struct si_context *ctx);
1416 void si_init_viewport_functions(struct si_context *ctx);
1417
1418 /* si_texture.c */
1419 bool si_prepare_for_dma_blit(struct si_context *sctx,
1420 struct si_texture *dst,
1421 unsigned dst_level, unsigned dstx,
1422 unsigned dsty, unsigned dstz,
1423 struct si_texture *src,
1424 unsigned src_level,
1425 const struct pipe_box *src_box);
1426 void si_eliminate_fast_color_clear(struct si_context *sctx,
1427 struct si_texture *tex);
1428 void si_texture_discard_cmask(struct si_screen *sscreen,
1429 struct si_texture *tex);
1430 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1431 struct pipe_resource *texture,
1432 struct si_texture **staging);
1433 void si_print_texture_info(struct si_screen *sscreen,
1434 struct si_texture *tex, struct u_log_context *log);
1435 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1436 const struct pipe_resource *templ);
1437 bool vi_dcc_formats_compatible(enum pipe_format format1,
1438 enum pipe_format format2);
1439 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1440 unsigned level,
1441 enum pipe_format view_format);
1442 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1443 struct pipe_resource *tex,
1444 unsigned level,
1445 enum pipe_format view_format);
1446 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1447 struct pipe_resource *texture,
1448 const struct pipe_surface *templ,
1449 unsigned width0, unsigned height0,
1450 unsigned width, unsigned height);
1451 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1452 void vi_separate_dcc_try_enable(struct si_context *sctx,
1453 struct si_texture *tex);
1454 void vi_separate_dcc_start_query(struct si_context *sctx,
1455 struct si_texture *tex);
1456 void vi_separate_dcc_stop_query(struct si_context *sctx,
1457 struct si_texture *tex);
1458 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1459 struct si_texture *tex);
1460 bool si_texture_disable_dcc(struct si_context *sctx,
1461 struct si_texture *tex);
1462 void si_init_screen_texture_functions(struct si_screen *sscreen);
1463 void si_init_context_texture_functions(struct si_context *sctx);
1464
1465
1466 /*
1467 * common helpers
1468 */
1469
1470 static inline struct si_resource *si_resource(struct pipe_resource *r)
1471 {
1472 return (struct si_resource*)r;
1473 }
1474
1475 static inline void
1476 si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1477 {
1478 pipe_resource_reference((struct pipe_resource **)ptr,
1479 (struct pipe_resource *)res);
1480 }
1481
1482 static inline void
1483 si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1484 {
1485 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1486 }
1487
1488 static inline bool
1489 vi_dcc_enabled(struct si_texture *tex, unsigned level)
1490 {
1491 return tex->dcc_offset && level < tex->surface.num_dcc_levels;
1492 }
1493
1494 static inline unsigned
1495 si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1496 {
1497 if (stencil)
1498 return tex->surface.u.legacy.stencil_tiling_index[level];
1499 else
1500 return tex->surface.u.legacy.tiling_index[level];
1501 }
1502
1503 static inline unsigned
1504 si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx)
1505 {
1506 /* Don't count the needed CS space exactly and just use an upper bound.
1507 *
1508 * Also reserve space for stopping queries at the end of IB, because
1509 * the number of active queries is unlimited in theory.
1510 */
1511 return 2048 + sctx->num_cs_dw_queries_suspend;
1512 }
1513
1514 static inline void
1515 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1516 {
1517 if (r) {
1518 /* Add memory usage for need_gfx_cs_space */
1519 sctx->vram += si_resource(r)->vram_usage;
1520 sctx->gtt += si_resource(r)->gart_usage;
1521 }
1522 }
1523
1524 static inline void
1525 si_invalidate_draw_sh_constants(struct si_context *sctx)
1526 {
1527 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1528 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1529 }
1530
1531 static inline unsigned
1532 si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1533 {
1534 return 1 << (atom - sctx->atoms.array);
1535 }
1536
1537 static inline void
1538 si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1539 {
1540 unsigned bit = si_get_atom_bit(sctx, atom);
1541
1542 if (dirty)
1543 sctx->dirty_atoms |= bit;
1544 else
1545 sctx->dirty_atoms &= ~bit;
1546 }
1547
1548 static inline bool
1549 si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1550 {
1551 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1552 }
1553
1554 static inline void
1555 si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1556 {
1557 si_set_atom_dirty(sctx, atom, true);
1558 }
1559
1560 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1561 {
1562 if (sctx->gs_shader.cso)
1563 return &sctx->gs_shader;
1564 if (sctx->tes_shader.cso)
1565 return &sctx->tes_shader;
1566
1567 return &sctx->vs_shader;
1568 }
1569
1570 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1571 {
1572 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1573
1574 return vs->cso ? &vs->cso->info : NULL;
1575 }
1576
1577 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1578 {
1579 if (sctx->gs_shader.cso)
1580 return sctx->gs_shader.cso->gs_copy_shader;
1581
1582 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1583 return vs->current ? vs->current : NULL;
1584 }
1585
1586 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1587 unsigned processor)
1588 {
1589 return sscreen->debug_flags & (1 << processor);
1590 }
1591
1592 static inline bool si_get_strmout_en(struct si_context *sctx)
1593 {
1594 return sctx->streamout.streamout_enabled ||
1595 sctx->streamout.prims_gen_query_enabled;
1596 }
1597
1598 static inline unsigned
1599 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1600 {
1601 unsigned alignment, tcc_cache_line_size;
1602
1603 /* If the upload size is less than the cache line size (e.g. 16, 32),
1604 * the whole thing will fit into a cache line if we align it to its size.
1605 * The idea is that multiple small uploads can share a cache line.
1606 * If the upload size is greater, align it to the cache line size.
1607 */
1608 alignment = util_next_power_of_two(upload_size);
1609 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1610 return MIN2(alignment, tcc_cache_line_size);
1611 }
1612
1613 static inline void
1614 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1615 {
1616 if (pipe_reference(&(*dst)->reference, &src->reference))
1617 si_destroy_saved_cs(*dst);
1618
1619 *dst = src;
1620 }
1621
1622 static inline void
1623 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1624 bool shaders_read_metadata, bool dcc_pipe_aligned)
1625 {
1626 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1627 SI_CONTEXT_INV_VMEM_L1;
1628
1629 if (sctx->chip_class >= GFX9) {
1630 /* Single-sample color is coherent with shaders on GFX9, but
1631 * L2 metadata must be flushed if shaders read metadata.
1632 * (DCC, CMASK).
1633 */
1634 if (num_samples >= 2 ||
1635 (shaders_read_metadata && !dcc_pipe_aligned))
1636 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1637 else if (shaders_read_metadata)
1638 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1639 } else {
1640 /* GFX6-GFX8 */
1641 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1642 }
1643 }
1644
1645 static inline void
1646 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1647 bool include_stencil, bool shaders_read_metadata)
1648 {
1649 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1650 SI_CONTEXT_INV_VMEM_L1;
1651
1652 if (sctx->chip_class >= GFX9) {
1653 /* Single-sample depth (not stencil) is coherent with shaders
1654 * on GFX9, but L2 metadata must be flushed if shaders read
1655 * metadata.
1656 */
1657 if (num_samples >= 2 || include_stencil)
1658 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1659 else if (shaders_read_metadata)
1660 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1661 } else {
1662 /* GFX6-GFX8 */
1663 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1664 }
1665 }
1666
1667 static inline bool
1668 si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1669 {
1670 return (stencil_sampler && tex->can_sample_s) ||
1671 (!stencil_sampler && tex->can_sample_z);
1672 }
1673
1674 static inline bool
1675 si_htile_enabled(struct si_texture *tex, unsigned level)
1676 {
1677 return tex->htile_offset && level == 0;
1678 }
1679
1680 static inline bool
1681 vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level)
1682 {
1683 assert(!tex->tc_compatible_htile || tex->htile_offset);
1684 return tex->tc_compatible_htile && level == 0;
1685 }
1686
1687 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1688 {
1689 if (sctx->ps_uses_fbfetch)
1690 return sctx->framebuffer.nr_color_samples;
1691
1692 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1693 }
1694
1695 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1696 {
1697 if (sctx->queued.named.rasterizer->rasterizer_discard)
1698 return 0;
1699
1700 struct si_shader_selector *ps = sctx->ps_shader.cso;
1701 if (!ps)
1702 return 0;
1703
1704 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1705 sctx->queued.named.blend->cb_target_mask;
1706
1707 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1708 colormask &= ps->colors_written_4bit;
1709 else if (!ps->colors_written_4bit)
1710 colormask = 0; /* color0 writes all cbufs, but it's not written */
1711
1712 return colormask;
1713 }
1714
1715 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1716 (1 << PIPE_PRIM_LINE_LOOP) | \
1717 (1 << PIPE_PRIM_LINE_STRIP) | \
1718 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1719 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1720
1721 static inline bool util_prim_is_lines(unsigned prim)
1722 {
1723 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1724 }
1725
1726 static inline bool util_prim_is_points_or_lines(unsigned prim)
1727 {
1728 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES |
1729 (1 << PIPE_PRIM_POINTS))) != 0;
1730 }
1731
1732 /**
1733 * Return true if there is enough memory in VRAM and GTT for the buffers
1734 * added so far.
1735 *
1736 * \param vram VRAM memory size not added to the buffer list yet
1737 * \param gtt GTT memory size not added to the buffer list yet
1738 */
1739 static inline bool
1740 radeon_cs_memory_below_limit(struct si_screen *screen,
1741 struct radeon_cmdbuf *cs,
1742 uint64_t vram, uint64_t gtt)
1743 {
1744 vram += cs->used_vram;
1745 gtt += cs->used_gart;
1746
1747 /* Anything that goes above the VRAM size should go to GTT. */
1748 if (vram > screen->info.vram_size)
1749 gtt += vram - screen->info.vram_size;
1750
1751 /* Now we just need to check if we have enough GTT. */
1752 return gtt < screen->info.gart_size * 0.7;
1753 }
1754
1755 /**
1756 * Add a buffer to the buffer list for the given command stream (CS).
1757 *
1758 * All buffers used by a CS must be added to the list. This tells the kernel
1759 * driver which buffers are used by GPU commands. Other buffers can
1760 * be swapped out (not accessible) during execution.
1761 *
1762 * The buffer list becomes empty after every context flush and must be
1763 * rebuilt.
1764 */
1765 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1766 struct radeon_cmdbuf *cs,
1767 struct si_resource *bo,
1768 enum radeon_bo_usage usage,
1769 enum radeon_bo_priority priority)
1770 {
1771 assert(usage);
1772 sctx->ws->cs_add_buffer(
1773 cs, bo->buf,
1774 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1775 bo->domains, priority);
1776 }
1777
1778 /**
1779 * Same as above, but also checks memory usage and flushes the context
1780 * accordingly.
1781 *
1782 * When this SHOULD NOT be used:
1783 *
1784 * - if si_context_add_resource_size has been called for the buffer
1785 * followed by *_need_cs_space for checking the memory usage
1786 *
1787 * - if si_need_dma_space has been called for the buffer
1788 *
1789 * - when emitting state packets and draw packets (because preceding packets
1790 * can't be re-emitted at that point)
1791 *
1792 * - if shader resource "enabled_mask" is not up-to-date or there is
1793 * a different constraint disallowing a context flush
1794 */
1795 static inline void
1796 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1797 struct si_resource *bo,
1798 enum radeon_bo_usage usage,
1799 enum radeon_bo_priority priority,
1800 bool check_mem)
1801 {
1802 if (check_mem &&
1803 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1804 sctx->vram + bo->vram_usage,
1805 sctx->gtt + bo->gart_usage))
1806 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1807
1808 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority);
1809 }
1810
1811 static inline bool si_compute_prim_discard_enabled(struct si_context *sctx)
1812 {
1813 return sctx->prim_discard_vertex_count_threshold != UINT_MAX;
1814 }
1815
1816 #define PRINT_ERR(fmt, args...) \
1817 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1818
1819 #endif