2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
31 #include <llvm-c/TargetMachine.h>
33 #ifdef PIPE_ARCH_BIG_ENDIAN
34 #define SI_BIG_ENDIAN 1
36 #define SI_BIG_ENDIAN 0
39 /* The base vertex and primitive restart can be any number, but we must pick
40 * one which will mean "unknown" for the purpose of state tracking and
41 * the number shouldn't be a commonly-used one. */
42 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
43 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
44 #define SI_NUM_SMOOTH_AA_SAMPLES 8
45 #define SI_GS_PER_ES 128
47 /* Instruction cache. */
48 #define SI_CONTEXT_INV_ICACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
49 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
50 #define SI_CONTEXT_INV_SMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 1)
51 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
52 #define SI_CONTEXT_INV_VMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 2)
53 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
54 #define SI_CONTEXT_INV_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 3)
55 /* Framebuffer caches. */
56 #define SI_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
57 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
58 #define SI_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
59 #define SI_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
60 /* Engine synchronization. */
61 #define SI_CONTEXT_VS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
62 #define SI_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 9)
63 #define SI_CONTEXT_CS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 10)
64 #define SI_CONTEXT_VGT_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 11)
65 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (R600_CONTEXT_PRIVATE_FLAG << 12)
67 #define SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER (SI_CONTEXT_FLUSH_AND_INV_CB | \
68 SI_CONTEXT_FLUSH_AND_INV_CB_META | \
69 SI_CONTEXT_FLUSH_AND_INV_DB | \
70 SI_CONTEXT_FLUSH_AND_INV_DB_META)
72 #define SI_ENCODE_TRACE_POINT(id) (0xcafe0000 | ((id) & 0xffff))
73 #define SI_IS_TRACE_POINT(x) (((x) & 0xcafe0000) == 0xcafe0000)
74 #define SI_GET_TRACE_POINT_ID(x) ((x) & 0xffff)
76 #define SI_MAX_BORDER_COLORS 4096
80 struct u_suballocator
;
83 struct r600_common_screen b
;
84 unsigned gs_table_depth
;
86 /* Whether shaders are monolithic (1-part) or separate (3-part). */
87 bool use_monolithic_shaders
;
89 pipe_mutex shader_parts_mutex
;
90 struct si_shader_part
*vs_prologs
;
91 struct si_shader_part
*vs_epilogs
;
92 struct si_shader_part
*tcs_epilogs
;
93 struct si_shader_part
*ps_prologs
;
94 struct si_shader_part
*ps_epilogs
;
96 /* Shader cache in memory.
98 * Design & limitations:
99 * - The shader cache is per screen (= per process), never saved to
100 * disk, and skips redundant shader compilations from TGSI to bytecode.
101 * - It can only be used with one-variant-per-shader support, in which
102 * case only the main (typically middle) part of shaders is cached.
103 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
104 * variants of VS and TES are cached, so LS and ES aren't.
105 * - GS and CS aren't cached, but it's certainly possible to cache
108 pipe_mutex shader_cache_mutex
;
109 struct hash_table
*shader_cache
;
112 struct si_blend_color
{
113 struct r600_atom atom
;
114 struct pipe_blend_color state
;
117 struct si_sampler_view
{
118 struct pipe_sampler_view base
;
119 struct list_head list
;
120 /* [0..7] = image descriptor
121 * [4..7] = buffer descriptor */
123 uint32_t fmask_state
[8];
124 const struct radeon_surf_level
*base_level_info
;
126 unsigned block_width
;
127 bool is_stencil_sampler
;
130 struct si_sampler_state
{
134 struct si_cs_shader_state
{
135 struct si_compute
*program
;
136 struct si_compute
*emitted_program
;
141 struct si_textures_info
{
142 struct si_sampler_views views
;
143 uint32_t depth_texture_mask
; /* which textures are depth */
144 uint32_t compressed_colortex_mask
;
147 struct si_images_info
{
148 struct pipe_image_view views
[SI_NUM_IMAGES
];
149 uint32_t compressed_colortex_mask
;
150 unsigned enabled_mask
;
153 struct si_framebuffer
{
154 struct r600_atom atom
;
155 struct pipe_framebuffer_state state
;
157 unsigned log_samples
;
158 unsigned cb0_is_integer
;
159 unsigned compressed_cb_mask
;
160 unsigned spi_shader_col_format
;
161 unsigned spi_shader_col_format_alpha
;
162 unsigned spi_shader_col_format_blend
;
163 unsigned spi_shader_col_format_blend_alpha
;
164 unsigned color_is_int8
; /* bitmask */
165 unsigned dirty_cbufs
;
169 struct si_clip_state
{
170 struct r600_atom atom
;
171 struct pipe_clip_state state
;
174 struct si_sample_mask
{
175 struct r600_atom atom
;
176 uint16_t sample_mask
;
179 /* A shader state consists of the shader selector, which is a constant state
180 * object shared by multiple contexts and shouldn't be modified, and
181 * the current shader variant selected for this context.
183 struct si_shader_ctx_state
{
184 struct si_shader_selector
*cso
;
185 struct si_shader
*current
;
189 struct r600_common_context b
;
190 struct blitter_context
*blitter
;
191 void *custom_dsa_flush
;
192 void *custom_blend_resolve
;
193 void *custom_blend_decompress
;
194 void *custom_blend_fastclear
;
195 void *custom_blend_dcc_decompress
;
196 struct si_screen
*screen
;
198 struct radeon_winsys_cs
*ce_ib
;
199 struct radeon_winsys_cs
*ce_preamble_ib
;
200 bool ce_need_synchronization
;
201 struct u_suballocator
*ce_suballocator
;
203 struct pipe_fence_handle
*last_gfx_fence
;
204 struct si_shader_ctx_state fixed_func_tcs_shader
;
205 LLVMTargetMachineRef tm
;
206 bool gfx_flush_in_progress
;
208 /* Atoms (direct states). */
209 union si_state_atoms atoms
;
210 unsigned dirty_atoms
; /* mask */
211 /* PM4 states (precomputed immutable states) */
212 union si_state queued
;
213 union si_state emitted
;
215 /* Atom declarations. */
216 struct r600_atom cache_flush
;
217 struct si_framebuffer framebuffer
;
218 struct r600_atom msaa_sample_locs
;
219 struct r600_atom db_render_state
;
220 struct r600_atom msaa_config
;
221 struct si_sample_mask sample_mask
;
222 struct r600_atom cb_render_state
;
223 struct si_blend_color blend_color
;
224 struct r600_atom clip_regs
;
225 struct si_clip_state clip_state
;
226 struct si_shader_data shader_userdata
;
227 struct si_stencil_ref stencil_ref
;
228 struct r600_atom spi_map
;
230 /* Precomputed states. */
231 struct si_pm4_state
*init_config
;
232 struct si_pm4_state
*init_config_gs_rings
;
233 bool init_config_has_vgt_flush
;
234 struct si_pm4_state
*vgt_shader_config
[4];
237 struct si_shader_ctx_state ps_shader
;
238 struct si_shader_ctx_state gs_shader
;
239 struct si_shader_ctx_state vs_shader
;
240 struct si_shader_ctx_state tcs_shader
;
241 struct si_shader_ctx_state tes_shader
;
242 struct si_cs_shader_state cs_shader_state
;
244 /* shader information */
245 struct si_vertex_element
*vertex_elements
;
246 unsigned sprite_coord_enable
;
249 /* shader descriptors */
250 struct si_descriptors vertex_buffers
;
251 struct si_descriptors descriptors
[SI_NUM_DESCS
];
252 unsigned descriptors_dirty
;
253 struct si_buffer_resources rw_buffers
;
254 struct si_buffer_resources const_buffers
[SI_NUM_SHADERS
];
255 struct si_buffer_resources shader_buffers
[SI_NUM_SHADERS
];
256 struct si_textures_info samplers
[SI_NUM_SHADERS
];
257 struct si_images_info images
[SI_NUM_SHADERS
];
259 /* other shader resources */
260 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on CIK */
261 struct pipe_resource
*esgs_ring
;
262 struct pipe_resource
*gsvs_ring
;
263 struct pipe_resource
*tf_ring
;
264 struct pipe_resource
*tess_offchip_ring
;
265 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
266 struct r600_resource
*border_color_buffer
;
267 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
268 unsigned border_color_count
;
270 /* Vertex and index buffers. */
271 bool vertex_buffers_dirty
;
272 struct pipe_index_buffer index_buffer
;
273 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
275 /* MSAA config state. */
277 bool smoothing_enabled
;
279 /* DB render state. */
280 bool dbcb_depth_copy_enabled
;
281 bool dbcb_stencil_copy_enabled
;
282 unsigned dbcb_copy_sample
;
283 bool db_flush_depth_inplace
;
284 bool db_flush_stencil_inplace
;
286 bool db_depth_disable_expclear
;
287 bool db_stencil_clear
;
288 bool db_stencil_disable_expclear
;
289 unsigned ps_db_shader_control
;
290 bool occlusion_queries_disabled
;
292 /* Emitted draw state. */
293 int last_base_vertex
;
294 int last_start_instance
;
295 int last_sh_base_reg
;
296 int last_primitive_restart_en
;
297 int last_restart_index
;
298 int last_gs_out_prim
;
300 int last_multi_vgt_param
;
301 int last_ls_hs_config
;
303 unsigned last_sc_line_stipple
;
304 int current_rast_prim
; /* primitive type after TES, GS */
305 unsigned last_gsvs_itemsize
;
308 struct r600_resource
*scratch_buffer
;
309 boolean emit_scratch_reloc
;
310 unsigned scratch_waves
;
311 unsigned spi_tmpring_size
;
313 struct r600_resource
*compute_scratch_buffer
;
315 /* Emitted derived tessellation state. */
316 struct si_shader
*last_ls
; /* local shader (VS) */
317 struct si_shader_selector
*last_tcs
;
318 int last_num_tcs_input_cp
;
319 int last_tes_sh_base
;
324 unsigned last_ib_dw_size
;
325 struct r600_resource
*last_trace_buf
;
326 struct r600_resource
*trace_buf
;
328 uint64_t dmesg_timestamp
;
329 unsigned last_bo_count
;
330 struct radeon_bo_list_item
*last_bo_list
;
333 bool need_check_render_feedback
;
337 void cik_init_sdma_functions(struct si_context
*sctx
);
340 void si_init_blit_functions(struct si_context
*sctx
);
341 void si_decompress_graphics_textures(struct si_context
*sctx
);
342 void si_decompress_compute_textures(struct si_context
*sctx
);
343 void si_resource_copy_region(struct pipe_context
*ctx
,
344 struct pipe_resource
*dst
,
346 unsigned dstx
, unsigned dsty
, unsigned dstz
,
347 struct pipe_resource
*src
,
349 const struct pipe_box
*src_box
);
352 void si_copy_buffer(struct si_context
*sctx
,
353 struct pipe_resource
*dst
, struct pipe_resource
*src
,
354 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
);
355 void si_init_cp_dma_functions(struct si_context
*sctx
);
358 void si_init_debug_functions(struct si_context
*sctx
);
359 void si_check_vm_faults(struct si_context
*sctx
);
360 bool si_replace_shader(unsigned num
, struct radeon_shader_binary
*binary
);
363 void si_init_dma_functions(struct si_context
*sctx
);
365 /* si_hw_context.c */
366 void si_context_gfx_flush(void *context
, unsigned flags
,
367 struct pipe_fence_handle
**fence
);
368 void si_begin_new_cs(struct si_context
*ctx
);
369 void si_need_cs_space(struct si_context
*ctx
);
372 void si_init_compute_functions(struct si_context
*sctx
);
374 /* si_perfcounters.c */
375 void si_init_perfcounters(struct si_screen
*screen
);
378 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
379 const struct pipe_video_codec
*templ
);
381 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
382 const struct pipe_video_buffer
*tmpl
);
388 static inline struct r600_resource
*
389 si_resource_create_custom(struct pipe_screen
*screen
,
390 unsigned usage
, unsigned size
)
393 return r600_resource(pipe_buffer_create(screen
,
394 PIPE_BIND_CUSTOM
, usage
, size
));
398 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
400 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
401 sctx
->last_start_instance
= -1; /* reset to an unknown value */
402 sctx
->last_sh_base_reg
= -1; /* reset to an unknown value */
406 si_set_atom_dirty(struct si_context
*sctx
,
407 struct r600_atom
*atom
, bool dirty
)
409 unsigned bit
= 1 << (atom
->id
- 1);
412 sctx
->dirty_atoms
|= bit
;
414 sctx
->dirty_atoms
&= ~bit
;
418 si_is_atom_dirty(struct si_context
*sctx
,
419 struct r600_atom
*atom
)
421 unsigned bit
= 1 << (atom
->id
- 1);
423 return sctx
->dirty_atoms
& bit
;
427 si_mark_atom_dirty(struct si_context
*sctx
,
428 struct r600_atom
*atom
)
430 si_set_atom_dirty(sctx
, atom
, true);