2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "si_shader.h"
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_range.h"
34 #include "util/u_threaded_context.h"
36 #ifdef PIPE_ARCH_BIG_ENDIAN
37 #define SI_BIG_ENDIAN 1
39 #define SI_BIG_ENDIAN 0
42 #define ATI_VENDOR_ID 0x1002
44 #define SI_NOT_QUERY 0xffffffff
46 /* The base vertex and primitive restart can be any number, but we must pick
47 * one which will mean "unknown" for the purpose of state tracking and
48 * the number shouldn't be a commonly-used one. */
49 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
50 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_GS_PER_ES 128
53 /* Alignment for optimal CP DMA performance. */
54 #define SI_CPDMA_ALIGNMENT 32
56 /* Pipeline & streamout query controls. */
57 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
58 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
59 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
60 /* Instruction cache. */
61 #define SI_CONTEXT_INV_ICACHE (1 << 3)
62 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
63 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
64 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
65 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
66 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
67 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
68 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
69 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
70 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
71 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
72 * a CB or DB flush. */
73 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
74 /* Framebuffer caches. */
75 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
76 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
77 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
78 /* Engine synchronization. */
79 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
80 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
81 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
82 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
83 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
85 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
86 #define SI_PREFETCH_LS (1 << 1)
87 #define SI_PREFETCH_HS (1 << 2)
88 #define SI_PREFETCH_ES (1 << 3)
89 #define SI_PREFETCH_GS (1 << 4)
90 #define SI_PREFETCH_VS (1 << 5)
91 #define SI_PREFETCH_PS (1 << 6)
93 #define SI_MAX_BORDER_COLORS 4096
94 #define SI_MAX_VIEWPORTS 16
96 #define SI_MAP_BUFFER_ALIGNMENT 64
97 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
99 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
100 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
101 #define SI_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
102 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
103 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
104 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
105 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
109 /* Shader logging options: */
110 DBG_VS
= PIPE_SHADER_VERTEX
,
111 DBG_PS
= PIPE_SHADER_FRAGMENT
,
112 DBG_GS
= PIPE_SHADER_GEOMETRY
,
113 DBG_TCS
= PIPE_SHADER_TESS_CTRL
,
114 DBG_TES
= PIPE_SHADER_TESS_EVAL
,
115 DBG_CS
= PIPE_SHADER_COMPUTE
,
121 /* Shader compiler options the shader cache should be aware of: */
122 DBG_FS_CORRECT_DERIVS_AFTER_KILL
,
126 /* Shader compiler options (with no effect on the shader cache): */
129 DBG_MONOLITHIC_SHADERS
,
132 /* Information logging options: */
138 /* Driver options: */
146 /* 3D engine options: */
166 DBG_TEST_VMFAULT_SDMA
,
167 DBG_TEST_VMFAULT_SHADER
,
170 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
171 #define DBG(name) (1ull << DBG_##name)
175 struct u_suballocator
;
177 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
180 struct r600_resource
{
181 struct threaded_resource b
;
183 /* Winsys objects. */
184 struct pb_buffer
*buf
;
185 uint64_t gpu_address
;
186 /* Memory usage if the buffer placement is optimal. */
190 /* Resource properties. */
192 unsigned bo_alignment
;
193 enum radeon_bo_domain domains
;
194 enum radeon_bo_flag flags
;
195 unsigned bind_history
;
196 int max_forced_staging_uploads
;
198 /* The buffer range which is initialized (with a write transfer,
199 * streamout, DMA, or as a random access target). The rest of
200 * the buffer is considered invalid and can be mapped unsynchronized.
202 * This allows unsychronized mapping of a buffer range which hasn't
203 * been used yet. It's for applications which forget to use
204 * the unsynchronized map flag and expect the driver to figure it out.
206 struct util_range valid_buffer_range
;
208 /* For buffers only. This indicates that a write operation has been
209 * performed by TC L2, but the cache hasn't been flushed.
210 * Any hw block which doesn't use or bypasses TC L2 should check this
211 * flag and flush the cache before using the buffer.
213 * For example, TC L2 must be flushed if a buffer which has been
214 * modified by a shader store instruction is about to be used as
215 * an index buffer. The reason is that VGT DMA index fetching doesn't
220 /* Whether this resource is referenced by bindless handles. */
221 bool texture_handle_allocated
;
222 bool image_handle_allocated
;
224 /* Whether the resource has been exported via resource_get_handle. */
225 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
228 struct r600_transfer
{
229 struct threaded_transfer b
;
230 struct r600_resource
*staging
;
234 struct r600_cmask_info
{
238 unsigned slice_tile_max
;
239 uint64_t base_address_reg
;
243 struct r600_resource buffer
;
245 struct radeon_surf surface
;
247 struct si_texture
*flushed_depth_texture
;
249 /* Colorbuffer compression and fast clear. */
250 uint64_t fmask_offset
;
251 struct r600_cmask_info cmask
;
252 struct r600_resource
*cmask_buffer
;
253 uint64_t dcc_offset
; /* 0 = disabled */
254 unsigned cb_color_info
; /* fast clear enable bit */
255 unsigned color_clear_value
[2];
256 unsigned last_msaa_resolve_target_micro_mode
;
257 unsigned num_level0_transfers
;
258 unsigned num_color_samples
;
260 /* Depth buffer compression and fast clear. */
261 uint64_t htile_offset
;
262 float depth_clear_value
;
263 uint16_t dirty_level_mask
; /* each bit says if that mipmap is compressed */
264 uint16_t stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
265 enum pipe_format db_render_format
:16;
266 uint8_t stencil_clear_value
;
267 bool tc_compatible_htile
:1;
268 bool depth_cleared
:1; /* if it was cleared at least once */
269 bool stencil_cleared
:1; /* if it was cleared at least once */
270 bool upgraded_depth
:1; /* upgraded from unorm to Z32_FLOAT */
272 bool db_compatible
:1;
276 /* We need to track DCC dirtiness, because st/dri usually calls
277 * flush_resource twice per frame (not a bug) and we don't wanna
278 * decompress DCC twice. Also, the dirty tracking must be done even
279 * if DCC isn't used, because it's required by the DCC usage analysis
280 * for a possible future enablement.
282 bool separate_dcc_dirty
:1;
283 /* Statistics gathering for the DCC enablement heuristic. */
284 bool dcc_gather_statistics
:1;
285 /* Counter that should be non-zero if the texture is bound to a
288 unsigned framebuffers_bound
;
289 /* Whether the texture is a displayable back buffer and needs DCC
290 * decompression, which is expensive. Therefore, it's enabled only
291 * if statistics suggest that it will pay off and it's allocated
292 * separately. It can't be bound as a sampler by apps. Limited to
293 * target == 2D and last_level == 0. If enabled, dcc_offset contains
294 * the absolute GPUVM address, not the relative one.
296 struct r600_resource
*dcc_separate_buffer
;
297 /* When DCC is temporarily disabled, the separate buffer is here. */
298 struct r600_resource
*last_dcc_separate_buffer
;
299 /* Estimate of how much this color buffer is written to in units of
300 * full-screen draws: ps_invocations / (width * height)
301 * Shader kills, late Z, and blending with trivial discards make it
302 * inaccurate (we need to count CB updates, not PS invocations).
304 unsigned ps_draw_ratio
;
305 /* The number of clears since the last DCC usage analysis. */
306 unsigned num_slow_clears
;
309 struct r600_surface
{
310 struct pipe_surface base
;
312 /* These can vary with block-compressed textures. */
316 bool color_initialized
:1;
317 bool depth_initialized
:1;
319 /* Misc. color flags. */
320 bool color_is_int8
:1;
321 bool color_is_int10
:1;
322 bool dcc_incompatible
:1;
324 /* Color registers. */
325 unsigned cb_color_info
;
326 unsigned cb_color_view
;
327 unsigned cb_color_attrib
;
328 unsigned cb_color_attrib2
; /* GFX9 and later */
329 unsigned cb_dcc_control
; /* VI and later */
330 unsigned spi_shader_col_format
:8; /* no blending, no alpha-to-coverage. */
331 unsigned spi_shader_col_format_alpha
:8; /* alpha-to-coverage */
332 unsigned spi_shader_col_format_blend
:8; /* blending without alpha. */
333 unsigned spi_shader_col_format_blend_alpha
:8; /* blending with alpha. */
336 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE */
337 uint64_t db_stencil_base
;
338 uint64_t db_htile_data_base
;
339 unsigned db_depth_info
;
341 unsigned db_z_info2
; /* GFX9+ */
342 unsigned db_depth_view
;
343 unsigned db_depth_size
;
344 unsigned db_depth_slice
;
345 unsigned db_stencil_info
;
346 unsigned db_stencil_info2
; /* GFX9+ */
347 unsigned db_htile_surface
;
350 struct si_mmio_counter
{
355 union si_mmio_counters
{
357 /* For global GPU load including SDMA. */
358 struct si_mmio_counter gpu
;
361 struct si_mmio_counter spi
;
362 struct si_mmio_counter gui
;
363 struct si_mmio_counter ta
;
364 struct si_mmio_counter gds
;
365 struct si_mmio_counter vgt
;
366 struct si_mmio_counter ia
;
367 struct si_mmio_counter sx
;
368 struct si_mmio_counter wd
;
369 struct si_mmio_counter bci
;
370 struct si_mmio_counter sc
;
371 struct si_mmio_counter pa
;
372 struct si_mmio_counter db
;
373 struct si_mmio_counter cp
;
374 struct si_mmio_counter cb
;
377 struct si_mmio_counter sdma
;
380 struct si_mmio_counter pfp
;
381 struct si_mmio_counter meq
;
382 struct si_mmio_counter me
;
383 struct si_mmio_counter surf_sync
;
384 struct si_mmio_counter cp_dma
;
385 struct si_mmio_counter scratch_ram
;
390 struct r600_memory_object
{
391 struct pipe_memory_object b
;
392 struct pb_buffer
*buf
;
397 /* Saved CS data for debugging features. */
398 struct radeon_saved_cs
{
402 struct radeon_bo_list_item
*bo_list
;
407 struct pipe_screen b
;
408 struct radeon_winsys
*ws
;
409 struct disk_cache
*disk_shader_cache
;
411 struct radeon_info info
;
412 uint64_t debug_flags
;
413 char renderer_string
[183];
415 unsigned gs_table_depth
;
416 unsigned tess_offchip_block_dw_size
;
417 unsigned tess_offchip_ring_size
;
418 unsigned tess_factor_ring_size
;
419 unsigned vgt_hs_offchip_param
;
420 unsigned eqaa_force_coverage_samples
;
421 unsigned eqaa_force_z_samples
;
422 unsigned eqaa_force_color_samples
;
423 bool has_clear_state
;
424 bool has_distributed_tess
;
425 bool has_draw_indirect_multi
;
426 bool has_out_of_order_rast
;
427 bool assume_no_z_fights
;
428 bool commutative_blend_add
;
429 bool clear_db_cache_before_clear
;
430 bool has_msaa_sample_loc_bug
;
431 bool has_ls_vgpr_init_bug
;
434 bool llvm_has_working_vgpr_indexing
;
436 /* Whether shaders are monolithic (1-part) or separate (3-part). */
437 bool use_monolithic_shaders
;
439 bool has_rbplus
; /* if RB+ registers exist */
440 bool rbplus_allowed
; /* if RB+ is allowed */
441 bool dcc_msaa_allowed
;
442 bool cpdma_prefetch_writes_memory
;
444 struct slab_parent_pool pool_transfers
;
446 /* Texture filter settings. */
447 int force_aniso
; /* -1 = disabled */
449 /* Auxiliary context. Mainly used to initialize resources.
450 * It must be locked prior to using and flushed before unlocking. */
451 struct pipe_context
*aux_context
;
452 mtx_t aux_context_lock
;
454 /* This must be in the screen, because UE4 uses one context for
455 * compilation and another one for rendering.
457 unsigned num_compilations
;
458 /* Along with ST_DEBUG=precompile, this should show if applications
459 * are loading shaders on demand. This is a monotonic counter.
461 unsigned num_shaders_created
;
462 unsigned num_shader_cache_hits
;
464 /* GPU load thread. */
465 mtx_t gpu_load_mutex
;
466 thrd_t gpu_load_thread
;
467 union si_mmio_counters mmio_counters
;
468 volatile unsigned gpu_load_stop_thread
; /* bool */
470 /* Performance counters. */
471 struct si_perfcounters
*perfcounters
;
473 /* If pipe_screen wants to recompute and re-emit the framebuffer,
474 * sampler, and image states of all contexts, it should atomically
477 * Each context will compare this with its own last known value of
478 * the counter before drawing and re-emit the states accordingly.
480 unsigned dirty_tex_counter
;
482 /* Atomically increment this counter when an existing texture's
483 * metadata is enabled or disabled in a way that requires changing
484 * contexts' compressed texture binding masks.
486 unsigned compressed_colortex_counter
;
489 /* Context flags to set so that all writes from earlier jobs
490 * in the CP are seen by L2 clients.
494 /* Context flags to set so that all writes from earlier jobs
495 * that end in L2 are seen by CP.
500 mtx_t shader_parts_mutex
;
501 struct si_shader_part
*vs_prologs
;
502 struct si_shader_part
*tcs_epilogs
;
503 struct si_shader_part
*gs_prologs
;
504 struct si_shader_part
*ps_prologs
;
505 struct si_shader_part
*ps_epilogs
;
507 /* Shader cache in memory.
509 * Design & limitations:
510 * - The shader cache is per screen (= per process), never saved to
511 * disk, and skips redundant shader compilations from TGSI to bytecode.
512 * - It can only be used with one-variant-per-shader support, in which
513 * case only the main (typically middle) part of shaders is cached.
514 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
515 * variants of VS and TES are cached, so LS and ES aren't.
516 * - GS and CS aren't cached, but it's certainly possible to cache
519 mtx_t shader_cache_mutex
;
520 struct hash_table
*shader_cache
;
522 /* Shader compiler queue for multithreaded compilation. */
523 struct util_queue shader_compiler_queue
;
524 /* Use at most 3 normal compiler threads on quadcore and better.
525 * Hyperthreaded CPUs report the number of threads, but we want
526 * the number of cores. We only need this many threads for shader-db. */
527 struct si_compiler compiler
[24]; /* used by the queue only */
529 struct util_queue shader_compiler_queue_low_priority
;
530 /* Use at most 2 low priority threads on quadcore and better.
531 * We want to minimize the impact on multithreaded Mesa. */
532 struct si_compiler compiler_lowp
[10];
535 struct si_blend_color
{
536 struct pipe_blend_color state
;
540 struct si_sampler_view
{
541 struct pipe_sampler_view base
;
542 /* [0..7] = image descriptor
543 * [4..7] = buffer descriptor */
545 uint32_t fmask_state
[8];
546 const struct legacy_surf_level
*base_level_info
;
549 bool is_stencil_sampler
;
551 bool dcc_incompatible
;
554 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
556 struct si_sampler_state
{
561 uint32_t integer_val
[4];
562 uint32_t upgraded_depth_val
[4];
565 struct si_cs_shader_state
{
566 struct si_compute
*program
;
567 struct si_compute
*emitted_program
;
574 struct pipe_sampler_view
*views
[SI_NUM_SAMPLERS
];
575 struct si_sampler_state
*sampler_states
[SI_NUM_SAMPLERS
];
577 /* The i-th bit is set if that element is enabled (non-NULL resource). */
578 unsigned enabled_mask
;
579 uint32_t needs_depth_decompress_mask
;
580 uint32_t needs_color_decompress_mask
;
584 struct pipe_image_view views
[SI_NUM_IMAGES
];
585 uint32_t needs_color_decompress_mask
;
586 unsigned enabled_mask
;
589 struct si_framebuffer
{
590 struct pipe_framebuffer_state state
;
591 unsigned colorbuf_enabled_4bit
;
592 unsigned spi_shader_col_format
;
593 unsigned spi_shader_col_format_alpha
;
594 unsigned spi_shader_col_format_blend
;
595 unsigned spi_shader_col_format_blend_alpha
;
596 ubyte nr_samples
:5; /* at most 16xAA */
597 ubyte log_samples
:3; /* at most 4 = 16xAA */
598 ubyte nr_color_samples
; /* at most 8xAA */
599 ubyte compressed_cb_mask
;
600 ubyte uncompressed_cb_mask
;
602 ubyte color_is_int10
;
606 bool CB_has_shader_readable_metadata
;
607 bool DB_has_shader_readable_metadata
;
610 struct si_signed_scissor
{
619 struct pipe_scissor_state states
[SI_MAX_VIEWPORTS
];
622 struct si_viewports
{
624 unsigned depth_range_dirty_mask
;
625 struct pipe_viewport_state states
[SI_MAX_VIEWPORTS
];
626 struct si_signed_scissor as_scissor
[SI_MAX_VIEWPORTS
];
629 struct si_clip_state
{
630 struct pipe_clip_state state
;
634 struct si_streamout_target
{
635 struct pipe_stream_output_target b
;
637 /* The buffer where BUFFER_FILLED_SIZE is stored. */
638 struct r600_resource
*buf_filled_size
;
639 unsigned buf_filled_size_offset
;
640 bool buf_filled_size_valid
;
642 unsigned stride_in_dw
;
645 struct si_streamout
{
648 unsigned enabled_mask
;
649 unsigned num_targets
;
650 struct si_streamout_target
*targets
[PIPE_MAX_SO_BUFFERS
];
652 unsigned append_bitmask
;
655 /* External state which comes from the vertex shader,
656 * it must be set explicitly when binding a shader. */
657 uint16_t *stride_in_dw
;
658 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
660 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
661 unsigned hw_enabled_mask
;
663 /* The state of VGT_STRMOUT_(CONFIG|EN). */
664 bool streamout_enabled
;
665 bool prims_gen_query_enabled
;
666 int num_prims_gen_queries
;
669 /* A shader state consists of the shader selector, which is a constant state
670 * object shared by multiple contexts and shouldn't be modified, and
671 * the current shader variant selected for this context.
673 struct si_shader_ctx_state
{
674 struct si_shader_selector
*cso
;
675 struct si_shader
*current
;
678 #define SI_NUM_VGT_PARAM_KEY_BITS 12
679 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
681 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
682 * Some fields are set by state-change calls, most are set by draw_vbo.
684 union si_vgt_param_key
{
686 #ifdef PIPE_ARCH_LITTLE_ENDIAN
688 unsigned uses_instancing
:1;
689 unsigned multi_instances_smaller_than_primgroup
:1;
690 unsigned primitive_restart
:1;
691 unsigned count_from_stream_output
:1;
692 unsigned line_stipple_enabled
:1;
693 unsigned uses_tess
:1;
694 unsigned tess_uses_prim_id
:1;
696 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
697 #else /* PIPE_ARCH_BIG_ENDIAN */
698 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
700 unsigned tess_uses_prim_id
:1;
701 unsigned uses_tess
:1;
702 unsigned line_stipple_enabled
:1;
703 unsigned count_from_stream_output
:1;
704 unsigned primitive_restart
:1;
705 unsigned multi_instances_smaller_than_primgroup
:1;
706 unsigned uses_instancing
:1;
713 struct si_texture_handle
717 struct pipe_sampler_view
*view
;
718 struct si_sampler_state sstate
;
721 struct si_image_handle
725 struct pipe_image_view view
;
729 struct pipe_reference reference
;
730 struct si_context
*ctx
;
731 struct radeon_saved_cs gfx
;
732 struct r600_resource
*trace_buf
;
735 unsigned gfx_last_dw
;
741 struct pipe_context b
; /* base class */
743 enum radeon_family family
;
744 enum chip_class chip_class
;
746 struct radeon_winsys
*ws
;
747 struct radeon_winsys_ctx
*ctx
;
748 struct radeon_cmdbuf
*gfx_cs
;
749 struct radeon_cmdbuf
*dma_cs
;
750 struct pipe_fence_handle
*last_gfx_fence
;
751 struct pipe_fence_handle
*last_sdma_fence
;
752 struct r600_resource
*eop_bug_scratch
;
753 struct u_upload_mgr
*cached_gtt_allocator
;
754 struct threaded_context
*tc
;
755 struct u_suballocator
*allocator_zeroed_memory
;
756 struct slab_child_pool pool_transfers
;
757 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
758 struct pipe_device_reset_callback device_reset_callback
;
759 struct u_log_context
*log
;
760 void *query_result_shader
;
761 struct blitter_context
*blitter
;
762 void *custom_dsa_flush
;
763 void *custom_blend_resolve
;
764 void *custom_blend_fmask_decompress
;
765 void *custom_blend_eliminate_fastclear
;
766 void *custom_blend_dcc_decompress
;
768 void *vs_blit_pos_layered
;
770 void *vs_blit_color_layered
;
771 void *vs_blit_texcoord
;
772 struct si_screen
*screen
;
773 struct pipe_debug_callback debug
;
774 struct si_compiler compiler
; /* only non-threaded compilation */
775 struct si_shader_ctx_state fixed_func_tcs_shader
;
776 struct r600_resource
*wait_mem_scratch
;
777 unsigned wait_mem_number
;
778 uint16_t prefetch_L2_mask
;
780 bool gfx_flush_in_progress
:1;
781 bool gfx_last_ib_is_busy
:1;
782 bool compute_is_busy
:1;
784 unsigned num_gfx_cs_flushes
;
785 unsigned initial_gfx_cs_size
;
786 unsigned gpu_reset_counter
;
787 unsigned last_dirty_tex_counter
;
788 unsigned last_compressed_colortex_counter
;
789 unsigned last_num_draw_calls
;
790 unsigned flags
; /* flush flags */
791 /* Current unaccounted memory usage. */
795 /* Atoms (direct states). */
796 union si_state_atoms atoms
;
797 unsigned dirty_atoms
; /* mask */
798 /* PM4 states (precomputed immutable states) */
799 unsigned dirty_states
;
800 union si_state queued
;
801 union si_state emitted
;
803 /* Atom declarations. */
804 struct si_framebuffer framebuffer
;
805 unsigned sample_locs_num_samples
;
806 uint16_t sample_mask
;
807 unsigned last_cb_target_mask
;
808 struct si_blend_color blend_color
;
809 struct si_clip_state clip_state
;
810 struct si_shader_data shader_pointers
;
811 struct si_stencil_ref stencil_ref
;
812 struct si_scissors scissors
;
813 struct si_streamout streamout
;
814 struct si_viewports viewports
;
816 /* Precomputed states. */
817 struct si_pm4_state
*init_config
;
818 struct si_pm4_state
*init_config_gs_rings
;
819 bool init_config_has_vgt_flush
;
820 struct si_pm4_state
*vgt_shader_config
[4];
823 struct si_shader_ctx_state ps_shader
;
824 struct si_shader_ctx_state gs_shader
;
825 struct si_shader_ctx_state vs_shader
;
826 struct si_shader_ctx_state tcs_shader
;
827 struct si_shader_ctx_state tes_shader
;
828 struct si_cs_shader_state cs_shader_state
;
830 /* shader information */
831 struct si_vertex_elements
*vertex_elements
;
832 unsigned sprite_coord_enable
;
834 bool do_update_shaders
;
836 /* vertex buffer descriptors */
837 uint32_t *vb_descriptors_gpu_list
;
838 struct r600_resource
*vb_descriptors_buffer
;
839 unsigned vb_descriptors_offset
;
841 /* shader descriptors */
842 struct si_descriptors descriptors
[SI_NUM_DESCS
];
843 unsigned descriptors_dirty
;
844 unsigned shader_pointers_dirty
;
845 unsigned shader_needs_decompress_mask
;
846 struct si_buffer_resources rw_buffers
;
847 struct si_buffer_resources const_and_shader_buffers
[SI_NUM_SHADERS
];
848 struct si_samplers samplers
[SI_NUM_SHADERS
];
849 struct si_images images
[SI_NUM_SHADERS
];
851 /* other shader resources */
852 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on CIK */
853 struct pipe_resource
*esgs_ring
;
854 struct pipe_resource
*gsvs_ring
;
855 struct pipe_resource
*tess_rings
;
856 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
857 struct r600_resource
*border_color_buffer
;
858 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
859 unsigned border_color_count
;
860 unsigned num_vs_blit_sgprs
;
861 uint32_t vs_blit_sh_data
[SI_VS_BLIT_SGPRS_POS_TEXCOORD
];
863 /* Vertex and index buffers. */
864 bool vertex_buffers_dirty
;
865 bool vertex_buffer_pointer_dirty
;
866 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
868 /* MSAA config state. */
870 bool ps_uses_fbfetch
;
871 bool smoothing_enabled
;
873 /* DB render state. */
874 unsigned ps_db_shader_control
;
875 unsigned dbcb_copy_sample
;
876 bool dbcb_depth_copy_enabled
:1;
877 bool dbcb_stencil_copy_enabled
:1;
878 bool db_flush_depth_inplace
:1;
879 bool db_flush_stencil_inplace
:1;
880 bool db_depth_clear
:1;
881 bool db_depth_disable_expclear
:1;
882 bool db_stencil_clear
:1;
883 bool db_stencil_disable_expclear
:1;
884 bool occlusion_queries_disabled
:1;
885 bool generate_mipmap_for_depth
:1;
887 /* Emitted draw state. */
888 bool gs_tri_strip_adj_fix
:1;
891 int last_base_vertex
;
892 int last_start_instance
;
894 int last_sh_base_reg
;
895 int last_primitive_restart_en
;
896 int last_restart_index
;
898 int last_multi_vgt_param
;
900 unsigned last_sc_line_stipple
;
901 unsigned current_vs_state
;
902 unsigned last_vs_state
;
903 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
906 struct r600_resource
*scratch_buffer
;
907 unsigned scratch_waves
;
908 unsigned spi_tmpring_size
;
910 struct r600_resource
*compute_scratch_buffer
;
912 /* Emitted derived tessellation state. */
913 /* Local shader (VS), or HS if LS-HS are merged. */
914 struct si_shader
*last_ls
;
915 struct si_shader_selector
*last_tcs
;
916 int last_num_tcs_input_cp
;
917 int last_tes_sh_base
;
918 bool last_tess_uses_primid
;
919 unsigned last_num_patches
;
920 int last_ls_hs_config
;
924 struct si_saved_cs
*current_saved_cs
;
925 uint64_t dmesg_timestamp
;
926 unsigned apitrace_call_number
;
929 bool need_check_render_feedback
;
930 bool decompression_enabled
;
932 bool vs_writes_viewport_index
;
933 bool vs_disables_clipping_viewport
;
935 /* Precomputed IA_MULTI_VGT_PARAM */
936 union si_vgt_param_key ia_multi_vgt_param_key
;
937 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
939 /* Bindless descriptors. */
940 struct si_descriptors bindless_descriptors
;
941 struct util_idalloc bindless_used_slots
;
942 unsigned num_bindless_descriptors
;
943 bool bindless_descriptors_dirty
;
944 bool graphics_bindless_pointer_dirty
;
945 bool compute_bindless_pointer_dirty
;
947 /* Allocated bindless handles */
948 struct hash_table
*tex_handles
;
949 struct hash_table
*img_handles
;
951 /* Resident bindless handles */
952 struct util_dynarray resident_tex_handles
;
953 struct util_dynarray resident_img_handles
;
955 /* Resident bindless handles which need decompression */
956 struct util_dynarray resident_tex_needs_color_decompress
;
957 struct util_dynarray resident_img_needs_color_decompress
;
958 struct util_dynarray resident_tex_needs_depth_decompress
;
961 bool uses_bindless_samplers
;
962 bool uses_bindless_images
;
964 /* MSAA sample locations.
965 * The first index is the sample index.
966 * The second index is the coordinate: X, Y. */
967 float sample_locations_1x
[1][2];
968 float sample_locations_2x
[2][2];
969 float sample_locations_4x
[4][2];
970 float sample_locations_8x
[8][2];
971 float sample_locations_16x
[16][2];
974 unsigned num_draw_calls
;
975 unsigned num_decompress_calls
;
976 unsigned num_mrt_draw_calls
;
977 unsigned num_prim_restart_calls
;
978 unsigned num_spill_draw_calls
;
979 unsigned num_compute_calls
;
980 unsigned num_spill_compute_calls
;
981 unsigned num_dma_calls
;
982 unsigned num_cp_dma_calls
;
983 unsigned num_vs_flushes
;
984 unsigned num_ps_flushes
;
985 unsigned num_cs_flushes
;
986 unsigned num_cb_cache_flushes
;
987 unsigned num_db_cache_flushes
;
988 unsigned num_L2_invalidates
;
989 unsigned num_L2_writebacks
;
990 unsigned num_resident_handles
;
991 uint64_t num_alloc_tex_transfer_bytes
;
992 unsigned last_tex_ps_draw_ratio
; /* for query */
995 /* Maintain the list of active queries for pausing between IBs. */
996 int num_occlusion_queries
;
997 int num_perfect_occlusion_queries
;
998 struct list_head active_queries
;
999 unsigned num_cs_dw_queries_suspend
;
1001 /* Render condition. */
1002 struct pipe_query
*render_cond
;
1003 unsigned render_cond_mode
;
1004 bool render_cond_invert
;
1005 bool render_cond_force_off
; /* for u_blitter */
1007 /* Statistics gathering for the DCC enablement heuristic. It can't be
1008 * in si_texture because si_texture can be shared by multiple
1009 * contexts. This is for back buffers only. We shouldn't get too many
1012 * X11 DRI3 rotates among a finite set of back buffers. They should
1013 * all fit in this array. If they don't, separate DCC might never be
1014 * enabled by DCC stat gathering.
1017 struct si_texture
*tex
;
1018 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1019 struct pipe_query
*ps_stats
[3];
1020 /* If all slots are used and another slot is needed,
1021 * the least recently used slot is evicted based on this. */
1022 int64_t last_use_timestamp
;
1026 /* Copy one resource to another using async DMA. */
1027 void (*dma_copy
)(struct pipe_context
*ctx
,
1028 struct pipe_resource
*dst
,
1030 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
1031 struct pipe_resource
*src
,
1033 const struct pipe_box
*src_box
);
1035 void (*dma_clear_buffer
)(struct si_context
*sctx
, struct pipe_resource
*dst
,
1036 uint64_t offset
, uint64_t size
, unsigned value
);
1038 struct si_tracked_regs tracked_regs
;
1042 void cik_init_sdma_functions(struct si_context
*sctx
);
1045 enum si_blitter_op
/* bitmask */
1047 SI_SAVE_TEXTURES
= 1,
1048 SI_SAVE_FRAMEBUFFER
= 2,
1049 SI_SAVE_FRAGMENT_STATE
= 4,
1050 SI_DISABLE_RENDER_COND
= 8,
1053 void si_blitter_begin(struct si_context
*sctx
, enum si_blitter_op op
);
1054 void si_blitter_end(struct si_context
*sctx
);
1055 void si_init_blit_functions(struct si_context
*sctx
);
1056 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
);
1057 void si_resource_copy_region(struct pipe_context
*ctx
,
1058 struct pipe_resource
*dst
,
1060 unsigned dstx
, unsigned dsty
, unsigned dstz
,
1061 struct pipe_resource
*src
,
1063 const struct pipe_box
*src_box
);
1064 void si_decompress_dcc(struct si_context
*sctx
, struct si_texture
*tex
);
1065 void si_blit_decompress_depth(struct pipe_context
*ctx
,
1066 struct si_texture
*texture
,
1067 struct si_texture
*staging
,
1068 unsigned first_level
, unsigned last_level
,
1069 unsigned first_layer
, unsigned last_layer
,
1070 unsigned first_sample
, unsigned last_sample
);
1073 bool si_rings_is_buffer_referenced(struct si_context
*sctx
,
1074 struct pb_buffer
*buf
,
1075 enum radeon_bo_usage usage
);
1076 void *si_buffer_map_sync_with_rings(struct si_context
*sctx
,
1077 struct r600_resource
*resource
,
1079 void si_init_resource_fields(struct si_screen
*sscreen
,
1080 struct r600_resource
*res
,
1081 uint64_t size
, unsigned alignment
);
1082 bool si_alloc_resource(struct si_screen
*sscreen
,
1083 struct r600_resource
*res
);
1084 struct pipe_resource
*pipe_aligned_buffer_create(struct pipe_screen
*screen
,
1085 unsigned flags
, unsigned usage
,
1086 unsigned size
, unsigned alignment
);
1087 struct r600_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
,
1088 unsigned flags
, unsigned usage
,
1089 unsigned size
, unsigned alignment
);
1090 void si_replace_buffer_storage(struct pipe_context
*ctx
,
1091 struct pipe_resource
*dst
,
1092 struct pipe_resource
*src
);
1093 void si_init_screen_buffer_functions(struct si_screen
*sscreen
);
1094 void si_init_buffer_functions(struct si_context
*sctx
);
1097 enum pipe_format
si_simplify_cb_format(enum pipe_format format
);
1098 bool vi_alpha_is_on_msb(enum pipe_format format
);
1099 void vi_dcc_clear_level(struct si_context
*sctx
,
1100 struct si_texture
*tex
,
1101 unsigned level
, unsigned clear_value
);
1102 void si_init_clear_functions(struct si_context
*sctx
);
1105 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1106 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1107 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1108 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1109 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1110 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1111 SI_CPDMA_SKIP_SYNC_AFTER | \
1112 SI_CPDMA_SKIP_SYNC_BEFORE | \
1113 SI_CPDMA_SKIP_GFX_SYNC | \
1114 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1117 SI_COHERENCY_NONE
, /* no cache flushes needed */
1118 SI_COHERENCY_SHADER
,
1119 SI_COHERENCY_CB_META
,
1122 void si_cp_dma_wait_for_idle(struct si_context
*sctx
);
1123 void si_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1124 uint64_t offset
, uint64_t size
, unsigned value
,
1125 enum si_coherency coher
);
1126 void si_copy_buffer(struct si_context
*sctx
,
1127 struct pipe_resource
*dst
, struct pipe_resource
*src
,
1128 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
1129 unsigned user_flags
);
1130 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
1131 uint64_t offset
, unsigned size
);
1132 void cik_emit_prefetch_L2(struct si_context
*sctx
, bool vertex_stage_only
);
1133 void si_init_cp_dma_functions(struct si_context
*sctx
);
1136 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_cmdbuf
*cs
,
1137 struct radeon_saved_cs
*saved
, bool get_buffer_list
);
1138 void si_clear_saved_cs(struct radeon_saved_cs
*saved
);
1139 void si_destroy_saved_cs(struct si_saved_cs
*scs
);
1140 void si_auto_log_cs(void *data
, struct u_log_context
*log
);
1141 void si_log_hw_flush(struct si_context
*sctx
);
1142 void si_log_draw_state(struct si_context
*sctx
, struct u_log_context
*log
);
1143 void si_log_compute_state(struct si_context
*sctx
, struct u_log_context
*log
);
1144 void si_init_debug_functions(struct si_context
*sctx
);
1145 void si_check_vm_faults(struct si_context
*sctx
,
1146 struct radeon_saved_cs
*saved
, enum ring_type ring
);
1147 bool si_replace_shader(unsigned num
, struct ac_shader_binary
*binary
);
1150 void si_init_dma_functions(struct si_context
*sctx
);
1153 void si_need_dma_space(struct si_context
*ctx
, unsigned num_dw
,
1154 struct r600_resource
*dst
, struct r600_resource
*src
);
1155 void si_flush_dma_cs(struct si_context
*ctx
, unsigned flags
,
1156 struct pipe_fence_handle
**fence
);
1157 void si_screen_clear_buffer(struct si_screen
*sscreen
, struct pipe_resource
*dst
,
1158 uint64_t offset
, uint64_t size
, unsigned value
);
1161 void si_gfx_write_event_eop(struct si_context
*ctx
,
1162 unsigned event
, unsigned event_flags
,
1164 struct r600_resource
*buf
, uint64_t va
,
1165 uint32_t new_fence
, unsigned query_type
);
1166 unsigned si_gfx_write_fence_dwords(struct si_screen
*screen
);
1167 void si_gfx_wait_fence(struct si_context
*ctx
,
1168 uint64_t va
, uint32_t ref
, uint32_t mask
);
1169 void si_init_fence_functions(struct si_context
*ctx
);
1170 void si_init_screen_fence_functions(struct si_screen
*screen
);
1171 struct pipe_fence_handle
*si_create_fence(struct pipe_context
*ctx
,
1172 struct tc_unflushed_batch_token
*tc_token
);
1175 const char *si_get_family_name(const struct si_screen
*sscreen
);
1176 void si_init_screen_get_functions(struct si_screen
*sscreen
);
1179 void si_flush_gfx_cs(struct si_context
*ctx
, unsigned flags
,
1180 struct pipe_fence_handle
**fence
);
1181 void si_begin_new_gfx_cs(struct si_context
*ctx
);
1182 void si_need_gfx_cs_space(struct si_context
*ctx
);
1184 /* r600_gpu_load.c */
1185 void si_gpu_load_kill_thread(struct si_screen
*sscreen
);
1186 uint64_t si_begin_counter(struct si_screen
*sscreen
, unsigned type
);
1187 unsigned si_end_counter(struct si_screen
*sscreen
, unsigned type
,
1191 void si_init_compute_functions(struct si_context
*sctx
);
1193 /* r600_perfcounters.c */
1194 void si_perfcounters_destroy(struct si_screen
*sscreen
);
1196 /* si_perfcounters.c */
1197 void si_init_perfcounters(struct si_screen
*screen
);
1200 bool si_check_device_reset(struct si_context
*sctx
);
1203 void si_init_screen_query_functions(struct si_screen
*sscreen
);
1204 void si_init_query_functions(struct si_context
*sctx
);
1205 void si_suspend_queries(struct si_context
*sctx
);
1206 void si_resume_queries(struct si_context
*sctx
);
1209 void si_test_dma(struct si_screen
*sscreen
);
1212 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
1213 const struct pipe_video_codec
*templ
);
1215 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
1216 const struct pipe_video_buffer
*tmpl
);
1219 void si_update_vs_viewport_state(struct si_context
*ctx
);
1220 void si_init_viewport_functions(struct si_context
*ctx
);
1223 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
1224 struct si_texture
*dst
,
1225 unsigned dst_level
, unsigned dstx
,
1226 unsigned dsty
, unsigned dstz
,
1227 struct si_texture
*src
,
1229 const struct pipe_box
*src_box
);
1230 void si_texture_get_cmask_info(struct si_screen
*sscreen
,
1231 struct si_texture
*tex
,
1232 struct r600_cmask_info
*out
);
1233 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
1234 struct si_texture
*tex
);
1235 void si_texture_discard_cmask(struct si_screen
*sscreen
,
1236 struct si_texture
*tex
);
1237 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1238 struct pipe_resource
*texture
,
1239 struct si_texture
**staging
);
1240 void si_print_texture_info(struct si_screen
*sscreen
,
1241 struct si_texture
*tex
, struct u_log_context
*log
);
1242 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1243 const struct pipe_resource
*templ
);
1244 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1245 enum pipe_format format2
);
1246 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1248 enum pipe_format view_format
);
1249 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
1250 struct pipe_resource
*tex
,
1252 enum pipe_format view_format
);
1253 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1254 struct pipe_resource
*texture
,
1255 const struct pipe_surface
*templ
,
1256 unsigned width0
, unsigned height0
,
1257 unsigned width
, unsigned height
);
1258 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
1259 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
1260 struct si_texture
*tex
);
1261 void vi_separate_dcc_start_query(struct si_context
*sctx
,
1262 struct si_texture
*tex
);
1263 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
1264 struct si_texture
*tex
);
1265 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
1266 struct si_texture
*tex
);
1267 bool si_texture_disable_dcc(struct si_context
*sctx
,
1268 struct si_texture
*tex
);
1269 void si_init_screen_texture_functions(struct si_screen
*sscreen
);
1270 void si_init_context_texture_functions(struct si_context
*sctx
);
1277 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
1279 return (struct r600_resource
*)r
;
1283 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
1285 pipe_resource_reference((struct pipe_resource
**)ptr
,
1286 (struct pipe_resource
*)res
);
1290 si_texture_reference(struct si_texture
**ptr
, struct si_texture
*res
)
1292 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->buffer
.b
.b
);
1296 vi_dcc_enabled(struct si_texture
*tex
, unsigned level
)
1298 return tex
->dcc_offset
&& level
< tex
->surface
.num_dcc_levels
;
1301 static inline unsigned
1302 si_tile_mode_index(struct si_texture
*tex
, unsigned level
, bool stencil
)
1305 return tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
1307 return tex
->surface
.u
.legacy
.tiling_index
[level
];
1311 si_context_add_resource_size(struct si_context
*sctx
, struct pipe_resource
*r
)
1314 /* Add memory usage for need_gfx_cs_space */
1315 sctx
->vram
+= r600_resource(r
)->vram_usage
;
1316 sctx
->gtt
+= r600_resource(r
)->gart_usage
;
1321 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
1323 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
1326 static inline unsigned
1327 si_get_atom_bit(struct si_context
*sctx
, struct si_atom
*atom
)
1329 return 1 << (atom
- sctx
->atoms
.array
);
1333 si_set_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
, bool dirty
)
1335 unsigned bit
= si_get_atom_bit(sctx
, atom
);
1338 sctx
->dirty_atoms
|= bit
;
1340 sctx
->dirty_atoms
&= ~bit
;
1344 si_is_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1346 return (sctx
->dirty_atoms
& si_get_atom_bit(sctx
, atom
)) != 0;
1350 si_mark_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1352 si_set_atom_dirty(sctx
, atom
, true);
1355 static inline struct si_shader_ctx_state
*si_get_vs(struct si_context
*sctx
)
1357 if (sctx
->gs_shader
.cso
)
1358 return &sctx
->gs_shader
;
1359 if (sctx
->tes_shader
.cso
)
1360 return &sctx
->tes_shader
;
1362 return &sctx
->vs_shader
;
1365 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
1367 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1369 return vs
->cso
? &vs
->cso
->info
: NULL
;
1372 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
1374 if (sctx
->gs_shader
.cso
)
1375 return sctx
->gs_shader
.cso
->gs_copy_shader
;
1377 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1378 return vs
->current
? vs
->current
: NULL
;
1381 static inline bool si_can_dump_shader(struct si_screen
*sscreen
,
1384 return sscreen
->debug_flags
& (1 << processor
);
1387 static inline bool si_get_strmout_en(struct si_context
*sctx
)
1389 return sctx
->streamout
.streamout_enabled
||
1390 sctx
->streamout
.prims_gen_query_enabled
;
1393 static inline unsigned
1394 si_optimal_tcc_alignment(struct si_context
*sctx
, unsigned upload_size
)
1396 unsigned alignment
, tcc_cache_line_size
;
1398 /* If the upload size is less than the cache line size (e.g. 16, 32),
1399 * the whole thing will fit into a cache line if we align it to its size.
1400 * The idea is that multiple small uploads can share a cache line.
1401 * If the upload size is greater, align it to the cache line size.
1403 alignment
= util_next_power_of_two(upload_size
);
1404 tcc_cache_line_size
= sctx
->screen
->info
.tcc_cache_line_size
;
1405 return MIN2(alignment
, tcc_cache_line_size
);
1409 si_saved_cs_reference(struct si_saved_cs
**dst
, struct si_saved_cs
*src
)
1411 if (pipe_reference(&(*dst
)->reference
, &src
->reference
))
1412 si_destroy_saved_cs(*dst
);
1418 si_make_CB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1419 bool shaders_read_metadata
)
1421 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
|
1422 SI_CONTEXT_INV_VMEM_L1
;
1424 if (sctx
->chip_class
>= GFX9
) {
1425 /* Single-sample color is coherent with shaders on GFX9, but
1426 * L2 metadata must be flushed if shaders read metadata.
1429 if (num_samples
>= 2)
1430 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1431 else if (shaders_read_metadata
)
1432 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1435 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1440 si_make_DB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1441 bool include_stencil
, bool shaders_read_metadata
)
1443 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB
|
1444 SI_CONTEXT_INV_VMEM_L1
;
1446 if (sctx
->chip_class
>= GFX9
) {
1447 /* Single-sample depth (not stencil) is coherent with shaders
1448 * on GFX9, but L2 metadata must be flushed if shaders read
1451 if (num_samples
>= 2 || include_stencil
)
1452 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1453 else if (shaders_read_metadata
)
1454 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1457 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1462 si_can_sample_zs(struct si_texture
*tex
, bool stencil_sampler
)
1464 return (stencil_sampler
&& tex
->can_sample_s
) ||
1465 (!stencil_sampler
&& tex
->can_sample_z
);
1469 si_htile_enabled(struct si_texture
*tex
, unsigned level
)
1471 return tex
->htile_offset
&& level
== 0;
1475 vi_tc_compat_htile_enabled(struct si_texture
*tex
, unsigned level
)
1477 assert(!tex
->tc_compatible_htile
|| tex
->htile_offset
);
1478 return tex
->tc_compatible_htile
&& level
== 0;
1481 static inline unsigned si_get_ps_iter_samples(struct si_context
*sctx
)
1483 if (sctx
->ps_uses_fbfetch
)
1484 return sctx
->framebuffer
.nr_color_samples
;
1486 return MIN2(sctx
->ps_iter_samples
, sctx
->framebuffer
.nr_color_samples
);
1489 static inline unsigned si_get_total_colormask(struct si_context
*sctx
)
1491 if (sctx
->queued
.named
.rasterizer
->rasterizer_discard
)
1494 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1498 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
1499 sctx
->queued
.named
.blend
->cb_target_mask
;
1501 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
1502 colormask
&= ps
->colors_written_4bit
;
1503 else if (!ps
->colors_written_4bit
)
1504 colormask
= 0; /* color0 writes all cbufs, but it's not written */
1509 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1510 (1 << PIPE_PRIM_LINE_LOOP) | \
1511 (1 << PIPE_PRIM_LINE_STRIP) | \
1512 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1513 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1515 static inline bool util_prim_is_lines(unsigned prim
)
1517 return ((1 << prim
) & UTIL_ALL_PRIM_LINE_MODES
) != 0;
1520 static inline bool util_prim_is_points_or_lines(unsigned prim
)
1522 return ((1 << prim
) & (UTIL_ALL_PRIM_LINE_MODES
|
1523 (1 << PIPE_PRIM_POINTS
))) != 0;
1527 * Return true if there is enough memory in VRAM and GTT for the buffers
1530 * \param vram VRAM memory size not added to the buffer list yet
1531 * \param gtt GTT memory size not added to the buffer list yet
1534 radeon_cs_memory_below_limit(struct si_screen
*screen
,
1535 struct radeon_cmdbuf
*cs
,
1536 uint64_t vram
, uint64_t gtt
)
1538 vram
+= cs
->used_vram
;
1539 gtt
+= cs
->used_gart
;
1541 /* Anything that goes above the VRAM size should go to GTT. */
1542 if (vram
> screen
->info
.vram_size
)
1543 gtt
+= vram
- screen
->info
.vram_size
;
1545 /* Now we just need to check if we have enough GTT. */
1546 return gtt
< screen
->info
.gart_size
* 0.7;
1550 * Add a buffer to the buffer list for the given command stream (CS).
1552 * All buffers used by a CS must be added to the list. This tells the kernel
1553 * driver which buffers are used by GPU commands. Other buffers can
1554 * be swapped out (not accessible) during execution.
1556 * The buffer list becomes empty after every context flush and must be
1559 static inline void radeon_add_to_buffer_list(struct si_context
*sctx
,
1560 struct radeon_cmdbuf
*cs
,
1561 struct r600_resource
*rbo
,
1562 enum radeon_bo_usage usage
,
1563 enum radeon_bo_priority priority
)
1566 sctx
->ws
->cs_add_buffer(
1568 (enum radeon_bo_usage
)(usage
| RADEON_USAGE_SYNCHRONIZED
),
1569 rbo
->domains
, priority
);
1573 * Same as above, but also checks memory usage and flushes the context
1576 * When this SHOULD NOT be used:
1578 * - if si_context_add_resource_size has been called for the buffer
1579 * followed by *_need_cs_space for checking the memory usage
1581 * - if si_need_dma_space has been called for the buffer
1583 * - when emitting state packets and draw packets (because preceding packets
1584 * can't be re-emitted at that point)
1586 * - if shader resource "enabled_mask" is not up-to-date or there is
1587 * a different constraint disallowing a context flush
1590 radeon_add_to_gfx_buffer_list_check_mem(struct si_context
*sctx
,
1591 struct r600_resource
*rbo
,
1592 enum radeon_bo_usage usage
,
1593 enum radeon_bo_priority priority
,
1597 !radeon_cs_memory_below_limit(sctx
->screen
, sctx
->gfx_cs
,
1598 sctx
->vram
+ rbo
->vram_usage
,
1599 sctx
->gtt
+ rbo
->gart_usage
))
1600 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1602 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, rbo
, usage
, priority
);
1605 #define PRINT_ERR(fmt, args...) \
1606 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)