2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "si_shader.h"
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
38 #define SI_BIG_ENDIAN 0
41 #define ATI_VENDOR_ID 0x1002
42 #define SI_PRIM_DISCARD_DEBUG 0
43 #define SI_NOT_QUERY 0xffffffff
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
69 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
70 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
71 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
72 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
73 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
74 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
75 * invalidate L2. GFX6-GFX7 can't do it, so they will do complete invalidation. */
76 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
77 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
78 * a CB or DB flush. */
79 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
80 /* Framebuffer caches. */
81 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
82 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
83 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
84 /* Engine synchronization. */
85 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
86 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
87 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
88 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
89 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
91 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
92 #define SI_PREFETCH_LS (1 << 1)
93 #define SI_PREFETCH_HS (1 << 2)
94 #define SI_PREFETCH_ES (1 << 3)
95 #define SI_PREFETCH_GS (1 << 4)
96 #define SI_PREFETCH_VS (1 << 5)
97 #define SI_PREFETCH_PS (1 << 6)
99 #define SI_MAX_BORDER_COLORS 4096
100 #define SI_MAX_VIEWPORTS 16
101 #define SIX_BITS 0x3F
102 #define SI_MAP_BUFFER_ALIGNMENT 64
103 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
105 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
106 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
107 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
108 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
109 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
110 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
111 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
112 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
113 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
114 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
118 DCC_CLEAR_COLOR_0000
= 0x00000000,
119 DCC_CLEAR_COLOR_0001
= 0x40404040,
120 DCC_CLEAR_COLOR_1110
= 0x80808080,
121 DCC_CLEAR_COLOR_1111
= 0xC0C0C0C0,
122 DCC_CLEAR_COLOR_REG
= 0x20202020,
123 DCC_UNCOMPRESSED
= 0xFFFFFFFF,
126 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
130 /* Shader logging options: */
131 DBG_VS
= PIPE_SHADER_VERTEX
,
132 DBG_PS
= PIPE_SHADER_FRAGMENT
,
133 DBG_GS
= PIPE_SHADER_GEOMETRY
,
134 DBG_TCS
= PIPE_SHADER_TESS_CTRL
,
135 DBG_TES
= PIPE_SHADER_TESS_EVAL
,
136 DBG_CS
= PIPE_SHADER_COMPUTE
,
142 /* Shader compiler options the shader cache should be aware of: */
143 DBG_FS_CORRECT_DERIVS_AFTER_KILL
,
148 /* Shader compiler options (with no effect on the shader cache): */
150 DBG_MONOLITHIC_SHADERS
,
153 /* Information logging options: */
159 /* Driver options: */
167 /* 3D engine options: */
190 DBG_TEST_VMFAULT_SDMA
,
191 DBG_TEST_VMFAULT_SHADER
,
198 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
199 #define DBG(name) (1ull << DBG_##name)
201 enum si_cache_policy
{
203 L2_STREAM
, /* same as SLC=1 */
204 L2_LRU
, /* same as SLC=0 */
208 SI_COHERENCY_NONE
, /* no cache flushes needed */
210 SI_COHERENCY_CB_META
,
215 struct si_shader_context
;
217 struct u_suballocator
;
219 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
223 struct threaded_resource b
;
225 /* Winsys objects. */
226 struct pb_buffer
*buf
;
227 uint64_t gpu_address
;
228 /* Memory usage if the buffer placement is optimal. */
232 /* Resource properties. */
234 unsigned bo_alignment
;
235 enum radeon_bo_domain domains
;
236 enum radeon_bo_flag flags
;
237 unsigned bind_history
;
238 int max_forced_staging_uploads
;
240 /* The buffer range which is initialized (with a write transfer,
241 * streamout, DMA, or as a random access target). The rest of
242 * the buffer is considered invalid and can be mapped unsynchronized.
244 * This allows unsychronized mapping of a buffer range which hasn't
245 * been used yet. It's for applications which forget to use
246 * the unsynchronized map flag and expect the driver to figure it out.
248 struct util_range valid_buffer_range
;
250 /* For buffers only. This indicates that a write operation has been
251 * performed by TC L2, but the cache hasn't been flushed.
252 * Any hw block which doesn't use or bypasses TC L2 should check this
253 * flag and flush the cache before using the buffer.
255 * For example, TC L2 must be flushed if a buffer which has been
256 * modified by a shader store instruction is about to be used as
257 * an index buffer. The reason is that VGT DMA index fetching doesn't
262 /* Whether this resource is referenced by bindless handles. */
263 bool texture_handle_allocated
;
264 bool image_handle_allocated
;
266 /* Whether the resource has been exported via resource_get_handle. */
267 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
271 struct threaded_transfer b
;
272 struct si_resource
*staging
;
277 struct si_resource buffer
;
279 struct radeon_surf surface
;
281 struct si_texture
*flushed_depth_texture
;
283 /* One texture allocation can contain these buffers:
284 * - image (pixel data)
285 * - FMASK buffer (MSAA compression)
286 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
287 * - HTILE buffer (Z/S compression and fast Z/S clear)
288 * - DCC buffer (color compression and new fast color clear)
289 * - displayable DCC buffer (if the DCC buffer is not displayable)
290 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
292 uint64_t fmask_offset
;
293 uint64_t cmask_offset
;
294 uint64_t cmask_base_address_reg
;
295 struct si_resource
*cmask_buffer
;
296 uint64_t dcc_offset
; /* 0 = disabled */
297 uint64_t display_dcc_offset
;
298 uint64_t dcc_retile_map_offset
;
299 unsigned cb_color_info
; /* fast clear enable bit */
300 unsigned color_clear_value
[2];
301 unsigned last_msaa_resolve_target_micro_mode
;
302 unsigned num_level0_transfers
;
304 /* Depth buffer compression and fast clear. */
305 uint64_t htile_offset
;
306 float depth_clear_value
;
307 uint16_t dirty_level_mask
; /* each bit says if that mipmap is compressed */
308 uint16_t stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
309 enum pipe_format db_render_format
:16;
310 uint8_t stencil_clear_value
;
311 bool tc_compatible_htile
:1;
312 bool depth_cleared
:1; /* if it was cleared at least once */
313 bool stencil_cleared
:1; /* if it was cleared at least once */
314 bool upgraded_depth
:1; /* upgraded from unorm to Z32_FLOAT */
316 bool db_compatible
:1;
320 /* We need to track DCC dirtiness, because st/dri usually calls
321 * flush_resource twice per frame (not a bug) and we don't wanna
322 * decompress DCC twice. Also, the dirty tracking must be done even
323 * if DCC isn't used, because it's required by the DCC usage analysis
324 * for a possible future enablement.
326 bool separate_dcc_dirty
:1;
327 /* Statistics gathering for the DCC enablement heuristic. */
328 bool dcc_gather_statistics
:1;
329 /* Counter that should be non-zero if the texture is bound to a
332 unsigned framebuffers_bound
;
333 /* Whether the texture is a displayable back buffer and needs DCC
334 * decompression, which is expensive. Therefore, it's enabled only
335 * if statistics suggest that it will pay off and it's allocated
336 * separately. It can't be bound as a sampler by apps. Limited to
337 * target == 2D and last_level == 0. If enabled, dcc_offset contains
338 * the absolute GPUVM address, not the relative one.
340 struct si_resource
*dcc_separate_buffer
;
341 /* When DCC is temporarily disabled, the separate buffer is here. */
342 struct si_resource
*last_dcc_separate_buffer
;
343 /* Estimate of how much this color buffer is written to in units of
344 * full-screen draws: ps_invocations / (width * height)
345 * Shader kills, late Z, and blending with trivial discards make it
346 * inaccurate (we need to count CB updates, not PS invocations).
348 unsigned ps_draw_ratio
;
349 /* The number of clears since the last DCC usage analysis. */
350 unsigned num_slow_clears
;
354 struct pipe_surface base
;
356 /* These can vary with block-compressed textures. */
360 bool color_initialized
:1;
361 bool depth_initialized
:1;
363 /* Misc. color flags. */
364 bool color_is_int8
:1;
365 bool color_is_int10
:1;
366 bool dcc_incompatible
:1;
368 /* Color registers. */
369 unsigned cb_color_info
;
370 unsigned cb_color_view
;
371 unsigned cb_color_attrib
;
372 unsigned cb_color_attrib2
; /* GFX9 and later */
373 unsigned cb_dcc_control
; /* GFX8 and later */
374 unsigned spi_shader_col_format
:8; /* no blending, no alpha-to-coverage. */
375 unsigned spi_shader_col_format_alpha
:8; /* alpha-to-coverage */
376 unsigned spi_shader_col_format_blend
:8; /* blending without alpha. */
377 unsigned spi_shader_col_format_blend_alpha
:8; /* blending with alpha. */
380 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE */
381 uint64_t db_stencil_base
;
382 uint64_t db_htile_data_base
;
383 unsigned db_depth_info
;
385 unsigned db_z_info2
; /* GFX9+ */
386 unsigned db_depth_view
;
387 unsigned db_depth_size
;
388 unsigned db_depth_slice
;
389 unsigned db_stencil_info
;
390 unsigned db_stencil_info2
; /* GFX9+ */
391 unsigned db_htile_surface
;
394 struct si_mmio_counter
{
399 union si_mmio_counters
{
401 /* For global GPU load including SDMA. */
402 struct si_mmio_counter gpu
;
405 struct si_mmio_counter spi
;
406 struct si_mmio_counter gui
;
407 struct si_mmio_counter ta
;
408 struct si_mmio_counter gds
;
409 struct si_mmio_counter vgt
;
410 struct si_mmio_counter ia
;
411 struct si_mmio_counter sx
;
412 struct si_mmio_counter wd
;
413 struct si_mmio_counter bci
;
414 struct si_mmio_counter sc
;
415 struct si_mmio_counter pa
;
416 struct si_mmio_counter db
;
417 struct si_mmio_counter cp
;
418 struct si_mmio_counter cb
;
421 struct si_mmio_counter sdma
;
424 struct si_mmio_counter pfp
;
425 struct si_mmio_counter meq
;
426 struct si_mmio_counter me
;
427 struct si_mmio_counter surf_sync
;
428 struct si_mmio_counter cp_dma
;
429 struct si_mmio_counter scratch_ram
;
434 struct si_memory_object
{
435 struct pipe_memory_object b
;
436 struct pb_buffer
*buf
;
440 /* Saved CS data for debugging features. */
441 struct radeon_saved_cs
{
445 struct radeon_bo_list_item
*bo_list
;
450 struct pipe_screen b
;
451 struct radeon_winsys
*ws
;
452 struct disk_cache
*disk_shader_cache
;
454 struct radeon_info info
;
455 uint64_t debug_flags
;
456 char renderer_string
[183];
458 unsigned pa_sc_raster_config
;
459 unsigned pa_sc_raster_config_1
;
460 unsigned se_tile_repeat
;
461 unsigned gs_table_depth
;
462 unsigned tess_offchip_block_dw_size
;
463 unsigned tess_offchip_ring_size
;
464 unsigned tess_factor_ring_size
;
465 unsigned vgt_hs_offchip_param
;
466 unsigned eqaa_force_coverage_samples
;
467 unsigned eqaa_force_z_samples
;
468 unsigned eqaa_force_color_samples
;
469 bool has_clear_state
;
470 bool has_distributed_tess
;
471 bool has_draw_indirect_multi
;
472 bool has_out_of_order_rast
;
473 bool assume_no_z_fights
;
474 bool commutative_blend_add
;
475 bool has_gfx9_scissor_bug
;
476 bool has_msaa_sample_loc_bug
;
477 bool has_ls_vgpr_init_bug
;
478 bool has_dcc_constant_encode
;
481 bool llvm_has_working_vgpr_indexing
;
484 #define OPT_BOOL(name, dflt, description) bool name:1;
485 #include "si_debug_options.h"
488 /* Whether shaders are monolithic (1-part) or separate (3-part). */
489 bool use_monolithic_shaders
;
491 bool has_rbplus
; /* if RB+ registers exist */
492 bool rbplus_allowed
; /* if RB+ is allowed */
493 bool dcc_msaa_allowed
;
494 bool cpdma_prefetch_writes_memory
;
496 struct slab_parent_pool pool_transfers
;
498 /* Texture filter settings. */
499 int force_aniso
; /* -1 = disabled */
501 /* Auxiliary context. Mainly used to initialize resources.
502 * It must be locked prior to using and flushed before unlocking. */
503 struct pipe_context
*aux_context
;
504 mtx_t aux_context_lock
;
506 /* This must be in the screen, because UE4 uses one context for
507 * compilation and another one for rendering.
509 unsigned num_compilations
;
510 /* Along with ST_DEBUG=precompile, this should show if applications
511 * are loading shaders on demand. This is a monotonic counter.
513 unsigned num_shaders_created
;
514 unsigned num_shader_cache_hits
;
516 /* GPU load thread. */
517 mtx_t gpu_load_mutex
;
518 thrd_t gpu_load_thread
;
519 union si_mmio_counters mmio_counters
;
520 volatile unsigned gpu_load_stop_thread
; /* bool */
522 /* Performance counters. */
523 struct si_perfcounters
*perfcounters
;
525 /* If pipe_screen wants to recompute and re-emit the framebuffer,
526 * sampler, and image states of all contexts, it should atomically
529 * Each context will compare this with its own last known value of
530 * the counter before drawing and re-emit the states accordingly.
532 unsigned dirty_tex_counter
;
533 unsigned dirty_buf_counter
;
535 /* Atomically increment this counter when an existing texture's
536 * metadata is enabled or disabled in a way that requires changing
537 * contexts' compressed texture binding masks.
539 unsigned compressed_colortex_counter
;
542 /* Context flags to set so that all writes from earlier jobs
543 * in the CP are seen by L2 clients.
547 /* Context flags to set so that all writes from earlier jobs
548 * that end in L2 are seen by CP.
553 mtx_t shader_parts_mutex
;
554 struct si_shader_part
*vs_prologs
;
555 struct si_shader_part
*tcs_epilogs
;
556 struct si_shader_part
*gs_prologs
;
557 struct si_shader_part
*ps_prologs
;
558 struct si_shader_part
*ps_epilogs
;
560 /* Shader cache in memory.
562 * Design & limitations:
563 * - The shader cache is per screen (= per process), never saved to
564 * disk, and skips redundant shader compilations from TGSI to bytecode.
565 * - It can only be used with one-variant-per-shader support, in which
566 * case only the main (typically middle) part of shaders is cached.
567 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
568 * variants of VS and TES are cached, so LS and ES aren't.
569 * - GS and CS aren't cached, but it's certainly possible to cache
572 mtx_t shader_cache_mutex
;
573 struct hash_table
*shader_cache
;
575 /* Shader compiler queue for multithreaded compilation. */
576 struct util_queue shader_compiler_queue
;
577 /* Use at most 3 normal compiler threads on quadcore and better.
578 * Hyperthreaded CPUs report the number of threads, but we want
579 * the number of cores. We only need this many threads for shader-db. */
580 struct ac_llvm_compiler compiler
[24]; /* used by the queue only */
582 struct util_queue shader_compiler_queue_low_priority
;
583 /* Use at most 2 low priority threads on quadcore and better.
584 * We want to minimize the impact on multithreaded Mesa. */
585 struct ac_llvm_compiler compiler_lowp
[10];
588 struct si_blend_color
{
589 struct pipe_blend_color state
;
593 struct si_sampler_view
{
594 struct pipe_sampler_view base
;
595 /* [0..7] = image descriptor
596 * [4..7] = buffer descriptor */
598 uint32_t fmask_state
[8];
599 const struct legacy_surf_level
*base_level_info
;
602 bool is_stencil_sampler
;
604 bool dcc_incompatible
;
607 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
609 struct si_sampler_state
{
614 uint32_t integer_val
[4];
615 uint32_t upgraded_depth_val
[4];
618 struct si_cs_shader_state
{
619 struct si_compute
*program
;
620 struct si_compute
*emitted_program
;
627 struct pipe_sampler_view
*views
[SI_NUM_SAMPLERS
];
628 struct si_sampler_state
*sampler_states
[SI_NUM_SAMPLERS
];
630 /* The i-th bit is set if that element is enabled (non-NULL resource). */
631 unsigned enabled_mask
;
632 uint32_t needs_depth_decompress_mask
;
633 uint32_t needs_color_decompress_mask
;
637 struct pipe_image_view views
[SI_NUM_IMAGES
];
638 uint32_t needs_color_decompress_mask
;
639 unsigned enabled_mask
;
642 struct si_framebuffer
{
643 struct pipe_framebuffer_state state
;
644 unsigned colorbuf_enabled_4bit
;
645 unsigned spi_shader_col_format
;
646 unsigned spi_shader_col_format_alpha
;
647 unsigned spi_shader_col_format_blend
;
648 unsigned spi_shader_col_format_blend_alpha
;
649 ubyte nr_samples
:5; /* at most 16xAA */
650 ubyte log_samples
:3; /* at most 4 = 16xAA */
651 ubyte nr_color_samples
; /* at most 8xAA */
652 ubyte compressed_cb_mask
;
653 ubyte uncompressed_cb_mask
;
655 ubyte color_is_int10
;
657 ubyte dcc_overwrite_combiner_watermark
;
660 bool CB_has_shader_readable_metadata
;
661 bool DB_has_shader_readable_metadata
;
662 bool all_DCC_pipe_aligned
;
666 /* This is the list we want to support. */
667 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH
,
668 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH
,
669 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH
,
672 struct si_signed_scissor
{
677 enum si_quant_mode quant_mode
;
680 struct si_viewports
{
681 struct pipe_viewport_state states
[SI_MAX_VIEWPORTS
];
682 struct si_signed_scissor as_scissor
[SI_MAX_VIEWPORTS
];
686 struct si_clip_state
{
687 struct pipe_clip_state state
;
691 struct si_streamout_target
{
692 struct pipe_stream_output_target b
;
694 /* The buffer where BUFFER_FILLED_SIZE is stored. */
695 struct si_resource
*buf_filled_size
;
696 unsigned buf_filled_size_offset
;
697 bool buf_filled_size_valid
;
699 unsigned stride_in_dw
;
702 struct si_streamout
{
705 unsigned enabled_mask
;
706 unsigned num_targets
;
707 struct si_streamout_target
*targets
[PIPE_MAX_SO_BUFFERS
];
709 unsigned append_bitmask
;
712 /* External state which comes from the vertex shader,
713 * it must be set explicitly when binding a shader. */
714 uint16_t *stride_in_dw
;
715 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
717 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
718 unsigned hw_enabled_mask
;
720 /* The state of VGT_STRMOUT_(CONFIG|EN). */
721 bool streamout_enabled
;
722 bool prims_gen_query_enabled
;
723 int num_prims_gen_queries
;
726 /* A shader state consists of the shader selector, which is a constant state
727 * object shared by multiple contexts and shouldn't be modified, and
728 * the current shader variant selected for this context.
730 struct si_shader_ctx_state
{
731 struct si_shader_selector
*cso
;
732 struct si_shader
*current
;
735 #define SI_NUM_VGT_PARAM_KEY_BITS 12
736 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
738 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
739 * Some fields are set by state-change calls, most are set by draw_vbo.
741 union si_vgt_param_key
{
743 #ifdef PIPE_ARCH_LITTLE_ENDIAN
745 unsigned uses_instancing
:1;
746 unsigned multi_instances_smaller_than_primgroup
:1;
747 unsigned primitive_restart
:1;
748 unsigned count_from_stream_output
:1;
749 unsigned line_stipple_enabled
:1;
750 unsigned uses_tess
:1;
751 unsigned tess_uses_prim_id
:1;
753 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
754 #else /* PIPE_ARCH_BIG_ENDIAN */
755 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
757 unsigned tess_uses_prim_id
:1;
758 unsigned uses_tess
:1;
759 unsigned line_stipple_enabled
:1;
760 unsigned count_from_stream_output
:1;
761 unsigned primitive_restart
:1;
762 unsigned multi_instances_smaller_than_primgroup
:1;
763 unsigned uses_instancing
:1;
770 struct si_texture_handle
774 struct pipe_sampler_view
*view
;
775 struct si_sampler_state sstate
;
778 struct si_image_handle
782 struct pipe_image_view view
;
786 struct pipe_reference reference
;
787 struct si_context
*ctx
;
788 struct radeon_saved_cs gfx
;
789 struct radeon_saved_cs compute
;
790 struct si_resource
*trace_buf
;
793 unsigned gfx_last_dw
;
794 unsigned compute_last_dw
;
799 struct si_sdma_upload
{
800 struct si_resource
*dst
;
801 struct si_resource
*src
;
808 struct pipe_context b
; /* base class */
810 enum radeon_family family
;
811 enum chip_class chip_class
;
813 struct radeon_winsys
*ws
;
814 struct radeon_winsys_ctx
*ctx
;
815 struct radeon_cmdbuf
*gfx_cs
; /* compute IB if graphics is disabled */
816 struct radeon_cmdbuf
*dma_cs
;
817 struct pipe_fence_handle
*last_gfx_fence
;
818 struct pipe_fence_handle
*last_sdma_fence
;
819 struct si_resource
*eop_bug_scratch
;
820 struct u_upload_mgr
*cached_gtt_allocator
;
821 struct threaded_context
*tc
;
822 struct u_suballocator
*allocator_zeroed_memory
;
823 struct slab_child_pool pool_transfers
;
824 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
825 struct pipe_device_reset_callback device_reset_callback
;
826 struct u_log_context
*log
;
827 void *query_result_shader
;
828 struct blitter_context
*blitter
;
829 void *custom_dsa_flush
;
830 void *custom_blend_resolve
;
831 void *custom_blend_fmask_decompress
;
832 void *custom_blend_eliminate_fastclear
;
833 void *custom_blend_dcc_decompress
;
835 void *vs_blit_pos_layered
;
837 void *vs_blit_color_layered
;
838 void *vs_blit_texcoord
;
839 void *cs_clear_buffer
;
840 void *cs_copy_buffer
;
842 void *cs_copy_image_1d_array
;
843 void *cs_clear_render_target
;
844 void *cs_clear_render_target_1d_array
;
846 struct si_screen
*screen
;
847 struct pipe_debug_callback debug
;
848 struct ac_llvm_compiler compiler
; /* only non-threaded compilation */
849 struct si_shader_ctx_state fixed_func_tcs_shader
;
850 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
851 struct si_resource
*wait_mem_scratch
;
852 unsigned wait_mem_number
;
853 uint16_t prefetch_L2_mask
;
856 bool gfx_flush_in_progress
:1;
857 bool gfx_last_ib_is_busy
:1;
858 bool compute_is_busy
:1;
860 unsigned num_gfx_cs_flushes
;
861 unsigned initial_gfx_cs_size
;
862 unsigned gpu_reset_counter
;
863 unsigned last_dirty_tex_counter
;
864 unsigned last_dirty_buf_counter
;
865 unsigned last_compressed_colortex_counter
;
866 unsigned last_num_draw_calls
;
867 unsigned flags
; /* flush flags */
868 /* Current unaccounted memory usage. */
872 /* Compute-based primitive discard. */
873 unsigned prim_discard_vertex_count_threshold
;
874 struct pb_buffer
*gds
;
875 struct pb_buffer
*gds_oa
;
876 struct radeon_cmdbuf
*prim_discard_compute_cs
;
877 unsigned compute_gds_offset
;
878 struct si_shader
*compute_ib_last_shader
;
879 uint32_t compute_rewind_va
;
880 unsigned compute_num_prims_in_batch
;
881 bool preserve_prim_restart_gds_at_flush
;
882 /* index_ring is divided into 2 halves for doublebuffering. */
883 struct si_resource
*index_ring
;
884 unsigned index_ring_base
; /* offset of a per-IB portion */
885 unsigned index_ring_offset
; /* offset within a per-IB portion */
886 unsigned index_ring_size_per_ib
; /* max available size per IB */
887 bool prim_discard_compute_ib_initialized
;
888 /* For tracking the last execution barrier - it can be either
889 * a WRITE_DATA packet or a fence. */
890 uint32_t *last_pkt3_write_data
;
891 struct si_resource
*barrier_buf
;
892 unsigned barrier_buf_offset
;
893 struct pipe_fence_handle
*last_ib_barrier_fence
;
894 struct si_resource
*last_ib_barrier_buf
;
895 unsigned last_ib_barrier_buf_offset
;
897 /* Atoms (direct states). */
898 union si_state_atoms atoms
;
899 unsigned dirty_atoms
; /* mask */
900 /* PM4 states (precomputed immutable states) */
901 unsigned dirty_states
;
902 union si_state queued
;
903 union si_state emitted
;
905 /* Atom declarations. */
906 struct si_framebuffer framebuffer
;
907 unsigned sample_locs_num_samples
;
908 uint16_t sample_mask
;
909 unsigned last_cb_target_mask
;
910 struct si_blend_color blend_color
;
911 struct si_clip_state clip_state
;
912 struct si_shader_data shader_pointers
;
913 struct si_stencil_ref stencil_ref
;
914 struct pipe_scissor_state scissors
[SI_MAX_VIEWPORTS
];
915 struct si_streamout streamout
;
916 struct si_viewports viewports
;
917 unsigned num_window_rectangles
;
918 bool window_rectangles_include
;
919 struct pipe_scissor_state window_rectangles
[4];
921 /* Precomputed states. */
922 struct si_pm4_state
*init_config
;
923 struct si_pm4_state
*init_config_gs_rings
;
924 bool init_config_has_vgt_flush
;
925 struct si_pm4_state
*vgt_shader_config
[4];
928 struct si_shader_ctx_state ps_shader
;
929 struct si_shader_ctx_state gs_shader
;
930 struct si_shader_ctx_state vs_shader
;
931 struct si_shader_ctx_state tcs_shader
;
932 struct si_shader_ctx_state tes_shader
;
933 struct si_shader_ctx_state cs_prim_discard_state
;
934 struct si_cs_shader_state cs_shader_state
;
936 /* shader information */
937 struct si_vertex_elements
*vertex_elements
;
938 unsigned sprite_coord_enable
;
939 unsigned cs_max_waves_per_sh
;
941 bool do_update_shaders
;
943 /* vertex buffer descriptors */
944 uint32_t *vb_descriptors_gpu_list
;
945 struct si_resource
*vb_descriptors_buffer
;
946 unsigned vb_descriptors_offset
;
948 /* shader descriptors */
949 struct si_descriptors descriptors
[SI_NUM_DESCS
];
950 unsigned descriptors_dirty
;
951 unsigned shader_pointers_dirty
;
952 unsigned shader_needs_decompress_mask
;
953 struct si_buffer_resources rw_buffers
;
954 struct si_buffer_resources const_and_shader_buffers
[SI_NUM_SHADERS
];
955 struct si_samplers samplers
[SI_NUM_SHADERS
];
956 struct si_images images
[SI_NUM_SHADERS
];
957 bool bo_list_add_all_resident_resources
;
958 bool bo_list_add_all_gfx_resources
;
959 bool bo_list_add_all_compute_resources
;
961 /* other shader resources */
962 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on GFX7 */
963 struct pipe_resource
*esgs_ring
;
964 struct pipe_resource
*gsvs_ring
;
965 struct pipe_resource
*tess_rings
;
966 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
967 struct si_resource
*border_color_buffer
;
968 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
969 unsigned border_color_count
;
970 unsigned num_vs_blit_sgprs
;
971 uint32_t vs_blit_sh_data
[SI_VS_BLIT_SGPRS_POS_TEXCOORD
];
972 uint32_t cs_user_data
[4];
974 /* Vertex and index buffers. */
975 bool vertex_buffers_dirty
;
976 bool vertex_buffer_pointer_dirty
;
977 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
978 uint16_t vertex_buffer_unaligned
; /* bitmask of not dword-aligned buffers */
980 /* MSAA config state. */
982 bool ps_uses_fbfetch
;
983 bool smoothing_enabled
;
985 /* DB render state. */
986 unsigned ps_db_shader_control
;
987 unsigned dbcb_copy_sample
;
988 bool dbcb_depth_copy_enabled
:1;
989 bool dbcb_stencil_copy_enabled
:1;
990 bool db_flush_depth_inplace
:1;
991 bool db_flush_stencil_inplace
:1;
992 bool db_depth_clear
:1;
993 bool db_depth_disable_expclear
:1;
994 bool db_stencil_clear
:1;
995 bool db_stencil_disable_expclear
:1;
996 bool occlusion_queries_disabled
:1;
997 bool generate_mipmap_for_depth
:1;
999 /* Emitted draw state. */
1000 bool gs_tri_strip_adj_fix
:1;
1002 bool prim_discard_cs_instancing
:1;
1003 int last_index_size
;
1004 int last_base_vertex
;
1005 int last_start_instance
;
1006 int last_instance_count
;
1008 int last_sh_base_reg
;
1009 int last_primitive_restart_en
;
1010 int last_restart_index
;
1012 int last_multi_vgt_param
;
1014 unsigned last_sc_line_stipple
;
1015 unsigned current_vs_state
;
1016 unsigned last_vs_state
;
1017 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
1019 /* Scratch buffer */
1020 struct si_resource
*scratch_buffer
;
1021 unsigned scratch_waves
;
1022 unsigned spi_tmpring_size
;
1024 struct si_resource
*compute_scratch_buffer
;
1026 /* Emitted derived tessellation state. */
1027 /* Local shader (VS), or HS if LS-HS are merged. */
1028 struct si_shader
*last_ls
;
1029 struct si_shader_selector
*last_tcs
;
1030 int last_num_tcs_input_cp
;
1031 int last_tes_sh_base
;
1032 bool last_tess_uses_primid
;
1033 unsigned last_num_patches
;
1034 int last_ls_hs_config
;
1038 struct si_saved_cs
*current_saved_cs
;
1039 uint64_t dmesg_timestamp
;
1040 unsigned apitrace_call_number
;
1043 bool need_check_render_feedback
;
1044 bool decompression_enabled
;
1045 bool dpbb_force_off
;
1046 bool vs_writes_viewport_index
;
1047 bool vs_disables_clipping_viewport
;
1049 /* Precomputed IA_MULTI_VGT_PARAM */
1050 union si_vgt_param_key ia_multi_vgt_param_key
;
1051 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
1053 /* Bindless descriptors. */
1054 struct si_descriptors bindless_descriptors
;
1055 struct util_idalloc bindless_used_slots
;
1056 unsigned num_bindless_descriptors
;
1057 bool bindless_descriptors_dirty
;
1058 bool graphics_bindless_pointer_dirty
;
1059 bool compute_bindless_pointer_dirty
;
1061 /* Allocated bindless handles */
1062 struct hash_table
*tex_handles
;
1063 struct hash_table
*img_handles
;
1065 /* Resident bindless handles */
1066 struct util_dynarray resident_tex_handles
;
1067 struct util_dynarray resident_img_handles
;
1069 /* Resident bindless handles which need decompression */
1070 struct util_dynarray resident_tex_needs_color_decompress
;
1071 struct util_dynarray resident_img_needs_color_decompress
;
1072 struct util_dynarray resident_tex_needs_depth_decompress
;
1074 /* Bindless state */
1075 bool uses_bindless_samplers
;
1076 bool uses_bindless_images
;
1078 /* MSAA sample locations.
1079 * The first index is the sample index.
1080 * The second index is the coordinate: X, Y. */
1088 struct pipe_resource
*sample_pos_buffer
;
1091 unsigned num_draw_calls
;
1092 unsigned num_decompress_calls
;
1093 unsigned num_mrt_draw_calls
;
1094 unsigned num_prim_restart_calls
;
1095 unsigned num_spill_draw_calls
;
1096 unsigned num_compute_calls
;
1097 unsigned num_spill_compute_calls
;
1098 unsigned num_dma_calls
;
1099 unsigned num_cp_dma_calls
;
1100 unsigned num_vs_flushes
;
1101 unsigned num_ps_flushes
;
1102 unsigned num_cs_flushes
;
1103 unsigned num_cb_cache_flushes
;
1104 unsigned num_db_cache_flushes
;
1105 unsigned num_L2_invalidates
;
1106 unsigned num_L2_writebacks
;
1107 unsigned num_resident_handles
;
1108 uint64_t num_alloc_tex_transfer_bytes
;
1109 unsigned last_tex_ps_draw_ratio
; /* for query */
1110 unsigned compute_num_verts_accepted
;
1111 unsigned compute_num_verts_rejected
;
1112 unsigned compute_num_verts_ineligible
; /* due to low vertex count */
1113 unsigned context_roll
;
1116 /* Maintain the list of active queries for pausing between IBs. */
1117 int num_occlusion_queries
;
1118 int num_perfect_occlusion_queries
;
1119 int num_pipeline_stat_queries
;
1120 struct list_head active_queries
;
1121 unsigned num_cs_dw_queries_suspend
;
1123 /* Render condition. */
1124 struct pipe_query
*render_cond
;
1125 unsigned render_cond_mode
;
1126 bool render_cond_invert
;
1127 bool render_cond_force_off
; /* for u_blitter */
1129 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1130 bool sdma_uploads_in_progress
;
1131 struct si_sdma_upload
*sdma_uploads
;
1132 unsigned num_sdma_uploads
;
1133 unsigned max_sdma_uploads
;
1135 /* Statistics gathering for the DCC enablement heuristic. It can't be
1136 * in si_texture because si_texture can be shared by multiple
1137 * contexts. This is for back buffers only. We shouldn't get too many
1140 * X11 DRI3 rotates among a finite set of back buffers. They should
1141 * all fit in this array. If they don't, separate DCC might never be
1142 * enabled by DCC stat gathering.
1145 struct si_texture
*tex
;
1146 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1147 struct pipe_query
*ps_stats
[3];
1148 /* If all slots are used and another slot is needed,
1149 * the least recently used slot is evicted based on this. */
1150 int64_t last_use_timestamp
;
1154 /* Copy one resource to another using async DMA. */
1155 void (*dma_copy
)(struct pipe_context
*ctx
,
1156 struct pipe_resource
*dst
,
1158 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
1159 struct pipe_resource
*src
,
1161 const struct pipe_box
*src_box
);
1163 struct si_tracked_regs tracked_regs
;
1167 void cik_init_sdma_functions(struct si_context
*sctx
);
1170 enum si_blitter_op
/* bitmask */
1172 SI_SAVE_TEXTURES
= 1,
1173 SI_SAVE_FRAMEBUFFER
= 2,
1174 SI_SAVE_FRAGMENT_STATE
= 4,
1175 SI_DISABLE_RENDER_COND
= 8,
1178 void si_blitter_begin(struct si_context
*sctx
, enum si_blitter_op op
);
1179 void si_blitter_end(struct si_context
*sctx
);
1180 void si_init_blit_functions(struct si_context
*sctx
);
1181 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
);
1182 void si_resource_copy_region(struct pipe_context
*ctx
,
1183 struct pipe_resource
*dst
,
1185 unsigned dstx
, unsigned dsty
, unsigned dstz
,
1186 struct pipe_resource
*src
,
1188 const struct pipe_box
*src_box
);
1189 void si_decompress_dcc(struct si_context
*sctx
, struct si_texture
*tex
);
1190 void si_blit_decompress_depth(struct pipe_context
*ctx
,
1191 struct si_texture
*texture
,
1192 struct si_texture
*staging
,
1193 unsigned first_level
, unsigned last_level
,
1194 unsigned first_layer
, unsigned last_layer
,
1195 unsigned first_sample
, unsigned last_sample
);
1198 bool si_rings_is_buffer_referenced(struct si_context
*sctx
,
1199 struct pb_buffer
*buf
,
1200 enum radeon_bo_usage usage
);
1201 void *si_buffer_map_sync_with_rings(struct si_context
*sctx
,
1202 struct si_resource
*resource
,
1204 void si_init_resource_fields(struct si_screen
*sscreen
,
1205 struct si_resource
*res
,
1206 uint64_t size
, unsigned alignment
);
1207 bool si_alloc_resource(struct si_screen
*sscreen
,
1208 struct si_resource
*res
);
1209 struct pipe_resource
*pipe_aligned_buffer_create(struct pipe_screen
*screen
,
1210 unsigned flags
, unsigned usage
,
1211 unsigned size
, unsigned alignment
);
1212 struct si_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
,
1213 unsigned flags
, unsigned usage
,
1214 unsigned size
, unsigned alignment
);
1215 void si_replace_buffer_storage(struct pipe_context
*ctx
,
1216 struct pipe_resource
*dst
,
1217 struct pipe_resource
*src
);
1218 void si_init_screen_buffer_functions(struct si_screen
*sscreen
);
1219 void si_init_buffer_functions(struct si_context
*sctx
);
1222 enum pipe_format
si_simplify_cb_format(enum pipe_format format
);
1223 bool vi_alpha_is_on_msb(enum pipe_format format
);
1224 void vi_dcc_clear_level(struct si_context
*sctx
,
1225 struct si_texture
*tex
,
1226 unsigned level
, unsigned clear_value
);
1227 void si_init_clear_functions(struct si_context
*sctx
);
1229 /* si_compute_blit.c */
1230 unsigned si_get_flush_flags(struct si_context
*sctx
, enum si_coherency coher
,
1231 enum si_cache_policy cache_policy
);
1232 void si_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1233 uint64_t offset
, uint64_t size
, uint32_t *clear_value
,
1234 uint32_t clear_value_size
, enum si_coherency coher
,
1236 void si_copy_buffer(struct si_context
*sctx
,
1237 struct pipe_resource
*dst
, struct pipe_resource
*src
,
1238 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
);
1239 void si_compute_copy_image(struct si_context
*sctx
,
1240 struct pipe_resource
*dst
,
1242 struct pipe_resource
*src
,
1244 unsigned dstx
, unsigned dsty
, unsigned dstz
,
1245 const struct pipe_box
*src_box
);
1246 void si_compute_clear_render_target(struct pipe_context
*ctx
,
1247 struct pipe_surface
*dstsurf
,
1248 const union pipe_color_union
*color
,
1249 unsigned dstx
, unsigned dsty
,
1250 unsigned width
, unsigned height
,
1251 bool render_condition_enabled
);
1252 void si_retile_dcc(struct si_context
*sctx
, struct si_texture
*tex
);
1253 void si_init_compute_blit_functions(struct si_context
*sctx
);
1256 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1257 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1258 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1259 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1260 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1261 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1262 SI_CPDMA_SKIP_SYNC_AFTER | \
1263 SI_CPDMA_SKIP_SYNC_BEFORE | \
1264 SI_CPDMA_SKIP_GFX_SYNC | \
1265 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1267 void si_cp_dma_wait_for_idle(struct si_context
*sctx
);
1268 void si_cp_dma_clear_buffer(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
,
1269 struct pipe_resource
*dst
, uint64_t offset
,
1270 uint64_t size
, unsigned value
, unsigned user_flags
,
1271 enum si_coherency coher
, enum si_cache_policy cache_policy
);
1272 void si_cp_dma_copy_buffer(struct si_context
*sctx
,
1273 struct pipe_resource
*dst
, struct pipe_resource
*src
,
1274 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
1275 unsigned user_flags
, enum si_coherency coher
,
1276 enum si_cache_policy cache_policy
);
1277 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
1278 uint64_t offset
, unsigned size
);
1279 void cik_emit_prefetch_L2(struct si_context
*sctx
, bool vertex_stage_only
);
1280 void si_test_gds(struct si_context
*sctx
);
1281 void si_cp_write_data(struct si_context
*sctx
, struct si_resource
*buf
,
1282 unsigned offset
, unsigned size
, unsigned dst_sel
,
1283 unsigned engine
, const void *data
);
1284 void si_cp_copy_data(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
,
1285 unsigned dst_sel
, struct si_resource
*dst
, unsigned dst_offset
,
1286 unsigned src_sel
, struct si_resource
*src
, unsigned src_offset
);
1289 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_cmdbuf
*cs
,
1290 struct radeon_saved_cs
*saved
, bool get_buffer_list
);
1291 void si_clear_saved_cs(struct radeon_saved_cs
*saved
);
1292 void si_destroy_saved_cs(struct si_saved_cs
*scs
);
1293 void si_auto_log_cs(void *data
, struct u_log_context
*log
);
1294 void si_log_hw_flush(struct si_context
*sctx
);
1295 void si_log_draw_state(struct si_context
*sctx
, struct u_log_context
*log
);
1296 void si_log_compute_state(struct si_context
*sctx
, struct u_log_context
*log
);
1297 void si_init_debug_functions(struct si_context
*sctx
);
1298 void si_check_vm_faults(struct si_context
*sctx
,
1299 struct radeon_saved_cs
*saved
, enum ring_type ring
);
1300 bool si_replace_shader(unsigned num
, struct ac_shader_binary
*binary
);
1303 void si_init_dma_functions(struct si_context
*sctx
);
1306 void si_dma_emit_timestamp(struct si_context
*sctx
, struct si_resource
*dst
,
1308 void si_sdma_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1309 uint64_t offset
, uint64_t size
, unsigned clear_value
);
1310 void si_need_dma_space(struct si_context
*ctx
, unsigned num_dw
,
1311 struct si_resource
*dst
, struct si_resource
*src
);
1312 void si_flush_dma_cs(struct si_context
*ctx
, unsigned flags
,
1313 struct pipe_fence_handle
**fence
);
1314 void si_screen_clear_buffer(struct si_screen
*sscreen
, struct pipe_resource
*dst
,
1315 uint64_t offset
, uint64_t size
, unsigned value
);
1318 void si_cp_release_mem(struct si_context
*ctx
, struct radeon_cmdbuf
*cs
,
1319 unsigned event
, unsigned event_flags
,
1320 unsigned dst_sel
, unsigned int_sel
, unsigned data_sel
,
1321 struct si_resource
*buf
, uint64_t va
,
1322 uint32_t new_fence
, unsigned query_type
);
1323 unsigned si_cp_write_fence_dwords(struct si_screen
*screen
);
1324 void si_cp_wait_mem(struct si_context
*ctx
, struct radeon_cmdbuf
*cs
,
1325 uint64_t va
, uint32_t ref
, uint32_t mask
, unsigned flags
);
1326 void si_init_fence_functions(struct si_context
*ctx
);
1327 void si_init_screen_fence_functions(struct si_screen
*screen
);
1328 struct pipe_fence_handle
*si_create_fence(struct pipe_context
*ctx
,
1329 struct tc_unflushed_batch_token
*tc_token
);
1332 void si_init_screen_get_functions(struct si_screen
*sscreen
);
1335 void si_flush_gfx_cs(struct si_context
*ctx
, unsigned flags
,
1336 struct pipe_fence_handle
**fence
);
1337 void si_begin_new_gfx_cs(struct si_context
*ctx
);
1338 void si_need_gfx_cs_space(struct si_context
*ctx
);
1339 void si_unref_sdma_uploads(struct si_context
*sctx
);
1342 void si_gpu_load_kill_thread(struct si_screen
*sscreen
);
1343 uint64_t si_begin_counter(struct si_screen
*sscreen
, unsigned type
);
1344 unsigned si_end_counter(struct si_screen
*sscreen
, unsigned type
,
1348 void si_emit_initial_compute_regs(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
);
1349 unsigned si_get_compute_resource_limits(struct si_screen
*sscreen
,
1350 unsigned waves_per_threadgroup
,
1351 unsigned max_waves_per_sh
,
1352 unsigned threadgroups_per_cu
);
1353 void si_init_compute_functions(struct si_context
*sctx
);
1355 /* si_compute_prim_discard.c */
1356 enum si_prim_discard_outcome
{
1357 SI_PRIM_DISCARD_ENABLED
,
1358 SI_PRIM_DISCARD_DISABLED
,
1359 SI_PRIM_DISCARD_DRAW_SPLIT
,
1362 void si_build_prim_discard_compute_shader(struct si_shader_context
*ctx
);
1363 enum si_prim_discard_outcome
1364 si_prepare_prim_discard_or_split_draw(struct si_context
*sctx
,
1365 const struct pipe_draw_info
*info
,
1366 bool primitive_restart
);
1367 void si_compute_signal_gfx(struct si_context
*sctx
);
1368 void si_dispatch_prim_discard_cs_and_draw(struct si_context
*sctx
,
1369 const struct pipe_draw_info
*info
,
1370 unsigned index_size
,
1371 unsigned base_vertex
,
1372 uint64_t input_indexbuf_va
,
1373 unsigned input_indexbuf_max_elements
);
1374 void si_initialize_prim_discard_tunables(struct si_context
*sctx
);
1376 /* si_perfcounters.c */
1377 void si_init_perfcounters(struct si_screen
*screen
);
1378 void si_destroy_perfcounters(struct si_screen
*screen
);
1381 bool si_check_device_reset(struct si_context
*sctx
);
1384 void si_init_screen_query_functions(struct si_screen
*sscreen
);
1385 void si_init_query_functions(struct si_context
*sctx
);
1386 void si_suspend_queries(struct si_context
*sctx
);
1387 void si_resume_queries(struct si_context
*sctx
);
1389 /* si_shaderlib_tgsi.c */
1390 void *si_get_blitter_vs(struct si_context
*sctx
, enum blitter_attrib_type type
,
1391 unsigned num_layers
);
1392 void *si_create_fixed_func_tcs(struct si_context
*sctx
);
1393 void *si_create_dma_compute_shader(struct pipe_context
*ctx
,
1394 unsigned num_dwords_per_thread
,
1395 bool dst_stream_cache_policy
, bool is_copy
);
1396 void *si_create_copy_image_compute_shader(struct pipe_context
*ctx
);
1397 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context
*ctx
);
1398 void *si_clear_render_target_shader(struct pipe_context
*ctx
);
1399 void *si_clear_render_target_shader_1d_array(struct pipe_context
*ctx
);
1400 void *si_create_dcc_retile_cs(struct pipe_context
*ctx
);
1401 void *si_create_query_result_cs(struct si_context
*sctx
);
1404 void si_test_dma(struct si_screen
*sscreen
);
1406 /* si_test_clearbuffer.c */
1407 void si_test_dma_perf(struct si_screen
*sscreen
);
1410 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
1411 const struct pipe_video_codec
*templ
);
1413 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
1414 const struct pipe_video_buffer
*tmpl
);
1417 void si_update_vs_viewport_state(struct si_context
*ctx
);
1418 void si_init_viewport_functions(struct si_context
*ctx
);
1421 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
1422 struct si_texture
*dst
,
1423 unsigned dst_level
, unsigned dstx
,
1424 unsigned dsty
, unsigned dstz
,
1425 struct si_texture
*src
,
1427 const struct pipe_box
*src_box
);
1428 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
1429 struct si_texture
*tex
);
1430 void si_texture_discard_cmask(struct si_screen
*sscreen
,
1431 struct si_texture
*tex
);
1432 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1433 struct pipe_resource
*texture
,
1434 struct si_texture
**staging
);
1435 void si_print_texture_info(struct si_screen
*sscreen
,
1436 struct si_texture
*tex
, struct u_log_context
*log
);
1437 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1438 const struct pipe_resource
*templ
);
1439 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1440 enum pipe_format format2
);
1441 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1443 enum pipe_format view_format
);
1444 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
1445 struct pipe_resource
*tex
,
1447 enum pipe_format view_format
);
1448 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1449 struct pipe_resource
*texture
,
1450 const struct pipe_surface
*templ
,
1451 unsigned width0
, unsigned height0
,
1452 unsigned width
, unsigned height
);
1453 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
1454 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
1455 struct si_texture
*tex
);
1456 void vi_separate_dcc_start_query(struct si_context
*sctx
,
1457 struct si_texture
*tex
);
1458 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
1459 struct si_texture
*tex
);
1460 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
1461 struct si_texture
*tex
);
1462 bool si_texture_disable_dcc(struct si_context
*sctx
,
1463 struct si_texture
*tex
);
1464 void si_init_screen_texture_functions(struct si_screen
*sscreen
);
1465 void si_init_context_texture_functions(struct si_context
*sctx
);
1472 static inline struct si_resource
*si_resource(struct pipe_resource
*r
)
1474 return (struct si_resource
*)r
;
1478 si_resource_reference(struct si_resource
**ptr
, struct si_resource
*res
)
1480 pipe_resource_reference((struct pipe_resource
**)ptr
,
1481 (struct pipe_resource
*)res
);
1485 si_texture_reference(struct si_texture
**ptr
, struct si_texture
*res
)
1487 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->buffer
.b
.b
);
1491 vi_dcc_enabled(struct si_texture
*tex
, unsigned level
)
1493 return tex
->dcc_offset
&& level
< tex
->surface
.num_dcc_levels
;
1496 static inline unsigned
1497 si_tile_mode_index(struct si_texture
*tex
, unsigned level
, bool stencil
)
1500 return tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
1502 return tex
->surface
.u
.legacy
.tiling_index
[level
];
1505 static inline unsigned
1506 si_get_minimum_num_gfx_cs_dwords(struct si_context
*sctx
)
1508 /* Don't count the needed CS space exactly and just use an upper bound.
1510 * Also reserve space for stopping queries at the end of IB, because
1511 * the number of active queries is unlimited in theory.
1513 return 2048 + sctx
->num_cs_dw_queries_suspend
;
1517 si_context_add_resource_size(struct si_context
*sctx
, struct pipe_resource
*r
)
1520 /* Add memory usage for need_gfx_cs_space */
1521 sctx
->vram
+= si_resource(r
)->vram_usage
;
1522 sctx
->gtt
+= si_resource(r
)->gart_usage
;
1527 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
1529 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
1530 sctx
->last_instance_count
= SI_INSTANCE_COUNT_UNKNOWN
;
1533 static inline unsigned
1534 si_get_atom_bit(struct si_context
*sctx
, struct si_atom
*atom
)
1536 return 1 << (atom
- sctx
->atoms
.array
);
1540 si_set_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
, bool dirty
)
1542 unsigned bit
= si_get_atom_bit(sctx
, atom
);
1545 sctx
->dirty_atoms
|= bit
;
1547 sctx
->dirty_atoms
&= ~bit
;
1551 si_is_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1553 return (sctx
->dirty_atoms
& si_get_atom_bit(sctx
, atom
)) != 0;
1557 si_mark_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1559 si_set_atom_dirty(sctx
, atom
, true);
1562 static inline struct si_shader_ctx_state
*si_get_vs(struct si_context
*sctx
)
1564 if (sctx
->gs_shader
.cso
)
1565 return &sctx
->gs_shader
;
1566 if (sctx
->tes_shader
.cso
)
1567 return &sctx
->tes_shader
;
1569 return &sctx
->vs_shader
;
1572 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
1574 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1576 return vs
->cso
? &vs
->cso
->info
: NULL
;
1579 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
1581 if (sctx
->gs_shader
.cso
)
1582 return sctx
->gs_shader
.cso
->gs_copy_shader
;
1584 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1585 return vs
->current
? vs
->current
: NULL
;
1588 static inline bool si_can_dump_shader(struct si_screen
*sscreen
,
1591 return sscreen
->debug_flags
& (1 << processor
);
1594 static inline bool si_get_strmout_en(struct si_context
*sctx
)
1596 return sctx
->streamout
.streamout_enabled
||
1597 sctx
->streamout
.prims_gen_query_enabled
;
1600 static inline unsigned
1601 si_optimal_tcc_alignment(struct si_context
*sctx
, unsigned upload_size
)
1603 unsigned alignment
, tcc_cache_line_size
;
1605 /* If the upload size is less than the cache line size (e.g. 16, 32),
1606 * the whole thing will fit into a cache line if we align it to its size.
1607 * The idea is that multiple small uploads can share a cache line.
1608 * If the upload size is greater, align it to the cache line size.
1610 alignment
= util_next_power_of_two(upload_size
);
1611 tcc_cache_line_size
= sctx
->screen
->info
.tcc_cache_line_size
;
1612 return MIN2(alignment
, tcc_cache_line_size
);
1616 si_saved_cs_reference(struct si_saved_cs
**dst
, struct si_saved_cs
*src
)
1618 if (pipe_reference(&(*dst
)->reference
, &src
->reference
))
1619 si_destroy_saved_cs(*dst
);
1625 si_make_CB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1626 bool shaders_read_metadata
, bool dcc_pipe_aligned
)
1628 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
|
1629 SI_CONTEXT_INV_VMEM_L1
;
1631 if (sctx
->chip_class
>= GFX9
) {
1632 /* Single-sample color is coherent with shaders on GFX9, but
1633 * L2 metadata must be flushed if shaders read metadata.
1636 if (num_samples
>= 2 ||
1637 (shaders_read_metadata
&& !dcc_pipe_aligned
))
1638 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1639 else if (shaders_read_metadata
)
1640 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1643 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1648 si_make_DB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1649 bool include_stencil
, bool shaders_read_metadata
)
1651 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB
|
1652 SI_CONTEXT_INV_VMEM_L1
;
1654 if (sctx
->chip_class
>= GFX9
) {
1655 /* Single-sample depth (not stencil) is coherent with shaders
1656 * on GFX9, but L2 metadata must be flushed if shaders read
1659 if (num_samples
>= 2 || include_stencil
)
1660 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1661 else if (shaders_read_metadata
)
1662 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1665 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1670 si_can_sample_zs(struct si_texture
*tex
, bool stencil_sampler
)
1672 return (stencil_sampler
&& tex
->can_sample_s
) ||
1673 (!stencil_sampler
&& tex
->can_sample_z
);
1677 si_htile_enabled(struct si_texture
*tex
, unsigned level
)
1679 return tex
->htile_offset
&& level
== 0;
1683 vi_tc_compat_htile_enabled(struct si_texture
*tex
, unsigned level
)
1685 assert(!tex
->tc_compatible_htile
|| tex
->htile_offset
);
1686 return tex
->tc_compatible_htile
&& level
== 0;
1689 static inline unsigned si_get_ps_iter_samples(struct si_context
*sctx
)
1691 if (sctx
->ps_uses_fbfetch
)
1692 return sctx
->framebuffer
.nr_color_samples
;
1694 return MIN2(sctx
->ps_iter_samples
, sctx
->framebuffer
.nr_color_samples
);
1697 static inline unsigned si_get_total_colormask(struct si_context
*sctx
)
1699 if (sctx
->queued
.named
.rasterizer
->rasterizer_discard
)
1702 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1706 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
1707 sctx
->queued
.named
.blend
->cb_target_mask
;
1709 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
1710 colormask
&= ps
->colors_written_4bit
;
1711 else if (!ps
->colors_written_4bit
)
1712 colormask
= 0; /* color0 writes all cbufs, but it's not written */
1717 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1718 (1 << PIPE_PRIM_LINE_LOOP) | \
1719 (1 << PIPE_PRIM_LINE_STRIP) | \
1720 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1721 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1723 static inline bool util_prim_is_lines(unsigned prim
)
1725 return ((1 << prim
) & UTIL_ALL_PRIM_LINE_MODES
) != 0;
1728 static inline bool util_prim_is_points_or_lines(unsigned prim
)
1730 return ((1 << prim
) & (UTIL_ALL_PRIM_LINE_MODES
|
1731 (1 << PIPE_PRIM_POINTS
))) != 0;
1735 * Return true if there is enough memory in VRAM and GTT for the buffers
1738 * \param vram VRAM memory size not added to the buffer list yet
1739 * \param gtt GTT memory size not added to the buffer list yet
1742 radeon_cs_memory_below_limit(struct si_screen
*screen
,
1743 struct radeon_cmdbuf
*cs
,
1744 uint64_t vram
, uint64_t gtt
)
1746 vram
+= cs
->used_vram
;
1747 gtt
+= cs
->used_gart
;
1749 /* Anything that goes above the VRAM size should go to GTT. */
1750 if (vram
> screen
->info
.vram_size
)
1751 gtt
+= vram
- screen
->info
.vram_size
;
1753 /* Now we just need to check if we have enough GTT. */
1754 return gtt
< screen
->info
.gart_size
* 0.7;
1758 * Add a buffer to the buffer list for the given command stream (CS).
1760 * All buffers used by a CS must be added to the list. This tells the kernel
1761 * driver which buffers are used by GPU commands. Other buffers can
1762 * be swapped out (not accessible) during execution.
1764 * The buffer list becomes empty after every context flush and must be
1767 static inline void radeon_add_to_buffer_list(struct si_context
*sctx
,
1768 struct radeon_cmdbuf
*cs
,
1769 struct si_resource
*bo
,
1770 enum radeon_bo_usage usage
,
1771 enum radeon_bo_priority priority
)
1774 sctx
->ws
->cs_add_buffer(
1776 (enum radeon_bo_usage
)(usage
| RADEON_USAGE_SYNCHRONIZED
),
1777 bo
->domains
, priority
);
1781 * Same as above, but also checks memory usage and flushes the context
1784 * When this SHOULD NOT be used:
1786 * - if si_context_add_resource_size has been called for the buffer
1787 * followed by *_need_cs_space for checking the memory usage
1789 * - if si_need_dma_space has been called for the buffer
1791 * - when emitting state packets and draw packets (because preceding packets
1792 * can't be re-emitted at that point)
1794 * - if shader resource "enabled_mask" is not up-to-date or there is
1795 * a different constraint disallowing a context flush
1798 radeon_add_to_gfx_buffer_list_check_mem(struct si_context
*sctx
,
1799 struct si_resource
*bo
,
1800 enum radeon_bo_usage usage
,
1801 enum radeon_bo_priority priority
,
1805 !radeon_cs_memory_below_limit(sctx
->screen
, sctx
->gfx_cs
,
1806 sctx
->vram
+ bo
->vram_usage
,
1807 sctx
->gtt
+ bo
->gart_usage
))
1808 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1810 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, bo
, usage
, priority
);
1813 static inline bool si_compute_prim_discard_enabled(struct si_context
*sctx
)
1815 return sctx
->prim_discard_vertex_count_threshold
!= UINT_MAX
;
1818 #define PRINT_ERR(fmt, args...) \
1819 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)