src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef SI_PIPE_H
  27 #define SI_PIPE_H
  28
  29 #include "si_shader.h"
  30
  31 #ifdef PIPE_ARCH_BIG_ENDIAN
  32 #define SI_BIG_ENDIAN 1
  33 #else
  34 #define SI_BIG_ENDIAN 0
  35 #endif
  36
  37 /* The base vertex and primitive restart can be any number, but we must pick
  38  * one which will mean "unknown" for the purpose of state tracking and
  39  * the number shouldn't be a commonly-used one. */
  40 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  41 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  42 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  43 #define SI_GS_PER_ES 128
  44
  45 /* Instruction cache. */
  46 #define SI_CONTEXT_INV_ICACHE           (R600_CONTEXT_PRIVATE_FLAG << 0)
  47 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  48 #define SI_CONTEXT_INV_SMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 1)
  49 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  50 #define SI_CONTEXT_INV_VMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 2)
  51 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  52 #define SI_CONTEXT_INV_GLOBAL_L2        (R600_CONTEXT_PRIVATE_FLAG << 3)
  53 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  54  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
  55 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2  (R600_CONTEXT_PRIVATE_FLAG << 4)
  56 /* Framebuffer caches. */
  57 #define SI_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
  58 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 6)
  59 #define SI_CONTEXT_FLUSH_AND_INV_DB     (R600_CONTEXT_PRIVATE_FLAG << 7)
  60 #define SI_CONTEXT_FLUSH_AND_INV_CB     (R600_CONTEXT_PRIVATE_FLAG << 8)
  61 /* Engine synchronization. */
  62 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 9)
  63 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 10)
  64 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 11)
  65 #define SI_CONTEXT_VGT_FLUSH            (R600_CONTEXT_PRIVATE_FLAG << 12)
  66 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (R600_CONTEXT_PRIVATE_FLAG << 13)
  67
  68 #define SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER (SI_CONTEXT_FLUSH_AND_INV_CB | \
  69                                               SI_CONTEXT_FLUSH_AND_INV_CB_META | \
  70                                               SI_CONTEXT_FLUSH_AND_INV_DB | \
  71                                               SI_CONTEXT_FLUSH_AND_INV_DB_META)
  72
  73 #define SI_ENCODE_TRACE_POINT(id)       (0xcafe0000 | ((id) & 0xffff))
  74 #define SI_IS_TRACE_POINT(x)            (((x) & 0xcafe0000) == 0xcafe0000)
  75 #define SI_GET_TRACE_POINT_ID(x)        ((x) & 0xffff)
  76
  77 #define SI_MAX_BORDER_COLORS    4096
  78
  79 struct si_compute;
  80 struct hash_table;
  81 struct u_suballocator;
  82
  83 struct si_screen {
  84         struct r600_common_screen       b;
  85         unsigned                        gs_table_depth;
  86         unsigned                        tess_offchip_block_dw_size;
  87         bool                            has_distributed_tess;
  88         bool                            has_draw_indirect_multi;
  89         bool                            has_ds_bpermute;
  90
  91         /* Whether shaders are monolithic (1-part) or separate (3-part). */
  92         bool                            use_monolithic_shaders;
  93         bool                            record_llvm_ir;
  94
  95         pipe_mutex                      shader_parts_mutex;
  96         struct si_shader_part           *vs_prologs;
  97         struct si_shader_part           *vs_epilogs;
  98         struct si_shader_part           *tcs_epilogs;
  99         struct si_shader_part           *gs_prologs;
 100         struct si_shader_part           *ps_prologs;
 101         struct si_shader_part           *ps_epilogs;
 102
 103         /* Shader cache in memory.
 104          *
 105          * Design & limitations:
 106          * - The shader cache is per screen (= per process), never saved to
 107          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 108          * - It can only be used with one-variant-per-shader support, in which
 109          *   case only the main (typically middle) part of shaders is cached.
 110          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 111          *   variants of VS and TES are cached, so LS and ES aren't.
 112          * - GS and CS aren't cached, but it's certainly possible to cache
 113          *   those as well.
 114          */
 115         pipe_mutex                      shader_cache_mutex;
 116         struct hash_table               *shader_cache;
 117
 118         /* Shader compiler queue for multithreaded compilation. */
 119         struct util_queue               shader_compiler_queue;
 120         LLVMTargetMachineRef            tm[4]; /* used by the queue only */
 121 };
 122
 123 struct si_blend_color {
 124         struct r600_atom                atom;
 125         struct pipe_blend_color         state;
 126 };
 127
 128 struct si_sampler_view {
 129         struct pipe_sampler_view        base;
 130         /* [0..7] = image descriptor
 131          * [4..7] = buffer descriptor */
 132         uint32_t                        state[8];
 133         uint32_t                        fmask_state[8];
 134         const struct radeon_surf_level  *base_level_info;
 135         unsigned                        base_level;
 136         unsigned                        block_width;
 137         bool is_stencil_sampler;
 138 };
 139
 140 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
 141
 142 struct si_sampler_state {
 143 #ifdef DEBUG
 144         unsigned                        magic;
 145 #endif
 146         uint32_t                        val[4];
 147 };
 148
 149 struct si_cs_shader_state {
 150         struct si_compute               *program;
 151         struct si_compute               *emitted_program;
 152         unsigned                        offset;
 153         bool                            initialized;
 154         bool                            uses_scratch;
 155 };
 156
 157 struct si_textures_info {
 158         struct si_sampler_views         views;
 159         uint32_t                        depth_texture_mask; /* which textures are depth */
 160         uint32_t                        compressed_colortex_mask;
 161 };
 162
 163 struct si_images_info {
 164         struct pipe_image_view          views[SI_NUM_IMAGES];
 165         uint32_t                        compressed_colortex_mask;
 166         unsigned                        enabled_mask;
 167 };
 168
 169 struct si_framebuffer {
 170         struct r600_atom                atom;
 171         struct pipe_framebuffer_state   state;
 172         unsigned                        nr_samples;
 173         unsigned                        log_samples;
 174         unsigned                        compressed_cb_mask;
 175         unsigned                        colorbuf_enabled_4bit;
 176         unsigned                        spi_shader_col_format;
 177         unsigned                        spi_shader_col_format_alpha;
 178         unsigned                        spi_shader_col_format_blend;
 179         unsigned                        spi_shader_col_format_blend_alpha;
 180         unsigned                        color_is_int8; /* bitmask */
 181         unsigned                        dirty_cbufs;
 182         bool                            dirty_zsbuf;
 183         bool                            any_dst_linear;
 184 };
 185
 186 struct si_clip_state {
 187         struct r600_atom                atom;
 188         struct pipe_clip_state          state;
 189 };
 190
 191 struct si_sample_locs {
 192         struct r600_atom        atom;
 193         unsigned                nr_samples;
 194 };
 195
 196 struct si_sample_mask {
 197         struct r600_atom        atom;
 198         uint16_t                sample_mask;
 199 };
 200
 201 /* A shader state consists of the shader selector, which is a constant state
 202  * object shared by multiple contexts and shouldn't be modified, and
 203  * the current shader variant selected for this context.
 204  */
 205 struct si_shader_ctx_state {
 206         struct si_shader_selector       *cso;
 207         struct si_shader                *current;
 208 };
 209
 210 struct si_context {
 211         struct r600_common_context      b;
 212         struct blitter_context          *blitter;
 213         void                            *custom_dsa_flush;
 214         void                            *custom_blend_resolve;
 215         void                            *custom_blend_decompress;
 216         void                            *custom_blend_fastclear;
 217         void                            *custom_blend_dcc_decompress;
 218         struct si_screen                *screen;
 219
 220         struct radeon_winsys_cs         *ce_ib;
 221         struct radeon_winsys_cs         *ce_preamble_ib;
 222         bool                            ce_need_synchronization;
 223         struct u_suballocator           *ce_suballocator;
 224
 225         struct si_shader_ctx_state      fixed_func_tcs_shader;
 226         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 227         bool                            gfx_flush_in_progress;
 228         bool                            compute_is_busy;
 229
 230         /* Atoms (direct states). */
 231         union si_state_atoms            atoms;
 232         unsigned                        dirty_atoms; /* mask */
 233         /* PM4 states (precomputed immutable states) */
 234         union si_state                  queued;
 235         union si_state                  emitted;
 236
 237         /* Atom declarations. */
 238         struct si_framebuffer           framebuffer;
 239         struct si_sample_locs           msaa_sample_locs;
 240         struct r600_atom                db_render_state;
 241         struct r600_atom                msaa_config;
 242         struct si_sample_mask           sample_mask;
 243         struct r600_atom                cb_render_state;
 244         struct si_blend_color           blend_color;
 245         struct r600_atom                clip_regs;
 246         struct si_clip_state            clip_state;
 247         struct si_shader_data           shader_userdata;
 248         struct si_stencil_ref           stencil_ref;
 249         struct r600_atom                spi_map;
 250
 251         /* Precomputed states. */
 252         struct si_pm4_state             *init_config;
 253         struct si_pm4_state             *init_config_gs_rings;
 254         bool                            init_config_has_vgt_flush;
 255         struct si_pm4_state             *vgt_shader_config[4];
 256
 257         /* shaders */
 258         struct si_shader_ctx_state      ps_shader;
 259         struct si_shader_ctx_state      gs_shader;
 260         struct si_shader_ctx_state      vs_shader;
 261         struct si_shader_ctx_state      tcs_shader;
 262         struct si_shader_ctx_state      tes_shader;
 263         struct si_cs_shader_state       cs_shader_state;
 264
 265         /* shader information */
 266         struct si_vertex_element        *vertex_elements;
 267         unsigned                        sprite_coord_enable;
 268         bool                            flatshade;
 269         bool                            do_update_shaders;
 270
 271         /* shader descriptors */
 272         struct si_descriptors           vertex_buffers;
 273         struct si_descriptors           descriptors[SI_NUM_DESCS];
 274         unsigned                        descriptors_dirty;
 275         struct si_buffer_resources      rw_buffers;
 276         struct si_buffer_resources      const_buffers[SI_NUM_SHADERS];
 277         struct si_buffer_resources      shader_buffers[SI_NUM_SHADERS];
 278         struct si_textures_info         samplers[SI_NUM_SHADERS];
 279         struct si_images_info           images[SI_NUM_SHADERS];
 280
 281         /* other shader resources */
 282         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 283         struct pipe_resource            *esgs_ring;
 284         struct pipe_resource            *gsvs_ring;
 285         struct pipe_resource            *tf_ring;
 286         struct pipe_resource            *tess_offchip_ring;
 287         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 288         struct r600_resource            *border_color_buffer;
 289         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 290         unsigned                        border_color_count;
 291
 292         /* Vertex and index buffers. */
 293         bool                            vertex_buffers_dirty;
 294         struct pipe_index_buffer        index_buffer;
 295         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 296
 297         /* MSAA config state. */
 298         int                             ps_iter_samples;
 299         bool                            smoothing_enabled;
 300
 301         /* DB render state. */
 302         bool                    dbcb_depth_copy_enabled;
 303         bool                    dbcb_stencil_copy_enabled;
 304         unsigned                dbcb_copy_sample;
 305         bool                    db_flush_depth_inplace;
 306         bool                    db_flush_stencil_inplace;
 307         bool                    db_depth_clear;
 308         bool                    db_depth_disable_expclear;
 309         bool                    db_stencil_clear;
 310         bool                    db_stencil_disable_expclear;
 311         unsigned                ps_db_shader_control;
 312         bool                    occlusion_queries_disabled;
 313
 314         /* Emitted draw state. */
 315         int                     last_index_size;
 316         int                     last_base_vertex;
 317         int                     last_start_instance;
 318         int                     last_drawid;
 319         int                     last_sh_base_reg;
 320         int                     last_primitive_restart_en;
 321         int                     last_restart_index;
 322         int                     last_gs_out_prim;
 323         int                     last_prim;
 324         int                     last_multi_vgt_param;
 325         int                     last_rast_prim;
 326         unsigned                last_sc_line_stipple;
 327         int                     last_vtx_reuse_depth;
 328         int                     current_rast_prim; /* primitive type after TES, GS */
 329         bool                    gs_tri_strip_adj_fix;
 330
 331         /* Scratch buffer */
 332         struct r600_resource    *scratch_buffer;
 333         bool                    emit_scratch_reloc;
 334         unsigned                scratch_waves;
 335         unsigned                spi_tmpring_size;
 336
 337         struct r600_resource    *compute_scratch_buffer;
 338
 339         /* Emitted derived tessellation state. */
 340         struct si_shader        *last_ls; /* local shader (VS) */
 341         struct si_shader_selector *last_tcs;
 342         int                     last_num_tcs_input_cp;
 343         int                     last_tes_sh_base;
 344         unsigned                last_num_patches;
 345
 346         /* Debug state. */
 347         bool                    is_debug;
 348         struct radeon_saved_cs  last_gfx;
 349         struct r600_resource    *last_trace_buf;
 350         struct r600_resource    *trace_buf;
 351         unsigned                trace_id;
 352         uint64_t                dmesg_timestamp;
 353         unsigned                apitrace_call_number;
 354
 355         /* Other state */
 356         bool need_check_render_feedback;
 357 };
 358
 359 /* cik_sdma.c */
 360 void cik_init_sdma_functions(struct si_context *sctx);
 361
 362 /* si_blit.c */
 363 void si_init_blit_functions(struct si_context *sctx);
 364 void si_decompress_graphics_textures(struct si_context *sctx);
 365 void si_decompress_compute_textures(struct si_context *sctx);
 366 void si_resource_copy_region(struct pipe_context *ctx,
 367                              struct pipe_resource *dst,
 368                              unsigned dst_level,
 369                              unsigned dstx, unsigned dsty, unsigned dstz,
 370                              struct pipe_resource *src,
 371                              unsigned src_level,
 372                              const struct pipe_box *src_box);
 373
 374 /* si_cp_dma.c */
 375 #define SI_CPDMA_SKIP_CHECK_CS_SPACE    (1 << 0) /* don't call need_cs_space */
 376 #define SI_CPDMA_SKIP_SYNC_AFTER        (1 << 1) /* don't wait for DMA after the copy */
 377 #define SI_CPDMA_SKIP_SYNC_BEFORE       (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
 378 #define SI_CPDMA_SKIP_GFX_SYNC          (1 << 3) /* don't flush caches and don't wait for PS/CS */
 379
 380 void si_copy_buffer(struct si_context *sctx,
 381                     struct pipe_resource *dst, struct pipe_resource *src,
 382                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 383                     unsigned user_flags);
 384 void si_init_cp_dma_functions(struct si_context *sctx);
 385
 386 /* si_debug.c */
 387 void si_init_debug_functions(struct si_context *sctx);
 388 void si_check_vm_faults(struct r600_common_context *ctx,
 389                         struct radeon_saved_cs *saved, enum ring_type ring);
 390 bool si_replace_shader(unsigned num, struct radeon_shader_binary *binary);
 391
 392 /* si_dma.c */
 393 void si_init_dma_functions(struct si_context *sctx);
 394
 395 /* si_hw_context.c */
 396 void si_context_gfx_flush(void *context, unsigned flags,
 397                           struct pipe_fence_handle **fence);
 398 void si_begin_new_cs(struct si_context *ctx);
 399 void si_need_cs_space(struct si_context *ctx);
 400
 401 /* si_compute.c */
 402 void si_init_compute_functions(struct si_context *sctx);
 403
 404 /* si_perfcounters.c */
 405 void si_init_perfcounters(struct si_screen *screen);
 406
 407 /* si_uvd.c */
 408 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 409                                                const struct pipe_video_codec *templ);
 410
 411 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 412                                                  const struct pipe_video_buffer *tmpl);
 413
 414 /*
 415  * common helpers
 416  */
 417
 418 static inline void
 419 si_invalidate_draw_sh_constants(struct si_context *sctx)
 420 {
 421         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 422 }
 423
 424 static inline void
 425 si_set_atom_dirty(struct si_context *sctx,
 426                   struct r600_atom *atom, bool dirty)
 427 {
 428         unsigned bit = 1 << (atom->id - 1);
 429
 430         if (dirty)
 431                 sctx->dirty_atoms |= bit;
 432         else
 433                 sctx->dirty_atoms &= ~bit;
 434 }
 435
 436 static inline bool
 437 si_is_atom_dirty(struct si_context *sctx,
 438                   struct r600_atom *atom)
 439 {
 440         unsigned bit = 1 << (atom->id - 1);
 441
 442         return sctx->dirty_atoms & bit;
 443 }
 444
 445 static inline void
 446 si_mark_atom_dirty(struct si_context *sctx,
 447                    struct r600_atom *atom)
 448 {
 449         si_set_atom_dirty(sctx, atom, true);
 450 }
 451
 452 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 453 {
 454         if (sctx->gs_shader.cso)
 455                 return &sctx->gs_shader.cso->info;
 456         else if (sctx->tes_shader.cso)
 457                 return &sctx->tes_shader.cso->info;
 458         else if (sctx->vs_shader.cso)
 459                 return &sctx->vs_shader.cso->info;
 460         else
 461                 return NULL;
 462 }
 463
 464 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 465 {
 466         if (sctx->gs_shader.current)
 467                 return sctx->gs_shader.cso->gs_copy_shader;
 468         else if (sctx->tes_shader.current)
 469                 return sctx->tes_shader.current;
 470         else
 471                 return sctx->vs_shader.current;
 472 }
 473
 474 static inline bool si_vs_exports_prim_id(struct si_shader *shader)
 475 {
 476         if (shader->selector->type == PIPE_SHADER_VERTEX)
 477                 return shader->key.part.vs.epilog.export_prim_id;
 478         else if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
 479                 return shader->key.part.tes.epilog.export_prim_id;
 480         else
 481                 return false;
 482 }
 483
 484 #endif