2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "si_shader.h"
28 #include "util/u_dynarray.h"
29 #include "util/u_idalloc.h"
31 #ifdef PIPE_ARCH_BIG_ENDIAN
32 #define SI_BIG_ENDIAN 1
34 #define SI_BIG_ENDIAN 0
37 /* The base vertex and primitive restart can be any number, but we must pick
38 * one which will mean "unknown" for the purpose of state tracking and
39 * the number shouldn't be a commonly-used one. */
40 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
41 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
42 #define SI_NUM_SMOOTH_AA_SAMPLES 8
43 #define SI_GS_PER_ES 128
44 /* Alignment for optimal CP DMA performance. */
45 #define SI_CPDMA_ALIGNMENT 32
47 /* Instruction cache. */
48 #define SI_CONTEXT_INV_ICACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
49 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
50 #define SI_CONTEXT_INV_SMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 1)
51 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
52 #define SI_CONTEXT_INV_VMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 2)
53 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
54 #define SI_CONTEXT_INV_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 3)
55 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
56 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
57 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 4)
58 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
59 * a CB or DB flush. */
60 #define SI_CONTEXT_INV_L2_METADATA (R600_CONTEXT_PRIVATE_FLAG << 5)
61 /* Framebuffer caches. */
62 #define SI_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
63 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 7)
64 #define SI_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 8)
65 /* Engine synchronization. */
66 #define SI_CONTEXT_VS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 9)
67 #define SI_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 10)
68 #define SI_CONTEXT_CS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 11)
69 #define SI_CONTEXT_VGT_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 12)
70 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (R600_CONTEXT_PRIVATE_FLAG << 13)
72 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
73 #define SI_PREFETCH_LS (1 << 1)
74 #define SI_PREFETCH_HS (1 << 2)
75 #define SI_PREFETCH_ES (1 << 3)
76 #define SI_PREFETCH_GS (1 << 4)
77 #define SI_PREFETCH_VS (1 << 5)
78 #define SI_PREFETCH_PS (1 << 6)
80 #define SI_MAX_BORDER_COLORS 4096
81 #define SI_MAX_VIEWPORTS 16
86 struct u_suballocator
;
89 struct r600_common_screen b
;
90 unsigned gs_table_depth
;
91 unsigned tess_offchip_block_dw_size
;
93 bool has_distributed_tess
;
94 bool has_draw_indirect_multi
;
95 bool has_out_of_order_rast
;
96 bool assume_no_z_fights
;
97 bool commutative_blend_add
;
98 bool clear_db_cache_before_clear
;
99 bool has_msaa_sample_loc_bug
;
100 bool has_ls_vgpr_init_bug
;
103 bool llvm_has_working_vgpr_indexing
;
105 /* Whether shaders are monolithic (1-part) or separate (3-part). */
106 bool use_monolithic_shaders
;
109 mtx_t shader_parts_mutex
;
110 struct si_shader_part
*vs_prologs
;
111 struct si_shader_part
*tcs_epilogs
;
112 struct si_shader_part
*gs_prologs
;
113 struct si_shader_part
*ps_prologs
;
114 struct si_shader_part
*ps_epilogs
;
116 /* Shader cache in memory.
118 * Design & limitations:
119 * - The shader cache is per screen (= per process), never saved to
120 * disk, and skips redundant shader compilations from TGSI to bytecode.
121 * - It can only be used with one-variant-per-shader support, in which
122 * case only the main (typically middle) part of shaders is cached.
123 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
124 * variants of VS and TES are cached, so LS and ES aren't.
125 * - GS and CS aren't cached, but it's certainly possible to cache
128 mtx_t shader_cache_mutex
;
129 struct hash_table
*shader_cache
;
131 /* Shader compiler queue for multithreaded compilation. */
132 struct util_queue shader_compiler_queue
;
133 /* Use at most 3 normal compiler threads on quadcore and better.
134 * Hyperthreaded CPUs report the number of threads, but we want
135 * the number of cores. */
136 LLVMTargetMachineRef tm
[3]; /* used by the queue only */
138 struct util_queue shader_compiler_queue_low_priority
;
139 /* Use at most 2 low priority threads on quadcore and better.
140 * We want to minimize the impact on multithreaded Mesa. */
141 LLVMTargetMachineRef tm_low_priority
[2]; /* at most 2 threads */
144 struct si_blend_color
{
145 struct r600_atom atom
;
146 struct pipe_blend_color state
;
150 struct si_sampler_view
{
151 struct pipe_sampler_view base
;
152 /* [0..7] = image descriptor
153 * [4..7] = buffer descriptor */
155 uint32_t fmask_state
[8];
156 const struct legacy_surf_level
*base_level_info
;
159 bool is_stencil_sampler
;
161 bool dcc_incompatible
;
164 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
166 struct si_sampler_state
{
171 uint32_t integer_val
[4];
172 uint32_t upgraded_depth_val
[4];
175 struct si_cs_shader_state
{
176 struct si_compute
*program
;
177 struct si_compute
*emitted_program
;
184 struct pipe_sampler_view
*views
[SI_NUM_SAMPLERS
];
185 struct si_sampler_state
*sampler_states
[SI_NUM_SAMPLERS
];
187 /* The i-th bit is set if that element is enabled (non-NULL resource). */
188 unsigned enabled_mask
;
189 uint32_t needs_depth_decompress_mask
;
190 uint32_t needs_color_decompress_mask
;
194 struct pipe_image_view views
[SI_NUM_IMAGES
];
195 uint32_t needs_color_decompress_mask
;
196 unsigned enabled_mask
;
199 struct si_framebuffer
{
200 struct r600_atom atom
;
201 struct pipe_framebuffer_state state
;
202 unsigned colorbuf_enabled_4bit
;
203 unsigned spi_shader_col_format
;
204 unsigned spi_shader_col_format_alpha
;
205 unsigned spi_shader_col_format_blend
;
206 unsigned spi_shader_col_format_blend_alpha
;
207 ubyte nr_samples
:5; /* at most 16xAA */
208 ubyte log_samples
:3; /* at most 4 = 16xAA */
209 ubyte compressed_cb_mask
;
211 ubyte color_is_int10
;
215 bool CB_has_shader_readable_metadata
;
216 bool DB_has_shader_readable_metadata
;
219 struct si_signed_scissor
{
227 struct r600_atom atom
;
229 struct pipe_scissor_state states
[SI_MAX_VIEWPORTS
];
232 struct si_viewports
{
233 struct r600_atom atom
;
235 unsigned depth_range_dirty_mask
;
236 struct pipe_viewport_state states
[SI_MAX_VIEWPORTS
];
237 struct si_signed_scissor as_scissor
[SI_MAX_VIEWPORTS
];
240 struct si_clip_state
{
241 struct r600_atom atom
;
242 struct pipe_clip_state state
;
246 struct si_sample_locs
{
247 struct r600_atom atom
;
251 struct si_sample_mask
{
252 struct r600_atom atom
;
253 uint16_t sample_mask
;
256 struct si_streamout_target
{
257 struct pipe_stream_output_target b
;
259 /* The buffer where BUFFER_FILLED_SIZE is stored. */
260 struct r600_resource
*buf_filled_size
;
261 unsigned buf_filled_size_offset
;
262 bool buf_filled_size_valid
;
264 unsigned stride_in_dw
;
267 struct si_streamout
{
268 struct r600_atom begin_atom
;
271 unsigned enabled_mask
;
272 unsigned num_targets
;
273 struct si_streamout_target
*targets
[PIPE_MAX_SO_BUFFERS
];
275 unsigned append_bitmask
;
278 /* External state which comes from the vertex shader,
279 * it must be set explicitly when binding a shader. */
280 uint16_t *stride_in_dw
;
281 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
283 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
284 unsigned hw_enabled_mask
;
286 /* The state of VGT_STRMOUT_(CONFIG|EN). */
287 struct r600_atom enable_atom
;
288 bool streamout_enabled
;
289 bool prims_gen_query_enabled
;
290 int num_prims_gen_queries
;
293 /* A shader state consists of the shader selector, which is a constant state
294 * object shared by multiple contexts and shouldn't be modified, and
295 * the current shader variant selected for this context.
297 struct si_shader_ctx_state
{
298 struct si_shader_selector
*cso
;
299 struct si_shader
*current
;
302 #define SI_NUM_VGT_PARAM_KEY_BITS 12
303 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
305 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
306 * Some fields are set by state-change calls, most are set by draw_vbo.
308 union si_vgt_param_key
{
311 unsigned uses_instancing
:1;
312 unsigned multi_instances_smaller_than_primgroup
:1;
313 unsigned primitive_restart
:1;
314 unsigned count_from_stream_output
:1;
315 unsigned line_stipple_enabled
:1;
316 unsigned uses_tess
:1;
317 unsigned tess_uses_prim_id
:1;
319 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
324 struct si_texture_handle
328 struct pipe_sampler_view
*view
;
329 struct si_sampler_state sstate
;
332 struct si_image_handle
336 struct pipe_image_view view
;
340 struct pipe_reference reference
;
341 struct si_context
*ctx
;
342 struct radeon_saved_cs gfx
;
343 struct r600_resource
*trace_buf
;
346 unsigned gfx_last_dw
;
351 struct r600_common_context b
;
352 struct blitter_context
*blitter
;
353 void *custom_dsa_flush
;
354 void *custom_blend_resolve
;
355 void *custom_blend_fmask_decompress
;
356 void *custom_blend_eliminate_fastclear
;
357 void *custom_blend_dcc_decompress
;
359 void *vs_blit_pos_layered
;
361 void *vs_blit_color_layered
;
362 void *vs_blit_texcoord
;
363 struct si_screen
*screen
;
364 struct pipe_debug_callback debug
;
365 LLVMTargetMachineRef tm
; /* only non-threaded compilation */
366 struct si_shader_ctx_state fixed_func_tcs_shader
;
367 struct r600_resource
*wait_mem_scratch
;
368 unsigned wait_mem_number
;
369 uint16_t prefetch_L2_mask
;
371 bool gfx_flush_in_progress
:1;
372 bool compute_is_busy
:1;
374 /* Atoms (direct states). */
375 union si_state_atoms atoms
;
376 unsigned dirty_atoms
; /* mask */
377 /* PM4 states (precomputed immutable states) */
378 unsigned dirty_states
;
379 union si_state queued
;
380 union si_state emitted
;
382 /* Atom declarations. */
383 struct si_framebuffer framebuffer
;
384 struct si_sample_locs msaa_sample_locs
;
385 struct r600_atom db_render_state
;
386 struct r600_atom dpbb_state
;
387 struct r600_atom msaa_config
;
388 struct si_sample_mask sample_mask
;
389 struct r600_atom cb_render_state
;
390 unsigned last_cb_target_mask
;
391 struct si_blend_color blend_color
;
392 struct r600_atom clip_regs
;
393 struct si_clip_state clip_state
;
394 struct si_shader_data shader_pointers
;
395 struct si_stencil_ref stencil_ref
;
396 struct r600_atom spi_map
;
397 struct si_scissors scissors
;
398 struct si_streamout streamout
;
399 struct si_viewports viewports
;
401 /* Precomputed states. */
402 struct si_pm4_state
*init_config
;
403 struct si_pm4_state
*init_config_gs_rings
;
404 bool init_config_has_vgt_flush
;
405 struct si_pm4_state
*vgt_shader_config
[4];
408 struct si_shader_ctx_state ps_shader
;
409 struct si_shader_ctx_state gs_shader
;
410 struct si_shader_ctx_state vs_shader
;
411 struct si_shader_ctx_state tcs_shader
;
412 struct si_shader_ctx_state tes_shader
;
413 struct si_cs_shader_state cs_shader_state
;
415 /* shader information */
416 struct si_vertex_elements
*vertex_elements
;
417 unsigned sprite_coord_enable
;
419 bool do_update_shaders
;
421 /* shader descriptors */
422 struct si_descriptors vertex_buffers
;
423 struct si_descriptors descriptors
[SI_NUM_DESCS
];
424 unsigned descriptors_dirty
;
425 unsigned shader_pointers_dirty
;
426 unsigned shader_needs_decompress_mask
;
427 struct si_buffer_resources rw_buffers
;
428 struct si_buffer_resources const_and_shader_buffers
[SI_NUM_SHADERS
];
429 struct si_samplers samplers
[SI_NUM_SHADERS
];
430 struct si_images images
[SI_NUM_SHADERS
];
432 /* other shader resources */
433 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on CIK */
434 struct pipe_resource
*esgs_ring
;
435 struct pipe_resource
*gsvs_ring
;
436 struct pipe_resource
*tf_ring
;
437 struct pipe_resource
*tess_offchip_ring
;
438 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
439 struct r600_resource
*border_color_buffer
;
440 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
441 unsigned border_color_count
;
442 unsigned num_vs_blit_sgprs
;
443 uint32_t vs_blit_sh_data
[SI_VS_BLIT_SGPRS_POS_TEXCOORD
];
445 /* Vertex and index buffers. */
446 bool vertex_buffers_dirty
;
447 bool vertex_buffer_pointer_dirty
;
448 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
450 /* MSAA config state. */
452 bool smoothing_enabled
;
454 /* DB render state. */
455 unsigned ps_db_shader_control
;
456 unsigned dbcb_copy_sample
;
457 bool dbcb_depth_copy_enabled
:1;
458 bool dbcb_stencil_copy_enabled
:1;
459 bool db_flush_depth_inplace
:1;
460 bool db_flush_stencil_inplace
:1;
461 bool db_depth_clear
:1;
462 bool db_depth_disable_expclear
:1;
463 bool db_stencil_clear
:1;
464 bool db_stencil_disable_expclear
:1;
465 bool occlusion_queries_disabled
:1;
466 bool generate_mipmap_for_depth
:1;
468 /* Emitted draw state. */
469 bool gs_tri_strip_adj_fix
:1;
472 int last_base_vertex
;
473 int last_start_instance
;
475 int last_sh_base_reg
;
476 int last_primitive_restart_en
;
477 int last_restart_index
;
478 int last_gs_out_prim
;
480 int last_multi_vgt_param
;
482 unsigned last_sc_line_stipple
;
483 unsigned current_vs_state
;
484 unsigned last_vs_state
;
485 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
488 struct r600_atom scratch_state
;
489 struct r600_resource
*scratch_buffer
;
490 unsigned scratch_waves
;
491 unsigned spi_tmpring_size
;
493 struct r600_resource
*compute_scratch_buffer
;
495 /* Emitted derived tessellation state. */
496 /* Local shader (VS), or HS if LS-HS are merged. */
497 struct si_shader
*last_ls
;
498 struct si_shader_selector
*last_tcs
;
499 int last_num_tcs_input_cp
;
500 int last_tes_sh_base
;
501 bool last_tess_uses_primid
;
502 unsigned last_num_patches
;
506 struct si_saved_cs
*current_saved_cs
;
507 uint64_t dmesg_timestamp
;
508 unsigned apitrace_call_number
;
511 bool need_check_render_feedback
;
512 bool decompression_enabled
;
514 bool vs_writes_viewport_index
;
515 bool vs_disables_clipping_viewport
;
517 /* Precomputed IA_MULTI_VGT_PARAM */
518 union si_vgt_param_key ia_multi_vgt_param_key
;
519 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
521 /* Bindless descriptors. */
522 struct si_descriptors bindless_descriptors
;
523 struct util_idalloc bindless_used_slots
;
524 unsigned num_bindless_descriptors
;
525 bool bindless_descriptors_dirty
;
526 bool graphics_bindless_pointer_dirty
;
527 bool compute_bindless_pointer_dirty
;
529 /* Allocated bindless handles */
530 struct hash_table
*tex_handles
;
531 struct hash_table
*img_handles
;
533 /* Resident bindless handles */
534 struct util_dynarray resident_tex_handles
;
535 struct util_dynarray resident_img_handles
;
537 /* Resident bindless handles which need decompression */
538 struct util_dynarray resident_tex_needs_color_decompress
;
539 struct util_dynarray resident_img_needs_color_decompress
;
540 struct util_dynarray resident_tex_needs_depth_decompress
;
543 bool uses_bindless_samplers
;
544 bool uses_bindless_images
;
546 /* MSAA sample locations.
547 * The first index is the sample index.
548 * The second index is the coordinate: X, Y. */
549 float sample_locations_1x
[1][2];
550 float sample_locations_2x
[2][2];
551 float sample_locations_4x
[4][2];
552 float sample_locations_8x
[8][2];
553 float sample_locations_16x
[16][2];
557 void cik_init_sdma_functions(struct si_context
*sctx
);
560 void si_init_blit_functions(struct si_context
*sctx
);
561 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
);
562 void si_resource_copy_region(struct pipe_context
*ctx
,
563 struct pipe_resource
*dst
,
565 unsigned dstx
, unsigned dsty
, unsigned dstz
,
566 struct pipe_resource
*src
,
568 const struct pipe_box
*src_box
);
571 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
572 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
573 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
574 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
575 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
576 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
577 SI_CPDMA_SKIP_SYNC_AFTER | \
578 SI_CPDMA_SKIP_SYNC_BEFORE | \
579 SI_CPDMA_SKIP_GFX_SYNC | \
580 SI_CPDMA_SKIP_BO_LIST_UPDATE)
582 void si_copy_buffer(struct si_context
*sctx
,
583 struct pipe_resource
*dst
, struct pipe_resource
*src
,
584 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
585 unsigned user_flags
);
586 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
587 uint64_t offset
, unsigned size
);
588 void cik_emit_prefetch_L2(struct si_context
*sctx
);
589 void si_init_cp_dma_functions(struct si_context
*sctx
);
592 void si_auto_log_cs(void *data
, struct u_log_context
*log
);
593 void si_log_hw_flush(struct si_context
*sctx
);
594 void si_log_draw_state(struct si_context
*sctx
, struct u_log_context
*log
);
595 void si_log_compute_state(struct si_context
*sctx
, struct u_log_context
*log
);
596 void si_init_debug_functions(struct si_context
*sctx
);
597 void si_check_vm_faults(struct r600_common_context
*ctx
,
598 struct radeon_saved_cs
*saved
, enum ring_type ring
);
599 bool si_replace_shader(unsigned num
, struct ac_shader_binary
*binary
);
602 void si_init_dma_functions(struct si_context
*sctx
);
605 void si_init_fence_functions(struct si_context
*ctx
);
606 void si_init_screen_fence_functions(struct si_screen
*screen
);
607 struct pipe_fence_handle
*si_create_fence(struct pipe_context
*ctx
,
608 struct tc_unflushed_batch_token
*tc_token
);
610 /* si_hw_context.c */
611 void si_destroy_saved_cs(struct si_saved_cs
*scs
);
612 void si_context_gfx_flush(void *context
, unsigned flags
,
613 struct pipe_fence_handle
**fence
);
614 void si_begin_new_cs(struct si_context
*ctx
);
615 void si_need_cs_space(struct si_context
*ctx
);
618 void si_init_compute_functions(struct si_context
*sctx
);
620 /* si_perfcounters.c */
621 void si_init_perfcounters(struct si_screen
*screen
);
624 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
625 const struct pipe_video_codec
*templ
);
627 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
628 const struct pipe_video_buffer
*tmpl
);
631 void si_update_vs_viewport_state(struct si_context
*ctx
);
632 void si_init_viewport_functions(struct si_context
*ctx
);
640 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
642 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
646 si_set_atom_dirty(struct si_context
*sctx
,
647 struct r600_atom
*atom
, bool dirty
)
649 unsigned bit
= 1 << atom
->id
;
652 sctx
->dirty_atoms
|= bit
;
654 sctx
->dirty_atoms
&= ~bit
;
658 si_is_atom_dirty(struct si_context
*sctx
,
659 struct r600_atom
*atom
)
661 unsigned bit
= 1 << atom
->id
;
663 return sctx
->dirty_atoms
& bit
;
667 si_mark_atom_dirty(struct si_context
*sctx
,
668 struct r600_atom
*atom
)
670 si_set_atom_dirty(sctx
, atom
, true);
673 static inline struct si_shader_ctx_state
*si_get_vs(struct si_context
*sctx
)
675 if (sctx
->gs_shader
.cso
)
676 return &sctx
->gs_shader
;
677 if (sctx
->tes_shader
.cso
)
678 return &sctx
->tes_shader
;
680 return &sctx
->vs_shader
;
683 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
685 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
687 return vs
->cso
? &vs
->cso
->info
: NULL
;
690 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
692 if (sctx
->gs_shader
.cso
)
693 return sctx
->gs_shader
.cso
->gs_copy_shader
;
695 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
696 return vs
->current
? vs
->current
: NULL
;
699 static inline bool si_get_strmout_en(struct si_context
*sctx
)
701 return sctx
->streamout
.streamout_enabled
||
702 sctx
->streamout
.prims_gen_query_enabled
;
705 static inline unsigned
706 si_optimal_tcc_alignment(struct si_context
*sctx
, unsigned upload_size
)
708 unsigned alignment
, tcc_cache_line_size
;
710 /* If the upload size is less than the cache line size (e.g. 16, 32),
711 * the whole thing will fit into a cache line if we align it to its size.
712 * The idea is that multiple small uploads can share a cache line.
713 * If the upload size is greater, align it to the cache line size.
715 alignment
= util_next_power_of_two(upload_size
);
716 tcc_cache_line_size
= sctx
->screen
->b
.info
.tcc_cache_line_size
;
717 return MIN2(alignment
, tcc_cache_line_size
);
721 si_saved_cs_reference(struct si_saved_cs
**dst
, struct si_saved_cs
*src
)
723 if (pipe_reference(&(*dst
)->reference
, &src
->reference
))
724 si_destroy_saved_cs(*dst
);
730 si_make_CB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
731 bool shaders_read_metadata
)
733 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
|
734 SI_CONTEXT_INV_VMEM_L1
;
736 if (sctx
->b
.chip_class
>= GFX9
) {
737 /* Single-sample color is coherent with shaders on GFX9, but
738 * L2 metadata must be flushed if shaders read metadata.
741 if (num_samples
>= 2)
742 sctx
->b
.flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
743 else if (shaders_read_metadata
)
744 sctx
->b
.flags
|= SI_CONTEXT_INV_L2_METADATA
;
747 sctx
->b
.flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
752 si_make_DB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
753 bool include_stencil
, bool shaders_read_metadata
)
755 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_DB
|
756 SI_CONTEXT_INV_VMEM_L1
;
758 if (sctx
->b
.chip_class
>= GFX9
) {
759 /* Single-sample depth (not stencil) is coherent with shaders
760 * on GFX9, but L2 metadata must be flushed if shaders read
763 if (num_samples
>= 2 || include_stencil
)
764 sctx
->b
.flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
765 else if (shaders_read_metadata
)
766 sctx
->b
.flags
|= SI_CONTEXT_INV_L2_METADATA
;
769 sctx
->b
.flags
|= SI_CONTEXT_INV_GLOBAL_L2
;