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[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
34
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
37 #else
38 #define SI_BIG_ENDIAN 0
39 #endif
40
41 #define ATI_VENDOR_ID 0x1002
42
43 #define SI_NOT_QUERY 0xffffffff
44
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_NUM_SMOOTH_AA_SAMPLES 8
51 #define SI_GS_PER_ES 128
52 /* Alignment for optimal CP DMA performance. */
53 #define SI_CPDMA_ALIGNMENT 32
54
55 /* Pipeline & streamout query controls. */
56 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
57 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
58 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
59 /* Instruction cache. */
60 #define SI_CONTEXT_INV_ICACHE (1 << 3)
61 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
62 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
63 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
64 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
65 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
66 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
67 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
68 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
69 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
70 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
71 * a CB or DB flush. */
72 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
73 /* Framebuffer caches. */
74 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
75 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
76 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
77 /* Engine synchronization. */
78 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
79 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
80 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
81 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
82 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
83
84 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
85 #define SI_PREFETCH_LS (1 << 1)
86 #define SI_PREFETCH_HS (1 << 2)
87 #define SI_PREFETCH_ES (1 << 3)
88 #define SI_PREFETCH_GS (1 << 4)
89 #define SI_PREFETCH_VS (1 << 5)
90 #define SI_PREFETCH_PS (1 << 6)
91
92 #define SI_MAX_BORDER_COLORS 4096
93 #define SI_MAX_VIEWPORTS 16
94 #define SIX_BITS 0x3F
95 #define SI_MAP_BUFFER_ALIGNMENT 64
96 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
97
98 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
99 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
100 #define SI_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
101 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
102 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
103 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
104 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
105
106 /* Debug flags. */
107 enum {
108 /* Shader logging options: */
109 DBG_VS = PIPE_SHADER_VERTEX,
110 DBG_PS = PIPE_SHADER_FRAGMENT,
111 DBG_GS = PIPE_SHADER_GEOMETRY,
112 DBG_TCS = PIPE_SHADER_TESS_CTRL,
113 DBG_TES = PIPE_SHADER_TESS_EVAL,
114 DBG_CS = PIPE_SHADER_COMPUTE,
115 DBG_NO_IR,
116 DBG_NO_TGSI,
117 DBG_NO_ASM,
118 DBG_PREOPT_IR,
119
120 /* Shader compiler options the shader cache should be aware of: */
121 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
122 DBG_UNSAFE_MATH,
123 DBG_SI_SCHED,
124 DBG_GISEL,
125
126 /* Shader compiler options (with no effect on the shader cache): */
127 DBG_CHECK_IR,
128 DBG_NIR,
129 DBG_MONOLITHIC_SHADERS,
130 DBG_NO_OPT_VARIANT,
131
132 /* Information logging options: */
133 DBG_INFO,
134 DBG_TEX,
135 DBG_COMPUTE,
136 DBG_VM,
137
138 /* Driver options: */
139 DBG_FORCE_DMA,
140 DBG_NO_ASYNC_DMA,
141 DBG_NO_WC,
142 DBG_CHECK_VM,
143 DBG_RESERVE_VMID,
144 DBG_ZERO_VRAM,
145
146 /* 3D engine options: */
147 DBG_SWITCH_ON_EOP,
148 DBG_NO_OUT_OF_ORDER,
149 DBG_NO_DPBB,
150 DBG_NO_DFSM,
151 DBG_DPBB,
152 DBG_DFSM,
153 DBG_NO_HYPERZ,
154 DBG_NO_RB_PLUS,
155 DBG_NO_2D_TILING,
156 DBG_NO_TILING,
157 DBG_NO_DCC,
158 DBG_NO_DCC_CLEAR,
159 DBG_NO_DCC_FB,
160 DBG_NO_DCC_MSAA,
161 DBG_NO_FMASK,
162
163 /* Tests: */
164 DBG_TEST_DMA,
165 DBG_TEST_VMFAULT_CP,
166 DBG_TEST_VMFAULT_SDMA,
167 DBG_TEST_VMFAULT_SHADER,
168 DBG_TEST_DMA_PERF,
169 };
170
171 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
172 #define DBG(name) (1ull << DBG_##name)
173
174 struct si_compute;
175 struct hash_table;
176 struct u_suballocator;
177
178 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
179 * at the moment.
180 */
181 struct r600_resource {
182 struct threaded_resource b;
183
184 /* Winsys objects. */
185 struct pb_buffer *buf;
186 uint64_t gpu_address;
187 /* Memory usage if the buffer placement is optimal. */
188 uint64_t vram_usage;
189 uint64_t gart_usage;
190
191 /* Resource properties. */
192 uint64_t bo_size;
193 unsigned bo_alignment;
194 enum radeon_bo_domain domains;
195 enum radeon_bo_flag flags;
196 unsigned bind_history;
197 int max_forced_staging_uploads;
198
199 /* The buffer range which is initialized (with a write transfer,
200 * streamout, DMA, or as a random access target). The rest of
201 * the buffer is considered invalid and can be mapped unsynchronized.
202 *
203 * This allows unsychronized mapping of a buffer range which hasn't
204 * been used yet. It's for applications which forget to use
205 * the unsynchronized map flag and expect the driver to figure it out.
206 */
207 struct util_range valid_buffer_range;
208
209 /* For buffers only. This indicates that a write operation has been
210 * performed by TC L2, but the cache hasn't been flushed.
211 * Any hw block which doesn't use or bypasses TC L2 should check this
212 * flag and flush the cache before using the buffer.
213 *
214 * For example, TC L2 must be flushed if a buffer which has been
215 * modified by a shader store instruction is about to be used as
216 * an index buffer. The reason is that VGT DMA index fetching doesn't
217 * use TC L2.
218 */
219 bool TC_L2_dirty;
220
221 /* Whether this resource is referenced by bindless handles. */
222 bool texture_handle_allocated;
223 bool image_handle_allocated;
224
225 /* Whether the resource has been exported via resource_get_handle. */
226 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
227 };
228
229 struct si_transfer {
230 struct threaded_transfer b;
231 struct r600_resource *staging;
232 unsigned offset;
233 };
234
235 struct si_texture {
236 struct r600_resource buffer;
237
238 struct radeon_surf surface;
239 uint64_t size;
240 struct si_texture *flushed_depth_texture;
241
242 /* Colorbuffer compression and fast clear. */
243 uint64_t fmask_offset;
244 uint64_t cmask_offset;
245 uint64_t cmask_base_address_reg;
246 struct r600_resource *cmask_buffer;
247 uint64_t dcc_offset; /* 0 = disabled */
248 unsigned cb_color_info; /* fast clear enable bit */
249 unsigned color_clear_value[2];
250 unsigned last_msaa_resolve_target_micro_mode;
251 unsigned num_level0_transfers;
252
253 /* Depth buffer compression and fast clear. */
254 uint64_t htile_offset;
255 float depth_clear_value;
256 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
257 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
258 enum pipe_format db_render_format:16;
259 uint8_t stencil_clear_value;
260 bool tc_compatible_htile:1;
261 bool depth_cleared:1; /* if it was cleared at least once */
262 bool stencil_cleared:1; /* if it was cleared at least once */
263 bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
264 bool is_depth:1;
265 bool db_compatible:1;
266 bool can_sample_z:1;
267 bool can_sample_s:1;
268
269 /* We need to track DCC dirtiness, because st/dri usually calls
270 * flush_resource twice per frame (not a bug) and we don't wanna
271 * decompress DCC twice. Also, the dirty tracking must be done even
272 * if DCC isn't used, because it's required by the DCC usage analysis
273 * for a possible future enablement.
274 */
275 bool separate_dcc_dirty:1;
276 /* Statistics gathering for the DCC enablement heuristic. */
277 bool dcc_gather_statistics:1;
278 /* Counter that should be non-zero if the texture is bound to a
279 * framebuffer.
280 */
281 unsigned framebuffers_bound;
282 /* Whether the texture is a displayable back buffer and needs DCC
283 * decompression, which is expensive. Therefore, it's enabled only
284 * if statistics suggest that it will pay off and it's allocated
285 * separately. It can't be bound as a sampler by apps. Limited to
286 * target == 2D and last_level == 0. If enabled, dcc_offset contains
287 * the absolute GPUVM address, not the relative one.
288 */
289 struct r600_resource *dcc_separate_buffer;
290 /* When DCC is temporarily disabled, the separate buffer is here. */
291 struct r600_resource *last_dcc_separate_buffer;
292 /* Estimate of how much this color buffer is written to in units of
293 * full-screen draws: ps_invocations / (width * height)
294 * Shader kills, late Z, and blending with trivial discards make it
295 * inaccurate (we need to count CB updates, not PS invocations).
296 */
297 unsigned ps_draw_ratio;
298 /* The number of clears since the last DCC usage analysis. */
299 unsigned num_slow_clears;
300 };
301
302 struct si_surface {
303 struct pipe_surface base;
304
305 /* These can vary with block-compressed textures. */
306 uint16_t width0;
307 uint16_t height0;
308
309 bool color_initialized:1;
310 bool depth_initialized:1;
311
312 /* Misc. color flags. */
313 bool color_is_int8:1;
314 bool color_is_int10:1;
315 bool dcc_incompatible:1;
316
317 /* Color registers. */
318 unsigned cb_color_info;
319 unsigned cb_color_view;
320 unsigned cb_color_attrib;
321 unsigned cb_color_attrib2; /* GFX9 and later */
322 unsigned cb_dcc_control; /* VI and later */
323 unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */
324 unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
325 unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
326 unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
327
328 /* DB registers. */
329 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
330 uint64_t db_stencil_base;
331 uint64_t db_htile_data_base;
332 unsigned db_depth_info;
333 unsigned db_z_info;
334 unsigned db_z_info2; /* GFX9+ */
335 unsigned db_depth_view;
336 unsigned db_depth_size;
337 unsigned db_depth_slice;
338 unsigned db_stencil_info;
339 unsigned db_stencil_info2; /* GFX9+ */
340 unsigned db_htile_surface;
341 };
342
343 struct si_mmio_counter {
344 unsigned busy;
345 unsigned idle;
346 };
347
348 union si_mmio_counters {
349 struct {
350 /* For global GPU load including SDMA. */
351 struct si_mmio_counter gpu;
352
353 /* GRBM_STATUS */
354 struct si_mmio_counter spi;
355 struct si_mmio_counter gui;
356 struct si_mmio_counter ta;
357 struct si_mmio_counter gds;
358 struct si_mmio_counter vgt;
359 struct si_mmio_counter ia;
360 struct si_mmio_counter sx;
361 struct si_mmio_counter wd;
362 struct si_mmio_counter bci;
363 struct si_mmio_counter sc;
364 struct si_mmio_counter pa;
365 struct si_mmio_counter db;
366 struct si_mmio_counter cp;
367 struct si_mmio_counter cb;
368
369 /* SRBM_STATUS2 */
370 struct si_mmio_counter sdma;
371
372 /* CP_STAT */
373 struct si_mmio_counter pfp;
374 struct si_mmio_counter meq;
375 struct si_mmio_counter me;
376 struct si_mmio_counter surf_sync;
377 struct si_mmio_counter cp_dma;
378 struct si_mmio_counter scratch_ram;
379 } named;
380 unsigned array[0];
381 };
382
383 struct si_memory_object {
384 struct pipe_memory_object b;
385 struct pb_buffer *buf;
386 uint32_t stride;
387 };
388
389 /* Saved CS data for debugging features. */
390 struct radeon_saved_cs {
391 uint32_t *ib;
392 unsigned num_dw;
393
394 struct radeon_bo_list_item *bo_list;
395 unsigned bo_count;
396 };
397
398 struct si_screen {
399 struct pipe_screen b;
400 struct radeon_winsys *ws;
401 struct disk_cache *disk_shader_cache;
402
403 struct radeon_info info;
404 uint64_t debug_flags;
405 char renderer_string[183];
406
407 unsigned gs_table_depth;
408 unsigned tess_offchip_block_dw_size;
409 unsigned tess_offchip_ring_size;
410 unsigned tess_factor_ring_size;
411 unsigned vgt_hs_offchip_param;
412 unsigned eqaa_force_coverage_samples;
413 unsigned eqaa_force_z_samples;
414 unsigned eqaa_force_color_samples;
415 bool has_clear_state;
416 bool has_distributed_tess;
417 bool has_draw_indirect_multi;
418 bool has_out_of_order_rast;
419 bool assume_no_z_fights;
420 bool commutative_blend_add;
421 bool clear_db_cache_before_clear;
422 bool has_msaa_sample_loc_bug;
423 bool has_ls_vgpr_init_bug;
424 bool dpbb_allowed;
425 bool dfsm_allowed;
426 bool llvm_has_working_vgpr_indexing;
427
428 /* Whether shaders are monolithic (1-part) or separate (3-part). */
429 bool use_monolithic_shaders;
430 bool record_llvm_ir;
431 bool has_rbplus; /* if RB+ registers exist */
432 bool rbplus_allowed; /* if RB+ is allowed */
433 bool dcc_msaa_allowed;
434 bool cpdma_prefetch_writes_memory;
435
436 struct slab_parent_pool pool_transfers;
437
438 /* Texture filter settings. */
439 int force_aniso; /* -1 = disabled */
440
441 /* Auxiliary context. Mainly used to initialize resources.
442 * It must be locked prior to using and flushed before unlocking. */
443 struct pipe_context *aux_context;
444 mtx_t aux_context_lock;
445
446 /* This must be in the screen, because UE4 uses one context for
447 * compilation and another one for rendering.
448 */
449 unsigned num_compilations;
450 /* Along with ST_DEBUG=precompile, this should show if applications
451 * are loading shaders on demand. This is a monotonic counter.
452 */
453 unsigned num_shaders_created;
454 unsigned num_shader_cache_hits;
455
456 /* GPU load thread. */
457 mtx_t gpu_load_mutex;
458 thrd_t gpu_load_thread;
459 union si_mmio_counters mmio_counters;
460 volatile unsigned gpu_load_stop_thread; /* bool */
461
462 /* Performance counters. */
463 struct si_perfcounters *perfcounters;
464
465 /* If pipe_screen wants to recompute and re-emit the framebuffer,
466 * sampler, and image states of all contexts, it should atomically
467 * increment this.
468 *
469 * Each context will compare this with its own last known value of
470 * the counter before drawing and re-emit the states accordingly.
471 */
472 unsigned dirty_tex_counter;
473
474 /* Atomically increment this counter when an existing texture's
475 * metadata is enabled or disabled in a way that requires changing
476 * contexts' compressed texture binding masks.
477 */
478 unsigned compressed_colortex_counter;
479
480 struct {
481 /* Context flags to set so that all writes from earlier jobs
482 * in the CP are seen by L2 clients.
483 */
484 unsigned cp_to_L2;
485
486 /* Context flags to set so that all writes from earlier jobs
487 * that end in L2 are seen by CP.
488 */
489 unsigned L2_to_cp;
490 } barrier_flags;
491
492 mtx_t shader_parts_mutex;
493 struct si_shader_part *vs_prologs;
494 struct si_shader_part *tcs_epilogs;
495 struct si_shader_part *gs_prologs;
496 struct si_shader_part *ps_prologs;
497 struct si_shader_part *ps_epilogs;
498
499 /* Shader cache in memory.
500 *
501 * Design & limitations:
502 * - The shader cache is per screen (= per process), never saved to
503 * disk, and skips redundant shader compilations from TGSI to bytecode.
504 * - It can only be used with one-variant-per-shader support, in which
505 * case only the main (typically middle) part of shaders is cached.
506 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
507 * variants of VS and TES are cached, so LS and ES aren't.
508 * - GS and CS aren't cached, but it's certainly possible to cache
509 * those as well.
510 */
511 mtx_t shader_cache_mutex;
512 struct hash_table *shader_cache;
513
514 /* Shader compiler queue for multithreaded compilation. */
515 struct util_queue shader_compiler_queue;
516 /* Use at most 3 normal compiler threads on quadcore and better.
517 * Hyperthreaded CPUs report the number of threads, but we want
518 * the number of cores. We only need this many threads for shader-db. */
519 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
520
521 struct util_queue shader_compiler_queue_low_priority;
522 /* Use at most 2 low priority threads on quadcore and better.
523 * We want to minimize the impact on multithreaded Mesa. */
524 struct ac_llvm_compiler compiler_lowp[10];
525 };
526
527 struct si_blend_color {
528 struct pipe_blend_color state;
529 bool any_nonzeros;
530 };
531
532 struct si_sampler_view {
533 struct pipe_sampler_view base;
534 /* [0..7] = image descriptor
535 * [4..7] = buffer descriptor */
536 uint32_t state[8];
537 uint32_t fmask_state[8];
538 const struct legacy_surf_level *base_level_info;
539 ubyte base_level;
540 ubyte block_width;
541 bool is_stencil_sampler;
542 bool is_integer;
543 bool dcc_incompatible;
544 };
545
546 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
547
548 struct si_sampler_state {
549 #ifdef DEBUG
550 unsigned magic;
551 #endif
552 uint32_t val[4];
553 uint32_t integer_val[4];
554 uint32_t upgraded_depth_val[4];
555 };
556
557 struct si_cs_shader_state {
558 struct si_compute *program;
559 struct si_compute *emitted_program;
560 unsigned offset;
561 bool initialized;
562 bool uses_scratch;
563 };
564
565 struct si_samplers {
566 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
567 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
568
569 /* The i-th bit is set if that element is enabled (non-NULL resource). */
570 unsigned enabled_mask;
571 uint32_t needs_depth_decompress_mask;
572 uint32_t needs_color_decompress_mask;
573 };
574
575 struct si_images {
576 struct pipe_image_view views[SI_NUM_IMAGES];
577 uint32_t needs_color_decompress_mask;
578 unsigned enabled_mask;
579 };
580
581 struct si_framebuffer {
582 struct pipe_framebuffer_state state;
583 unsigned colorbuf_enabled_4bit;
584 unsigned spi_shader_col_format;
585 unsigned spi_shader_col_format_alpha;
586 unsigned spi_shader_col_format_blend;
587 unsigned spi_shader_col_format_blend_alpha;
588 ubyte nr_samples:5; /* at most 16xAA */
589 ubyte log_samples:3; /* at most 4 = 16xAA */
590 ubyte nr_color_samples; /* at most 8xAA */
591 ubyte compressed_cb_mask;
592 ubyte uncompressed_cb_mask;
593 ubyte color_is_int8;
594 ubyte color_is_int10;
595 ubyte dirty_cbufs;
596 bool dirty_zsbuf;
597 bool any_dst_linear;
598 bool CB_has_shader_readable_metadata;
599 bool DB_has_shader_readable_metadata;
600 };
601
602 struct si_signed_scissor {
603 int minx;
604 int miny;
605 int maxx;
606 int maxy;
607 };
608
609 struct si_scissors {
610 unsigned dirty_mask;
611 struct pipe_scissor_state states[SI_MAX_VIEWPORTS];
612 };
613
614 struct si_viewports {
615 unsigned dirty_mask;
616 unsigned depth_range_dirty_mask;
617 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
618 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
619 };
620
621 struct si_clip_state {
622 struct pipe_clip_state state;
623 bool any_nonzeros;
624 };
625
626 struct si_streamout_target {
627 struct pipe_stream_output_target b;
628
629 /* The buffer where BUFFER_FILLED_SIZE is stored. */
630 struct r600_resource *buf_filled_size;
631 unsigned buf_filled_size_offset;
632 bool buf_filled_size_valid;
633
634 unsigned stride_in_dw;
635 };
636
637 struct si_streamout {
638 bool begin_emitted;
639
640 unsigned enabled_mask;
641 unsigned num_targets;
642 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
643
644 unsigned append_bitmask;
645 bool suspended;
646
647 /* External state which comes from the vertex shader,
648 * it must be set explicitly when binding a shader. */
649 uint16_t *stride_in_dw;
650 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
651
652 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
653 unsigned hw_enabled_mask;
654
655 /* The state of VGT_STRMOUT_(CONFIG|EN). */
656 bool streamout_enabled;
657 bool prims_gen_query_enabled;
658 int num_prims_gen_queries;
659 };
660
661 /* A shader state consists of the shader selector, which is a constant state
662 * object shared by multiple contexts and shouldn't be modified, and
663 * the current shader variant selected for this context.
664 */
665 struct si_shader_ctx_state {
666 struct si_shader_selector *cso;
667 struct si_shader *current;
668 };
669
670 #define SI_NUM_VGT_PARAM_KEY_BITS 12
671 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
672
673 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
674 * Some fields are set by state-change calls, most are set by draw_vbo.
675 */
676 union si_vgt_param_key {
677 struct {
678 #ifdef PIPE_ARCH_LITTLE_ENDIAN
679 unsigned prim:4;
680 unsigned uses_instancing:1;
681 unsigned multi_instances_smaller_than_primgroup:1;
682 unsigned primitive_restart:1;
683 unsigned count_from_stream_output:1;
684 unsigned line_stipple_enabled:1;
685 unsigned uses_tess:1;
686 unsigned tess_uses_prim_id:1;
687 unsigned uses_gs:1;
688 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
689 #else /* PIPE_ARCH_BIG_ENDIAN */
690 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
691 unsigned uses_gs:1;
692 unsigned tess_uses_prim_id:1;
693 unsigned uses_tess:1;
694 unsigned line_stipple_enabled:1;
695 unsigned count_from_stream_output:1;
696 unsigned primitive_restart:1;
697 unsigned multi_instances_smaller_than_primgroup:1;
698 unsigned uses_instancing:1;
699 unsigned prim:4;
700 #endif
701 } u;
702 uint32_t index;
703 };
704
705 struct si_texture_handle
706 {
707 unsigned desc_slot;
708 bool desc_dirty;
709 struct pipe_sampler_view *view;
710 struct si_sampler_state sstate;
711 };
712
713 struct si_image_handle
714 {
715 unsigned desc_slot;
716 bool desc_dirty;
717 struct pipe_image_view view;
718 };
719
720 struct si_saved_cs {
721 struct pipe_reference reference;
722 struct si_context *ctx;
723 struct radeon_saved_cs gfx;
724 struct r600_resource *trace_buf;
725 unsigned trace_id;
726
727 unsigned gfx_last_dw;
728 bool flushed;
729 int64_t time_flush;
730 };
731
732 struct si_context {
733 struct pipe_context b; /* base class */
734
735 enum radeon_family family;
736 enum chip_class chip_class;
737
738 struct radeon_winsys *ws;
739 struct radeon_winsys_ctx *ctx;
740 struct radeon_cmdbuf *gfx_cs;
741 struct radeon_cmdbuf *dma_cs;
742 struct pipe_fence_handle *last_gfx_fence;
743 struct pipe_fence_handle *last_sdma_fence;
744 struct r600_resource *eop_bug_scratch;
745 struct u_upload_mgr *cached_gtt_allocator;
746 struct threaded_context *tc;
747 struct u_suballocator *allocator_zeroed_memory;
748 struct slab_child_pool pool_transfers;
749 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
750 struct pipe_device_reset_callback device_reset_callback;
751 struct u_log_context *log;
752 void *query_result_shader;
753 struct blitter_context *blitter;
754 void *custom_dsa_flush;
755 void *custom_blend_resolve;
756 void *custom_blend_fmask_decompress;
757 void *custom_blend_eliminate_fastclear;
758 void *custom_blend_dcc_decompress;
759 void *vs_blit_pos;
760 void *vs_blit_pos_layered;
761 void *vs_blit_color;
762 void *vs_blit_color_layered;
763 void *vs_blit_texcoord;
764 struct si_screen *screen;
765 struct pipe_debug_callback debug;
766 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
767 struct si_shader_ctx_state fixed_func_tcs_shader;
768 struct r600_resource *wait_mem_scratch;
769 unsigned wait_mem_number;
770 uint16_t prefetch_L2_mask;
771
772 bool gfx_flush_in_progress:1;
773 bool gfx_last_ib_is_busy:1;
774 bool compute_is_busy:1;
775
776 unsigned num_gfx_cs_flushes;
777 unsigned initial_gfx_cs_size;
778 unsigned gpu_reset_counter;
779 unsigned last_dirty_tex_counter;
780 unsigned last_compressed_colortex_counter;
781 unsigned last_num_draw_calls;
782 unsigned flags; /* flush flags */
783 /* Current unaccounted memory usage. */
784 uint64_t vram;
785 uint64_t gtt;
786
787 /* Atoms (direct states). */
788 union si_state_atoms atoms;
789 unsigned dirty_atoms; /* mask */
790 /* PM4 states (precomputed immutable states) */
791 unsigned dirty_states;
792 union si_state queued;
793 union si_state emitted;
794
795 /* Atom declarations. */
796 struct si_framebuffer framebuffer;
797 unsigned sample_locs_num_samples;
798 uint16_t sample_mask;
799 unsigned last_cb_target_mask;
800 struct si_blend_color blend_color;
801 struct si_clip_state clip_state;
802 struct si_shader_data shader_pointers;
803 struct si_stencil_ref stencil_ref;
804 struct si_scissors scissors;
805 struct si_streamout streamout;
806 struct si_viewports viewports;
807 unsigned num_window_rectangles;
808 bool window_rectangles_include;
809 struct pipe_scissor_state window_rectangles[4];
810
811 /* Precomputed states. */
812 struct si_pm4_state *init_config;
813 struct si_pm4_state *init_config_gs_rings;
814 bool init_config_has_vgt_flush;
815 struct si_pm4_state *vgt_shader_config[4];
816
817 /* shaders */
818 struct si_shader_ctx_state ps_shader;
819 struct si_shader_ctx_state gs_shader;
820 struct si_shader_ctx_state vs_shader;
821 struct si_shader_ctx_state tcs_shader;
822 struct si_shader_ctx_state tes_shader;
823 struct si_cs_shader_state cs_shader_state;
824
825 /* shader information */
826 struct si_vertex_elements *vertex_elements;
827 unsigned sprite_coord_enable;
828 unsigned cs_max_waves_per_sh;
829 bool flatshade;
830 bool do_update_shaders;
831
832 /* vertex buffer descriptors */
833 uint32_t *vb_descriptors_gpu_list;
834 struct r600_resource *vb_descriptors_buffer;
835 unsigned vb_descriptors_offset;
836
837 /* shader descriptors */
838 struct si_descriptors descriptors[SI_NUM_DESCS];
839 unsigned descriptors_dirty;
840 unsigned shader_pointers_dirty;
841 unsigned shader_needs_decompress_mask;
842 struct si_buffer_resources rw_buffers;
843 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
844 struct si_samplers samplers[SI_NUM_SHADERS];
845 struct si_images images[SI_NUM_SHADERS];
846
847 /* other shader resources */
848 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
849 struct pipe_resource *esgs_ring;
850 struct pipe_resource *gsvs_ring;
851 struct pipe_resource *tess_rings;
852 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
853 struct r600_resource *border_color_buffer;
854 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
855 unsigned border_color_count;
856 unsigned num_vs_blit_sgprs;
857 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
858 uint32_t cs_user_data[4];
859
860 /* Vertex and index buffers. */
861 bool vertex_buffers_dirty;
862 bool vertex_buffer_pointer_dirty;
863 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
864
865 /* MSAA config state. */
866 int ps_iter_samples;
867 bool ps_uses_fbfetch;
868 bool smoothing_enabled;
869
870 /* DB render state. */
871 unsigned ps_db_shader_control;
872 unsigned dbcb_copy_sample;
873 bool dbcb_depth_copy_enabled:1;
874 bool dbcb_stencil_copy_enabled:1;
875 bool db_flush_depth_inplace:1;
876 bool db_flush_stencil_inplace:1;
877 bool db_depth_clear:1;
878 bool db_depth_disable_expclear:1;
879 bool db_stencil_clear:1;
880 bool db_stencil_disable_expclear:1;
881 bool occlusion_queries_disabled:1;
882 bool generate_mipmap_for_depth:1;
883
884 /* Emitted draw state. */
885 bool gs_tri_strip_adj_fix:1;
886 bool ls_vgpr_fix:1;
887 int last_index_size;
888 int last_base_vertex;
889 int last_start_instance;
890 int last_drawid;
891 int last_sh_base_reg;
892 int last_primitive_restart_en;
893 int last_restart_index;
894 int last_prim;
895 int last_multi_vgt_param;
896 int last_rast_prim;
897 unsigned last_sc_line_stipple;
898 unsigned current_vs_state;
899 unsigned last_vs_state;
900 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
901
902 /* Scratch buffer */
903 struct r600_resource *scratch_buffer;
904 unsigned scratch_waves;
905 unsigned spi_tmpring_size;
906
907 struct r600_resource *compute_scratch_buffer;
908
909 /* Emitted derived tessellation state. */
910 /* Local shader (VS), or HS if LS-HS are merged. */
911 struct si_shader *last_ls;
912 struct si_shader_selector *last_tcs;
913 int last_num_tcs_input_cp;
914 int last_tes_sh_base;
915 bool last_tess_uses_primid;
916 unsigned last_num_patches;
917 int last_ls_hs_config;
918
919 /* Debug state. */
920 bool is_debug;
921 struct si_saved_cs *current_saved_cs;
922 uint64_t dmesg_timestamp;
923 unsigned apitrace_call_number;
924
925 /* Other state */
926 bool need_check_render_feedback;
927 bool decompression_enabled;
928 bool dpbb_force_off;
929 bool vs_writes_viewport_index;
930 bool vs_disables_clipping_viewport;
931
932 /* Precomputed IA_MULTI_VGT_PARAM */
933 union si_vgt_param_key ia_multi_vgt_param_key;
934 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
935
936 /* Bindless descriptors. */
937 struct si_descriptors bindless_descriptors;
938 struct util_idalloc bindless_used_slots;
939 unsigned num_bindless_descriptors;
940 bool bindless_descriptors_dirty;
941 bool graphics_bindless_pointer_dirty;
942 bool compute_bindless_pointer_dirty;
943
944 /* Allocated bindless handles */
945 struct hash_table *tex_handles;
946 struct hash_table *img_handles;
947
948 /* Resident bindless handles */
949 struct util_dynarray resident_tex_handles;
950 struct util_dynarray resident_img_handles;
951
952 /* Resident bindless handles which need decompression */
953 struct util_dynarray resident_tex_needs_color_decompress;
954 struct util_dynarray resident_img_needs_color_decompress;
955 struct util_dynarray resident_tex_needs_depth_decompress;
956
957 /* Bindless state */
958 bool uses_bindless_samplers;
959 bool uses_bindless_images;
960
961 /* MSAA sample locations.
962 * The first index is the sample index.
963 * The second index is the coordinate: X, Y. */
964 float sample_locations_1x[1][2];
965 float sample_locations_2x[2][2];
966 float sample_locations_4x[4][2];
967 float sample_locations_8x[8][2];
968 float sample_locations_16x[16][2];
969
970 /* Misc stats. */
971 unsigned num_draw_calls;
972 unsigned num_decompress_calls;
973 unsigned num_mrt_draw_calls;
974 unsigned num_prim_restart_calls;
975 unsigned num_spill_draw_calls;
976 unsigned num_compute_calls;
977 unsigned num_spill_compute_calls;
978 unsigned num_dma_calls;
979 unsigned num_cp_dma_calls;
980 unsigned num_vs_flushes;
981 unsigned num_ps_flushes;
982 unsigned num_cs_flushes;
983 unsigned num_cb_cache_flushes;
984 unsigned num_db_cache_flushes;
985 unsigned num_L2_invalidates;
986 unsigned num_L2_writebacks;
987 unsigned num_resident_handles;
988 uint64_t num_alloc_tex_transfer_bytes;
989 unsigned last_tex_ps_draw_ratio; /* for query */
990
991 /* Queries. */
992 /* Maintain the list of active queries for pausing between IBs. */
993 int num_occlusion_queries;
994 int num_perfect_occlusion_queries;
995 struct list_head active_queries;
996 unsigned num_cs_dw_queries_suspend;
997
998 /* Render condition. */
999 struct pipe_query *render_cond;
1000 unsigned render_cond_mode;
1001 bool render_cond_invert;
1002 bool render_cond_force_off; /* for u_blitter */
1003
1004 /* Statistics gathering for the DCC enablement heuristic. It can't be
1005 * in si_texture because si_texture can be shared by multiple
1006 * contexts. This is for back buffers only. We shouldn't get too many
1007 * of those.
1008 *
1009 * X11 DRI3 rotates among a finite set of back buffers. They should
1010 * all fit in this array. If they don't, separate DCC might never be
1011 * enabled by DCC stat gathering.
1012 */
1013 struct {
1014 struct si_texture *tex;
1015 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1016 struct pipe_query *ps_stats[3];
1017 /* If all slots are used and another slot is needed,
1018 * the least recently used slot is evicted based on this. */
1019 int64_t last_use_timestamp;
1020 bool query_active;
1021 } dcc_stats[5];
1022
1023 /* Copy one resource to another using async DMA. */
1024 void (*dma_copy)(struct pipe_context *ctx,
1025 struct pipe_resource *dst,
1026 unsigned dst_level,
1027 unsigned dst_x, unsigned dst_y, unsigned dst_z,
1028 struct pipe_resource *src,
1029 unsigned src_level,
1030 const struct pipe_box *src_box);
1031
1032 void (*dma_clear_buffer)(struct si_context *sctx, struct pipe_resource *dst,
1033 uint64_t offset, uint64_t size, unsigned value);
1034
1035 struct si_tracked_regs tracked_regs;
1036 };
1037
1038 /* cik_sdma.c */
1039 void cik_init_sdma_functions(struct si_context *sctx);
1040
1041 /* si_blit.c */
1042 enum si_blitter_op /* bitmask */
1043 {
1044 SI_SAVE_TEXTURES = 1,
1045 SI_SAVE_FRAMEBUFFER = 2,
1046 SI_SAVE_FRAGMENT_STATE = 4,
1047 SI_DISABLE_RENDER_COND = 8,
1048 };
1049
1050 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1051 void si_blitter_end(struct si_context *sctx);
1052 void si_init_blit_functions(struct si_context *sctx);
1053 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1054 void si_resource_copy_region(struct pipe_context *ctx,
1055 struct pipe_resource *dst,
1056 unsigned dst_level,
1057 unsigned dstx, unsigned dsty, unsigned dstz,
1058 struct pipe_resource *src,
1059 unsigned src_level,
1060 const struct pipe_box *src_box);
1061 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1062 void si_blit_decompress_depth(struct pipe_context *ctx,
1063 struct si_texture *texture,
1064 struct si_texture *staging,
1065 unsigned first_level, unsigned last_level,
1066 unsigned first_layer, unsigned last_layer,
1067 unsigned first_sample, unsigned last_sample);
1068
1069 /* si_buffer.c */
1070 bool si_rings_is_buffer_referenced(struct si_context *sctx,
1071 struct pb_buffer *buf,
1072 enum radeon_bo_usage usage);
1073 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
1074 struct r600_resource *resource,
1075 unsigned usage);
1076 void si_init_resource_fields(struct si_screen *sscreen,
1077 struct r600_resource *res,
1078 uint64_t size, unsigned alignment);
1079 bool si_alloc_resource(struct si_screen *sscreen,
1080 struct r600_resource *res);
1081 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
1082 unsigned flags, unsigned usage,
1083 unsigned size, unsigned alignment);
1084 struct r600_resource *si_aligned_buffer_create(struct pipe_screen *screen,
1085 unsigned flags, unsigned usage,
1086 unsigned size, unsigned alignment);
1087 void si_replace_buffer_storage(struct pipe_context *ctx,
1088 struct pipe_resource *dst,
1089 struct pipe_resource *src);
1090 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1091 void si_init_buffer_functions(struct si_context *sctx);
1092
1093 /* si_clear.c */
1094 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1095 bool vi_alpha_is_on_msb(enum pipe_format format);
1096 void vi_dcc_clear_level(struct si_context *sctx,
1097 struct si_texture *tex,
1098 unsigned level, unsigned clear_value);
1099 void si_init_clear_functions(struct si_context *sctx);
1100
1101 /* si_cp_dma.c */
1102 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1103 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1104 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1105 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1106 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1107 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1108 SI_CPDMA_SKIP_SYNC_AFTER | \
1109 SI_CPDMA_SKIP_SYNC_BEFORE | \
1110 SI_CPDMA_SKIP_GFX_SYNC | \
1111 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1112
1113 enum si_cache_policy {
1114 L2_BYPASS,
1115 L2_STREAM, /* same as SLC=1 */
1116 L2_LRU, /* same as SLC=0 */
1117 };
1118
1119 enum si_coherency {
1120 SI_COHERENCY_NONE, /* no cache flushes needed */
1121 SI_COHERENCY_SHADER,
1122 SI_COHERENCY_CB_META,
1123 };
1124
1125 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1126 void si_cp_dma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1127 uint64_t offset, uint64_t size, unsigned value,
1128 enum si_coherency coher,
1129 enum si_cache_policy cache_policy);
1130 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1131 uint64_t offset, uint64_t size, unsigned value,
1132 enum si_coherency coher);
1133 void si_copy_buffer(struct si_context *sctx,
1134 struct pipe_resource *dst, struct pipe_resource *src,
1135 uint64_t dst_offset, uint64_t src_offset, unsigned size,
1136 unsigned user_flags, enum si_cache_policy cache_policy);
1137 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
1138 uint64_t offset, unsigned size);
1139 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1140 void si_init_cp_dma_functions(struct si_context *sctx);
1141
1142 /* si_debug.c */
1143 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
1144 struct radeon_saved_cs *saved, bool get_buffer_list);
1145 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1146 void si_destroy_saved_cs(struct si_saved_cs *scs);
1147 void si_auto_log_cs(void *data, struct u_log_context *log);
1148 void si_log_hw_flush(struct si_context *sctx);
1149 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1150 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1151 void si_init_debug_functions(struct si_context *sctx);
1152 void si_check_vm_faults(struct si_context *sctx,
1153 struct radeon_saved_cs *saved, enum ring_type ring);
1154 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
1155
1156 /* si_dma.c */
1157 void si_init_dma_functions(struct si_context *sctx);
1158
1159 /* si_dma_cs.c */
1160 void si_dma_emit_timestamp(struct si_context *sctx, struct r600_resource *dst,
1161 uint64_t offset);
1162 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
1163 struct r600_resource *dst, struct r600_resource *src);
1164 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
1165 struct pipe_fence_handle **fence);
1166 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
1167 uint64_t offset, uint64_t size, unsigned value);
1168
1169 /* si_fence.c */
1170 void si_gfx_write_event_eop(struct si_context *ctx,
1171 unsigned event, unsigned event_flags,
1172 unsigned data_sel,
1173 struct r600_resource *buf, uint64_t va,
1174 uint32_t new_fence, unsigned query_type);
1175 unsigned si_gfx_write_fence_dwords(struct si_screen *screen);
1176 void si_gfx_wait_fence(struct si_context *ctx,
1177 uint64_t va, uint32_t ref, uint32_t mask);
1178 void si_init_fence_functions(struct si_context *ctx);
1179 void si_init_screen_fence_functions(struct si_screen *screen);
1180 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1181 struct tc_unflushed_batch_token *tc_token);
1182
1183 /* si_get.c */
1184 void si_init_screen_get_functions(struct si_screen *sscreen);
1185
1186 /* si_gfx_cs.c */
1187 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
1188 struct pipe_fence_handle **fence);
1189 void si_begin_new_gfx_cs(struct si_context *ctx);
1190 void si_need_gfx_cs_space(struct si_context *ctx);
1191
1192 /* r600_gpu_load.c */
1193 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1194 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1195 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
1196 uint64_t begin);
1197
1198 /* si_compute.c */
1199 void si_init_compute_functions(struct si_context *sctx);
1200
1201 /* r600_perfcounters.c */
1202 void si_perfcounters_destroy(struct si_screen *sscreen);
1203
1204 /* si_perfcounters.c */
1205 void si_init_perfcounters(struct si_screen *screen);
1206
1207 /* si_pipe.c */
1208 bool si_check_device_reset(struct si_context *sctx);
1209
1210 /* si_query.c */
1211 void si_init_screen_query_functions(struct si_screen *sscreen);
1212 void si_init_query_functions(struct si_context *sctx);
1213 void si_suspend_queries(struct si_context *sctx);
1214 void si_resume_queries(struct si_context *sctx);
1215
1216 /* si_shaderlib_tgsi.c */
1217 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1218 unsigned num_layers);
1219 void *si_create_fixed_func_tcs(struct si_context *sctx);
1220 void *si_create_dma_compute_shader(struct pipe_context *ctx,
1221 unsigned num_dwords_per_thread,
1222 bool dst_stream_cache_policy, bool is_copy);
1223 void *si_create_query_result_cs(struct si_context *sctx);
1224
1225 /* si_test_dma.c */
1226 void si_test_dma(struct si_screen *sscreen);
1227
1228 /* si_test_clearbuffer.c */
1229 void si_test_dma_perf(struct si_screen *sscreen);
1230
1231 /* si_uvd.c */
1232 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1233 const struct pipe_video_codec *templ);
1234
1235 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1236 const struct pipe_video_buffer *tmpl);
1237
1238 /* si_viewport.c */
1239 void si_update_vs_viewport_state(struct si_context *ctx);
1240 void si_init_viewport_functions(struct si_context *ctx);
1241
1242 /* si_texture.c */
1243 bool si_prepare_for_dma_blit(struct si_context *sctx,
1244 struct si_texture *dst,
1245 unsigned dst_level, unsigned dstx,
1246 unsigned dsty, unsigned dstz,
1247 struct si_texture *src,
1248 unsigned src_level,
1249 const struct pipe_box *src_box);
1250 void si_eliminate_fast_color_clear(struct si_context *sctx,
1251 struct si_texture *tex);
1252 void si_texture_discard_cmask(struct si_screen *sscreen,
1253 struct si_texture *tex);
1254 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1255 struct pipe_resource *texture,
1256 struct si_texture **staging);
1257 void si_print_texture_info(struct si_screen *sscreen,
1258 struct si_texture *tex, struct u_log_context *log);
1259 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1260 const struct pipe_resource *templ);
1261 bool vi_dcc_formats_compatible(enum pipe_format format1,
1262 enum pipe_format format2);
1263 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1264 unsigned level,
1265 enum pipe_format view_format);
1266 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1267 struct pipe_resource *tex,
1268 unsigned level,
1269 enum pipe_format view_format);
1270 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1271 struct pipe_resource *texture,
1272 const struct pipe_surface *templ,
1273 unsigned width0, unsigned height0,
1274 unsigned width, unsigned height);
1275 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1276 void vi_separate_dcc_try_enable(struct si_context *sctx,
1277 struct si_texture *tex);
1278 void vi_separate_dcc_start_query(struct si_context *sctx,
1279 struct si_texture *tex);
1280 void vi_separate_dcc_stop_query(struct si_context *sctx,
1281 struct si_texture *tex);
1282 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1283 struct si_texture *tex);
1284 bool si_texture_disable_dcc(struct si_context *sctx,
1285 struct si_texture *tex);
1286 void si_init_screen_texture_functions(struct si_screen *sscreen);
1287 void si_init_context_texture_functions(struct si_context *sctx);
1288
1289
1290 /*
1291 * common helpers
1292 */
1293
1294 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
1295 {
1296 return (struct r600_resource*)r;
1297 }
1298
1299 static inline void
1300 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
1301 {
1302 pipe_resource_reference((struct pipe_resource **)ptr,
1303 (struct pipe_resource *)res);
1304 }
1305
1306 static inline void
1307 si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1308 {
1309 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1310 }
1311
1312 static inline bool
1313 vi_dcc_enabled(struct si_texture *tex, unsigned level)
1314 {
1315 return tex->dcc_offset && level < tex->surface.num_dcc_levels;
1316 }
1317
1318 static inline unsigned
1319 si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1320 {
1321 if (stencil)
1322 return tex->surface.u.legacy.stencil_tiling_index[level];
1323 else
1324 return tex->surface.u.legacy.tiling_index[level];
1325 }
1326
1327 static inline void
1328 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1329 {
1330 if (r) {
1331 /* Add memory usage for need_gfx_cs_space */
1332 sctx->vram += r600_resource(r)->vram_usage;
1333 sctx->gtt += r600_resource(r)->gart_usage;
1334 }
1335 }
1336
1337 static inline void
1338 si_invalidate_draw_sh_constants(struct si_context *sctx)
1339 {
1340 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1341 }
1342
1343 static inline unsigned
1344 si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1345 {
1346 return 1 << (atom - sctx->atoms.array);
1347 }
1348
1349 static inline void
1350 si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1351 {
1352 unsigned bit = si_get_atom_bit(sctx, atom);
1353
1354 if (dirty)
1355 sctx->dirty_atoms |= bit;
1356 else
1357 sctx->dirty_atoms &= ~bit;
1358 }
1359
1360 static inline bool
1361 si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1362 {
1363 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1364 }
1365
1366 static inline void
1367 si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1368 {
1369 si_set_atom_dirty(sctx, atom, true);
1370 }
1371
1372 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1373 {
1374 if (sctx->gs_shader.cso)
1375 return &sctx->gs_shader;
1376 if (sctx->tes_shader.cso)
1377 return &sctx->tes_shader;
1378
1379 return &sctx->vs_shader;
1380 }
1381
1382 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1383 {
1384 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1385
1386 return vs->cso ? &vs->cso->info : NULL;
1387 }
1388
1389 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1390 {
1391 if (sctx->gs_shader.cso)
1392 return sctx->gs_shader.cso->gs_copy_shader;
1393
1394 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1395 return vs->current ? vs->current : NULL;
1396 }
1397
1398 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1399 unsigned processor)
1400 {
1401 return sscreen->debug_flags & (1 << processor);
1402 }
1403
1404 static inline bool si_get_strmout_en(struct si_context *sctx)
1405 {
1406 return sctx->streamout.streamout_enabled ||
1407 sctx->streamout.prims_gen_query_enabled;
1408 }
1409
1410 static inline unsigned
1411 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1412 {
1413 unsigned alignment, tcc_cache_line_size;
1414
1415 /* If the upload size is less than the cache line size (e.g. 16, 32),
1416 * the whole thing will fit into a cache line if we align it to its size.
1417 * The idea is that multiple small uploads can share a cache line.
1418 * If the upload size is greater, align it to the cache line size.
1419 */
1420 alignment = util_next_power_of_two(upload_size);
1421 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1422 return MIN2(alignment, tcc_cache_line_size);
1423 }
1424
1425 static inline void
1426 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1427 {
1428 if (pipe_reference(&(*dst)->reference, &src->reference))
1429 si_destroy_saved_cs(*dst);
1430
1431 *dst = src;
1432 }
1433
1434 static inline void
1435 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1436 bool shaders_read_metadata)
1437 {
1438 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1439 SI_CONTEXT_INV_VMEM_L1;
1440
1441 if (sctx->chip_class >= GFX9) {
1442 /* Single-sample color is coherent with shaders on GFX9, but
1443 * L2 metadata must be flushed if shaders read metadata.
1444 * (DCC, CMASK).
1445 */
1446 if (num_samples >= 2)
1447 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1448 else if (shaders_read_metadata)
1449 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1450 } else {
1451 /* SI-CI-VI */
1452 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1453 }
1454 }
1455
1456 static inline void
1457 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1458 bool include_stencil, bool shaders_read_metadata)
1459 {
1460 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1461 SI_CONTEXT_INV_VMEM_L1;
1462
1463 if (sctx->chip_class >= GFX9) {
1464 /* Single-sample depth (not stencil) is coherent with shaders
1465 * on GFX9, but L2 metadata must be flushed if shaders read
1466 * metadata.
1467 */
1468 if (num_samples >= 2 || include_stencil)
1469 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1470 else if (shaders_read_metadata)
1471 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1472 } else {
1473 /* SI-CI-VI */
1474 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1475 }
1476 }
1477
1478 static inline bool
1479 si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1480 {
1481 return (stencil_sampler && tex->can_sample_s) ||
1482 (!stencil_sampler && tex->can_sample_z);
1483 }
1484
1485 static inline bool
1486 si_htile_enabled(struct si_texture *tex, unsigned level)
1487 {
1488 return tex->htile_offset && level == 0;
1489 }
1490
1491 static inline bool
1492 vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level)
1493 {
1494 assert(!tex->tc_compatible_htile || tex->htile_offset);
1495 return tex->tc_compatible_htile && level == 0;
1496 }
1497
1498 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1499 {
1500 if (sctx->ps_uses_fbfetch)
1501 return sctx->framebuffer.nr_color_samples;
1502
1503 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1504 }
1505
1506 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1507 {
1508 if (sctx->queued.named.rasterizer->rasterizer_discard)
1509 return 0;
1510
1511 struct si_shader_selector *ps = sctx->ps_shader.cso;
1512 if (!ps)
1513 return 0;
1514
1515 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1516 sctx->queued.named.blend->cb_target_mask;
1517
1518 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1519 colormask &= ps->colors_written_4bit;
1520 else if (!ps->colors_written_4bit)
1521 colormask = 0; /* color0 writes all cbufs, but it's not written */
1522
1523 return colormask;
1524 }
1525
1526 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1527 (1 << PIPE_PRIM_LINE_LOOP) | \
1528 (1 << PIPE_PRIM_LINE_STRIP) | \
1529 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1530 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1531
1532 static inline bool util_prim_is_lines(unsigned prim)
1533 {
1534 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1535 }
1536
1537 static inline bool util_prim_is_points_or_lines(unsigned prim)
1538 {
1539 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES |
1540 (1 << PIPE_PRIM_POINTS))) != 0;
1541 }
1542
1543 /**
1544 * Return true if there is enough memory in VRAM and GTT for the buffers
1545 * added so far.
1546 *
1547 * \param vram VRAM memory size not added to the buffer list yet
1548 * \param gtt GTT memory size not added to the buffer list yet
1549 */
1550 static inline bool
1551 radeon_cs_memory_below_limit(struct si_screen *screen,
1552 struct radeon_cmdbuf *cs,
1553 uint64_t vram, uint64_t gtt)
1554 {
1555 vram += cs->used_vram;
1556 gtt += cs->used_gart;
1557
1558 /* Anything that goes above the VRAM size should go to GTT. */
1559 if (vram > screen->info.vram_size)
1560 gtt += vram - screen->info.vram_size;
1561
1562 /* Now we just need to check if we have enough GTT. */
1563 return gtt < screen->info.gart_size * 0.7;
1564 }
1565
1566 /**
1567 * Add a buffer to the buffer list for the given command stream (CS).
1568 *
1569 * All buffers used by a CS must be added to the list. This tells the kernel
1570 * driver which buffers are used by GPU commands. Other buffers can
1571 * be swapped out (not accessible) during execution.
1572 *
1573 * The buffer list becomes empty after every context flush and must be
1574 * rebuilt.
1575 */
1576 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1577 struct radeon_cmdbuf *cs,
1578 struct r600_resource *rbo,
1579 enum radeon_bo_usage usage,
1580 enum radeon_bo_priority priority)
1581 {
1582 assert(usage);
1583 sctx->ws->cs_add_buffer(
1584 cs, rbo->buf,
1585 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1586 rbo->domains, priority);
1587 }
1588
1589 /**
1590 * Same as above, but also checks memory usage and flushes the context
1591 * accordingly.
1592 *
1593 * When this SHOULD NOT be used:
1594 *
1595 * - if si_context_add_resource_size has been called for the buffer
1596 * followed by *_need_cs_space for checking the memory usage
1597 *
1598 * - if si_need_dma_space has been called for the buffer
1599 *
1600 * - when emitting state packets and draw packets (because preceding packets
1601 * can't be re-emitted at that point)
1602 *
1603 * - if shader resource "enabled_mask" is not up-to-date or there is
1604 * a different constraint disallowing a context flush
1605 */
1606 static inline void
1607 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1608 struct r600_resource *rbo,
1609 enum radeon_bo_usage usage,
1610 enum radeon_bo_priority priority,
1611 bool check_mem)
1612 {
1613 if (check_mem &&
1614 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1615 sctx->vram + rbo->vram_usage,
1616 sctx->gtt + rbo->gart_usage))
1617 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1618
1619 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, rbo, usage, priority);
1620 }
1621
1622 #define PRINT_ERR(fmt, args...) \
1623 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1624
1625 #endif