src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef SI_PIPE_H
  24 #define SI_PIPE_H
  25
  26 #include "si_shader.h"
  27
  28 #include "util/u_dynarray.h"
  29 #include "util/u_idalloc.h"
  30
  31 #ifdef PIPE_ARCH_BIG_ENDIAN
  32 #define SI_BIG_ENDIAN 1
  33 #else
  34 #define SI_BIG_ENDIAN 0
  35 #endif
  36
  37 #define ATI_VENDOR_ID 0x1002
  38
  39 #define SI_NOT_QUERY            0xffffffff
  40
  41 /* The base vertex and primitive restart can be any number, but we must pick
  42  * one which will mean "unknown" for the purpose of state tracking and
  43  * the number shouldn't be a commonly-used one. */
  44 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  45 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  46 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  47 #define SI_GS_PER_ES 128
  48 /* Alignment for optimal CP DMA performance. */
  49 #define SI_CPDMA_ALIGNMENT      32
  50
  51 /* Instruction cache. */
  52 #define SI_CONTEXT_INV_ICACHE           (R600_CONTEXT_PRIVATE_FLAG << 0)
  53 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  54 #define SI_CONTEXT_INV_SMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 1)
  55 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  56 #define SI_CONTEXT_INV_VMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 2)
  57 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  58 #define SI_CONTEXT_INV_GLOBAL_L2        (R600_CONTEXT_PRIVATE_FLAG << 3)
  59 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  60  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
  61 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2  (R600_CONTEXT_PRIVATE_FLAG << 4)
  62 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
  63  * a CB or DB flush. */
  64 #define SI_CONTEXT_INV_L2_METADATA      (R600_CONTEXT_PRIVATE_FLAG << 5)
  65 /* Framebuffer caches. */
  66 #define SI_CONTEXT_FLUSH_AND_INV_DB     (R600_CONTEXT_PRIVATE_FLAG << 6)
  67 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 7)
  68 #define SI_CONTEXT_FLUSH_AND_INV_CB     (R600_CONTEXT_PRIVATE_FLAG << 8)
  69 /* Engine synchronization. */
  70 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 9)
  71 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 10)
  72 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 11)
  73 #define SI_CONTEXT_VGT_FLUSH            (R600_CONTEXT_PRIVATE_FLAG << 12)
  74 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (R600_CONTEXT_PRIVATE_FLAG << 13)
  75
  76 #define SI_PREFETCH_VBO_DESCRIPTORS     (1 << 0)
  77 #define SI_PREFETCH_LS                  (1 << 1)
  78 #define SI_PREFETCH_HS                  (1 << 2)
  79 #define SI_PREFETCH_ES                  (1 << 3)
  80 #define SI_PREFETCH_GS                  (1 << 4)
  81 #define SI_PREFETCH_VS                  (1 << 5)
  82 #define SI_PREFETCH_PS                  (1 << 6)
  83
  84 #define SI_MAX_BORDER_COLORS    4096
  85 #define SI_MAX_VIEWPORTS        16
  86 #define SIX_BITS                0x3F
  87
  88 struct si_compute;
  89 struct hash_table;
  90 struct u_suballocator;
  91
  92 struct si_screen {
  93         struct r600_common_screen       b;
  94         unsigned                        gs_table_depth;
  95         unsigned                        tess_offchip_block_dw_size;
  96         bool                            has_clear_state;
  97         bool                            has_distributed_tess;
  98         bool                            has_draw_indirect_multi;
  99         bool                            has_out_of_order_rast;
 100         bool                            assume_no_z_fights;
 101         bool                            commutative_blend_add;
 102         bool                            clear_db_cache_before_clear;
 103         bool                            has_msaa_sample_loc_bug;
 104         bool                            has_ls_vgpr_init_bug;
 105         bool                            dpbb_allowed;
 106         bool                            dfsm_allowed;
 107         bool                            llvm_has_working_vgpr_indexing;
 108
 109         /* Whether shaders are monolithic (1-part) or separate (3-part). */
 110         bool                            use_monolithic_shaders;
 111         bool                            record_llvm_ir;
 112
 113         mtx_t                   shader_parts_mutex;
 114         struct si_shader_part           *vs_prologs;
 115         struct si_shader_part           *tcs_epilogs;
 116         struct si_shader_part           *gs_prologs;
 117         struct si_shader_part           *ps_prologs;
 118         struct si_shader_part           *ps_epilogs;
 119
 120         /* Shader cache in memory.
 121          *
 122          * Design & limitations:
 123          * - The shader cache is per screen (= per process), never saved to
 124          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 125          * - It can only be used with one-variant-per-shader support, in which
 126          *   case only the main (typically middle) part of shaders is cached.
 127          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 128          *   variants of VS and TES are cached, so LS and ES aren't.
 129          * - GS and CS aren't cached, but it's certainly possible to cache
 130          *   those as well.
 131          */
 132         mtx_t                   shader_cache_mutex;
 133         struct hash_table               *shader_cache;
 134
 135         /* Shader compiler queue for multithreaded compilation. */
 136         struct util_queue               shader_compiler_queue;
 137         /* Use at most 3 normal compiler threads on quadcore and better.
 138          * Hyperthreaded CPUs report the number of threads, but we want
 139          * the number of cores. */
 140         LLVMTargetMachineRef            tm[3]; /* used by the queue only */
 141
 142         struct util_queue               shader_compiler_queue_low_priority;
 143         /* Use at most 2 low priority threads on quadcore and better.
 144          * We want to minimize the impact on multithreaded Mesa. */
 145         LLVMTargetMachineRef            tm_low_priority[2]; /* at most 2 threads */
 146 };
 147
 148 struct si_blend_color {
 149         struct r600_atom                atom;
 150         struct pipe_blend_color         state;
 151         bool                            any_nonzeros;
 152 };
 153
 154 struct si_sampler_view {
 155         struct pipe_sampler_view        base;
 156         /* [0..7] = image descriptor
 157          * [4..7] = buffer descriptor */
 158         uint32_t                        state[8];
 159         uint32_t                        fmask_state[8];
 160         const struct legacy_surf_level  *base_level_info;
 161         ubyte                           base_level;
 162         ubyte                           block_width;
 163         bool is_stencil_sampler;
 164         bool is_integer;
 165         bool dcc_incompatible;
 166 };
 167
 168 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
 169
 170 struct si_sampler_state {
 171 #ifdef DEBUG
 172         unsigned                        magic;
 173 #endif
 174         uint32_t                        val[4];
 175         uint32_t                        integer_val[4];
 176         uint32_t                        upgraded_depth_val[4];
 177 };
 178
 179 struct si_cs_shader_state {
 180         struct si_compute               *program;
 181         struct si_compute               *emitted_program;
 182         unsigned                        offset;
 183         bool                            initialized;
 184         bool                            uses_scratch;
 185 };
 186
 187 struct si_samplers {
 188         struct pipe_sampler_view        *views[SI_NUM_SAMPLERS];
 189         struct si_sampler_state         *sampler_states[SI_NUM_SAMPLERS];
 190
 191         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 192         unsigned                        enabled_mask;
 193         uint32_t                        needs_depth_decompress_mask;
 194         uint32_t                        needs_color_decompress_mask;
 195 };
 196
 197 struct si_images {
 198         struct pipe_image_view          views[SI_NUM_IMAGES];
 199         uint32_t                        needs_color_decompress_mask;
 200         unsigned                        enabled_mask;
 201 };
 202
 203 struct si_framebuffer {
 204         struct r600_atom                atom;
 205         struct pipe_framebuffer_state   state;
 206         unsigned                        colorbuf_enabled_4bit;
 207         unsigned                        spi_shader_col_format;
 208         unsigned                        spi_shader_col_format_alpha;
 209         unsigned                        spi_shader_col_format_blend;
 210         unsigned                        spi_shader_col_format_blend_alpha;
 211         ubyte                           nr_samples:5; /* at most 16xAA */
 212         ubyte                           log_samples:3; /* at most 4 = 16xAA */
 213         ubyte                           compressed_cb_mask;
 214         ubyte                           color_is_int8;
 215         ubyte                           color_is_int10;
 216         ubyte                           dirty_cbufs;
 217         bool                            dirty_zsbuf;
 218         bool                            any_dst_linear;
 219         bool                            CB_has_shader_readable_metadata;
 220         bool                            DB_has_shader_readable_metadata;
 221 };
 222
 223 struct si_signed_scissor {
 224         int minx;
 225         int miny;
 226         int maxx;
 227         int maxy;
 228 };
 229
 230 struct si_scissors {
 231         struct r600_atom                atom;
 232         unsigned                        dirty_mask;
 233         struct pipe_scissor_state       states[SI_MAX_VIEWPORTS];
 234 };
 235
 236 struct si_viewports {
 237         struct r600_atom                atom;
 238         unsigned                        dirty_mask;
 239         unsigned                        depth_range_dirty_mask;
 240         struct pipe_viewport_state      states[SI_MAX_VIEWPORTS];
 241         struct si_signed_scissor        as_scissor[SI_MAX_VIEWPORTS];
 242 };
 243
 244 struct si_clip_state {
 245         struct r600_atom                atom;
 246         struct pipe_clip_state          state;
 247         bool                            any_nonzeros;
 248 };
 249
 250 struct si_sample_locs {
 251         struct r600_atom        atom;
 252         unsigned                nr_samples;
 253 };
 254
 255 struct si_sample_mask {
 256         struct r600_atom        atom;
 257         uint16_t                sample_mask;
 258 };
 259
 260 struct si_streamout_target {
 261         struct pipe_stream_output_target b;
 262
 263         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 264         struct r600_resource    *buf_filled_size;
 265         unsigned                buf_filled_size_offset;
 266         bool                    buf_filled_size_valid;
 267
 268         unsigned                stride_in_dw;
 269 };
 270
 271 struct si_streamout {
 272         struct r600_atom                begin_atom;
 273         bool                            begin_emitted;
 274
 275         unsigned                        enabled_mask;
 276         unsigned                        num_targets;
 277         struct si_streamout_target      *targets[PIPE_MAX_SO_BUFFERS];
 278
 279         unsigned                        append_bitmask;
 280         bool                            suspended;
 281
 282         /* External state which comes from the vertex shader,
 283          * it must be set explicitly when binding a shader. */
 284         uint16_t                        *stride_in_dw;
 285         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 286
 287         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 288         unsigned                        hw_enabled_mask;
 289
 290         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 291         struct r600_atom                enable_atom;
 292         bool                            streamout_enabled;
 293         bool                            prims_gen_query_enabled;
 294         int                             num_prims_gen_queries;
 295 };
 296
 297 /* A shader state consists of the shader selector, which is a constant state
 298  * object shared by multiple contexts and shouldn't be modified, and
 299  * the current shader variant selected for this context.
 300  */
 301 struct si_shader_ctx_state {
 302         struct si_shader_selector       *cso;
 303         struct si_shader                *current;
 304 };
 305
 306 #define SI_NUM_VGT_PARAM_KEY_BITS 12
 307 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
 308
 309 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
 310  * Some fields are set by state-change calls, most are set by draw_vbo.
 311  */
 312 union si_vgt_param_key {
 313         struct {
 314                 unsigned prim:4;
 315                 unsigned uses_instancing:1;
 316                 unsigned multi_instances_smaller_than_primgroup:1;
 317                 unsigned primitive_restart:1;
 318                 unsigned count_from_stream_output:1;
 319                 unsigned line_stipple_enabled:1;
 320                 unsigned uses_tess:1;
 321                 unsigned tess_uses_prim_id:1;
 322                 unsigned uses_gs:1;
 323                 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
 324         } u;
 325         uint32_t index;
 326 };
 327
 328 struct si_texture_handle
 329 {
 330         unsigned                        desc_slot;
 331         bool                            desc_dirty;
 332         struct pipe_sampler_view        *view;
 333         struct si_sampler_state         sstate;
 334 };
 335
 336 struct si_image_handle
 337 {
 338         unsigned                        desc_slot;
 339         bool                            desc_dirty;
 340         struct pipe_image_view          view;
 341 };
 342
 343 struct si_saved_cs {
 344         struct pipe_reference   reference;
 345         struct si_context       *ctx;
 346         struct radeon_saved_cs  gfx;
 347         struct r600_resource    *trace_buf;
 348         unsigned                trace_id;
 349
 350         unsigned                gfx_last_dw;
 351         bool                    flushed;
 352         int64_t                 time_flush;
 353 };
 354
 355 struct si_context {
 356         struct r600_common_context      b;
 357         struct blitter_context          *blitter;
 358         void                            *custom_dsa_flush;
 359         void                            *custom_blend_resolve;
 360         void                            *custom_blend_fmask_decompress;
 361         void                            *custom_blend_eliminate_fastclear;
 362         void                            *custom_blend_dcc_decompress;
 363         void                            *vs_blit_pos;
 364         void                            *vs_blit_pos_layered;
 365         void                            *vs_blit_color;
 366         void                            *vs_blit_color_layered;
 367         void                            *vs_blit_texcoord;
 368         struct si_screen                *screen;
 369         struct pipe_debug_callback      debug;
 370         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 371         struct si_shader_ctx_state      fixed_func_tcs_shader;
 372         struct r600_resource            *wait_mem_scratch;
 373         unsigned                        wait_mem_number;
 374         uint16_t                        prefetch_L2_mask;
 375
 376         bool                            gfx_flush_in_progress:1;
 377         bool                            compute_is_busy:1;
 378
 379         /* Atoms (direct states). */
 380         union si_state_atoms            atoms;
 381         unsigned                        dirty_atoms; /* mask */
 382         /* PM4 states (precomputed immutable states) */
 383         unsigned                        dirty_states;
 384         union si_state                  queued;
 385         union si_state                  emitted;
 386
 387         /* Atom declarations. */
 388         struct si_framebuffer           framebuffer;
 389         struct si_sample_locs           msaa_sample_locs;
 390         struct r600_atom                db_render_state;
 391         struct r600_atom                dpbb_state;
 392         struct r600_atom                msaa_config;
 393         struct si_sample_mask           sample_mask;
 394         struct r600_atom                cb_render_state;
 395         unsigned                        last_cb_target_mask;
 396         struct si_blend_color           blend_color;
 397         struct r600_atom                clip_regs;
 398         struct si_clip_state            clip_state;
 399         struct si_shader_data           shader_pointers;
 400         struct si_stencil_ref           stencil_ref;
 401         struct r600_atom                spi_map;
 402         struct si_scissors              scissors;
 403         struct si_streamout             streamout;
 404         struct si_viewports             viewports;
 405
 406         /* Precomputed states. */
 407         struct si_pm4_state             *init_config;
 408         struct si_pm4_state             *init_config_gs_rings;
 409         bool                            init_config_has_vgt_flush;
 410         struct si_pm4_state             *vgt_shader_config[4];
 411
 412         /* shaders */
 413         struct si_shader_ctx_state      ps_shader;
 414         struct si_shader_ctx_state      gs_shader;
 415         struct si_shader_ctx_state      vs_shader;
 416         struct si_shader_ctx_state      tcs_shader;
 417         struct si_shader_ctx_state      tes_shader;
 418         struct si_cs_shader_state       cs_shader_state;
 419
 420         /* shader information */
 421         struct si_vertex_elements       *vertex_elements;
 422         unsigned                        sprite_coord_enable;
 423         bool                            flatshade;
 424         bool                            do_update_shaders;
 425
 426         /* shader descriptors */
 427         struct si_descriptors           vertex_buffers;
 428         struct si_descriptors           descriptors[SI_NUM_DESCS];
 429         unsigned                        descriptors_dirty;
 430         unsigned                        shader_pointers_dirty;
 431         unsigned                        shader_needs_decompress_mask;
 432         struct si_buffer_resources      rw_buffers;
 433         struct si_buffer_resources      const_and_shader_buffers[SI_NUM_SHADERS];
 434         struct si_samplers              samplers[SI_NUM_SHADERS];
 435         struct si_images                images[SI_NUM_SHADERS];
 436
 437         /* other shader resources */
 438         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 439         struct pipe_resource            *esgs_ring;
 440         struct pipe_resource            *gsvs_ring;
 441         struct pipe_resource            *tf_ring;
 442         struct pipe_resource            *tess_offchip_ring;
 443         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 444         struct r600_resource            *border_color_buffer;
 445         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 446         unsigned                        border_color_count;
 447         unsigned                        num_vs_blit_sgprs;
 448         uint32_t                        vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
 449
 450         /* Vertex and index buffers. */
 451         bool                            vertex_buffers_dirty;
 452         bool                            vertex_buffer_pointer_dirty;
 453         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 454
 455         /* MSAA config state. */
 456         int                             ps_iter_samples;
 457         bool                            smoothing_enabled;
 458
 459         /* DB render state. */
 460         unsigned                ps_db_shader_control;
 461         unsigned                dbcb_copy_sample;
 462         bool                    dbcb_depth_copy_enabled:1;
 463         bool                    dbcb_stencil_copy_enabled:1;
 464         bool                    db_flush_depth_inplace:1;
 465         bool                    db_flush_stencil_inplace:1;
 466         bool                    db_depth_clear:1;
 467         bool                    db_depth_disable_expclear:1;
 468         bool                    db_stencil_clear:1;
 469         bool                    db_stencil_disable_expclear:1;
 470         bool                    occlusion_queries_disabled:1;
 471         bool                    generate_mipmap_for_depth:1;
 472
 473         /* Emitted draw state. */
 474         bool                    gs_tri_strip_adj_fix:1;
 475         bool                    ls_vgpr_fix:1;
 476         int                     last_index_size;
 477         int                     last_base_vertex;
 478         int                     last_start_instance;
 479         int                     last_drawid;
 480         int                     last_sh_base_reg;
 481         int                     last_primitive_restart_en;
 482         int                     last_restart_index;
 483         int                     last_gs_out_prim;
 484         int                     last_prim;
 485         int                     last_multi_vgt_param;
 486         int                     last_rast_prim;
 487         unsigned                last_sc_line_stipple;
 488         unsigned                current_vs_state;
 489         unsigned                last_vs_state;
 490         enum pipe_prim_type     current_rast_prim; /* primitive type after TES, GS */
 491
 492         /* Scratch buffer */
 493         struct r600_atom        scratch_state;
 494         struct r600_resource    *scratch_buffer;
 495         unsigned                scratch_waves;
 496         unsigned                spi_tmpring_size;
 497
 498         struct r600_resource    *compute_scratch_buffer;
 499
 500         /* Emitted derived tessellation state. */
 501         /* Local shader (VS), or HS if LS-HS are merged. */
 502         struct si_shader        *last_ls;
 503         struct si_shader_selector *last_tcs;
 504         int                     last_num_tcs_input_cp;
 505         int                     last_tes_sh_base;
 506         bool                    last_tess_uses_primid;
 507         unsigned                last_num_patches;
 508
 509         /* Debug state. */
 510         bool                    is_debug;
 511         struct si_saved_cs      *current_saved_cs;
 512         uint64_t                dmesg_timestamp;
 513         unsigned                apitrace_call_number;
 514
 515         /* Other state */
 516         bool need_check_render_feedback;
 517         bool                    decompression_enabled;
 518
 519         bool                    vs_writes_viewport_index;
 520         bool                    vs_disables_clipping_viewport;
 521
 522         /* Precomputed IA_MULTI_VGT_PARAM */
 523         union si_vgt_param_key  ia_multi_vgt_param_key;
 524         unsigned                ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
 525
 526         /* Bindless descriptors. */
 527         struct si_descriptors   bindless_descriptors;
 528         struct util_idalloc     bindless_used_slots;
 529         unsigned                num_bindless_descriptors;
 530         bool                    bindless_descriptors_dirty;
 531         bool                    graphics_bindless_pointer_dirty;
 532         bool                    compute_bindless_pointer_dirty;
 533
 534         /* Allocated bindless handles */
 535         struct hash_table       *tex_handles;
 536         struct hash_table       *img_handles;
 537
 538         /* Resident bindless handles */
 539         struct util_dynarray    resident_tex_handles;
 540         struct util_dynarray    resident_img_handles;
 541
 542         /* Resident bindless handles which need decompression */
 543         struct util_dynarray    resident_tex_needs_color_decompress;
 544         struct util_dynarray    resident_img_needs_color_decompress;
 545         struct util_dynarray    resident_tex_needs_depth_decompress;
 546
 547         /* Bindless state */
 548         bool                    uses_bindless_samplers;
 549         bool                    uses_bindless_images;
 550
 551         /* MSAA sample locations.
 552          * The first index is the sample index.
 553          * The second index is the coordinate: X, Y. */
 554         float                   sample_locations_1x[1][2];
 555         float                   sample_locations_2x[2][2];
 556         float                   sample_locations_4x[4][2];
 557         float                   sample_locations_8x[8][2];
 558         float                   sample_locations_16x[16][2];
 559 };
 560
 561 /* cik_sdma.c */
 562 void cik_init_sdma_functions(struct si_context *sctx);
 563
 564 /* si_blit.c */
 565 enum si_blitter_op /* bitmask */
 566 {
 567         SI_SAVE_TEXTURES      = 1,
 568         SI_SAVE_FRAMEBUFFER   = 2,
 569         SI_SAVE_FRAGMENT_STATE = 4,
 570         SI_DISABLE_RENDER_COND = 8,
 571 };
 572
 573 void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op);
 574 void si_blitter_end(struct pipe_context *ctx);
 575 void si_init_blit_functions(struct si_context *sctx);
 576 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
 577 void si_resource_copy_region(struct pipe_context *ctx,
 578                              struct pipe_resource *dst,
 579                              unsigned dst_level,
 580                              unsigned dstx, unsigned dsty, unsigned dstz,
 581                              struct pipe_resource *src,
 582                              unsigned src_level,
 583                              const struct pipe_box *src_box);
 584
 585 /* si_clear.c */
 586 void vi_dcc_clear_level(struct si_context *sctx,
 587                         struct r600_texture *rtex,
 588                         unsigned level, unsigned clear_value);
 589 void si_init_clear_functions(struct si_context *sctx);
 590
 591 /* si_cp_dma.c */
 592 #define SI_CPDMA_SKIP_CHECK_CS_SPACE    (1 << 0) /* don't call need_cs_space */
 593 #define SI_CPDMA_SKIP_SYNC_AFTER        (1 << 1) /* don't wait for DMA after the copy */
 594 #define SI_CPDMA_SKIP_SYNC_BEFORE       (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
 595 #define SI_CPDMA_SKIP_GFX_SYNC          (1 << 3) /* don't flush caches and don't wait for PS/CS */
 596 #define SI_CPDMA_SKIP_BO_LIST_UPDATE    (1 << 4) /* don't update the BO list */
 597 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
 598                            SI_CPDMA_SKIP_SYNC_AFTER | \
 599                            SI_CPDMA_SKIP_SYNC_BEFORE | \
 600                            SI_CPDMA_SKIP_GFX_SYNC | \
 601                            SI_CPDMA_SKIP_BO_LIST_UPDATE)
 602
 603 enum r600_coherency {
 604         R600_COHERENCY_NONE, /* no cache flushes needed */
 605         R600_COHERENCY_SHADER,
 606         R600_COHERENCY_CB_META,
 607 };
 608
 609 void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
 610                      uint64_t offset, uint64_t size, unsigned value,
 611                      enum r600_coherency coher);
 612 void si_copy_buffer(struct si_context *sctx,
 613                     struct pipe_resource *dst, struct pipe_resource *src,
 614                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 615                     unsigned user_flags);
 616 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 617                               uint64_t offset, unsigned size);
 618 void cik_emit_prefetch_L2(struct si_context *sctx);
 619 void si_init_cp_dma_functions(struct si_context *sctx);
 620
 621 /* si_debug.c */
 622 void si_auto_log_cs(void *data, struct u_log_context *log);
 623 void si_log_hw_flush(struct si_context *sctx);
 624 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
 625 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
 626 void si_init_debug_functions(struct si_context *sctx);
 627 void si_check_vm_faults(struct r600_common_context *ctx,
 628                         struct radeon_saved_cs *saved, enum ring_type ring);
 629 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
 630
 631 /* si_dma.c */
 632 void si_init_dma_functions(struct si_context *sctx);
 633
 634 /* si_fence.c */
 635 void si_init_fence_functions(struct si_context *ctx);
 636 void si_init_screen_fence_functions(struct si_screen *screen);
 637 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
 638                                           struct tc_unflushed_batch_token *tc_token);
 639
 640 /* si_hw_context.c */
 641 void si_destroy_saved_cs(struct si_saved_cs *scs);
 642 void si_context_gfx_flush(void *context, unsigned flags,
 643                           struct pipe_fence_handle **fence);
 644 void si_begin_new_cs(struct si_context *ctx);
 645 void si_need_cs_space(struct si_context *ctx);
 646
 647 /* si_compute.c */
 648 void si_init_compute_functions(struct si_context *sctx);
 649
 650 /* si_perfcounters.c */
 651 void si_init_perfcounters(struct si_screen *screen);
 652
 653 /* si_test_dma.c */
 654 void si_test_dma(struct si_screen *sscreen);
 655
 656 /* si_uvd.c */
 657 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 658                                                const struct pipe_video_codec *templ);
 659
 660 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 661                                                  const struct pipe_video_buffer *tmpl);
 662
 663 /* si_viewport.c */
 664 void si_update_vs_viewport_state(struct si_context *ctx);
 665 void si_init_viewport_functions(struct si_context *ctx);
 666
 667
 668 /*
 669  * common helpers
 670  */
 671
 672 static inline void
 673 si_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 674 {
 675         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 676         struct r600_resource *res = (struct r600_resource *)r;
 677
 678         if (res) {
 679                 /* Add memory usage for need_gfx_cs_space */
 680                 rctx->vram += res->vram_usage;
 681                 rctx->gtt += res->gart_usage;
 682         }
 683 }
 684
 685 static inline void
 686 si_invalidate_draw_sh_constants(struct si_context *sctx)
 687 {
 688         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 689 }
 690
 691 static inline void
 692 si_set_atom_dirty(struct si_context *sctx,
 693                   struct r600_atom *atom, bool dirty)
 694 {
 695         unsigned bit = 1 << atom->id;
 696
 697         if (dirty)
 698                 sctx->dirty_atoms |= bit;
 699         else
 700                 sctx->dirty_atoms &= ~bit;
 701 }
 702
 703 static inline bool
 704 si_is_atom_dirty(struct si_context *sctx,
 705                   struct r600_atom *atom)
 706 {
 707         unsigned bit = 1 << atom->id;
 708
 709         return sctx->dirty_atoms & bit;
 710 }
 711
 712 static inline void
 713 si_mark_atom_dirty(struct si_context *sctx,
 714                    struct r600_atom *atom)
 715 {
 716         si_set_atom_dirty(sctx, atom, true);
 717 }
 718
 719 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
 720 {
 721         if (sctx->gs_shader.cso)
 722                 return &sctx->gs_shader;
 723         if (sctx->tes_shader.cso)
 724                 return &sctx->tes_shader;
 725
 726         return &sctx->vs_shader;
 727 }
 728
 729 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 730 {
 731         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 732
 733         return vs->cso ? &vs->cso->info : NULL;
 734 }
 735
 736 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 737 {
 738         if (sctx->gs_shader.cso)
 739                 return sctx->gs_shader.cso->gs_copy_shader;
 740
 741         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 742         return vs->current ? vs->current : NULL;
 743 }
 744
 745 static inline bool si_get_strmout_en(struct si_context *sctx)
 746 {
 747         return sctx->streamout.streamout_enabled ||
 748                sctx->streamout.prims_gen_query_enabled;
 749 }
 750
 751 static inline unsigned
 752 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
 753 {
 754         unsigned alignment, tcc_cache_line_size;
 755
 756         /* If the upload size is less than the cache line size (e.g. 16, 32),
 757          * the whole thing will fit into a cache line if we align it to its size.
 758          * The idea is that multiple small uploads can share a cache line.
 759          * If the upload size is greater, align it to the cache line size.
 760          */
 761         alignment = util_next_power_of_two(upload_size);
 762         tcc_cache_line_size = sctx->screen->b.info.tcc_cache_line_size;
 763         return MIN2(alignment, tcc_cache_line_size);
 764 }
 765
 766 static inline void
 767 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
 768 {
 769         if (pipe_reference(&(*dst)->reference, &src->reference))
 770                 si_destroy_saved_cs(*dst);
 771
 772         *dst = src;
 773 }
 774
 775 static inline void
 776 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 777                            bool shaders_read_metadata)
 778 {
 779         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
 780                          SI_CONTEXT_INV_VMEM_L1;
 781
 782         if (sctx->b.chip_class >= GFX9) {
 783                 /* Single-sample color is coherent with shaders on GFX9, but
 784                  * L2 metadata must be flushed if shaders read metadata.
 785                  * (DCC, CMASK).
 786                  */
 787                 if (num_samples >= 2)
 788                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 789                 else if (shaders_read_metadata)
 790                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 791         } else {
 792                 /* SI-CI-VI */
 793                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 794         }
 795 }
 796
 797 static inline void
 798 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 799                            bool include_stencil, bool shaders_read_metadata)
 800 {
 801         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
 802                          SI_CONTEXT_INV_VMEM_L1;
 803
 804         if (sctx->b.chip_class >= GFX9) {
 805                 /* Single-sample depth (not stencil) is coherent with shaders
 806                  * on GFX9, but L2 metadata must be flushed if shaders read
 807                  * metadata.
 808                  */
 809                 if (num_samples >= 2 || include_stencil)
 810                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 811                 else if (shaders_read_metadata)
 812                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 813         } else {
 814                 /* SI-CI-VI */
 815                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 816         }
 817 }
 818
 819 static inline bool
 820 si_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
 821 {
 822         return (stencil_sampler && tex->can_sample_s) ||
 823                (!stencil_sampler && tex->can_sample_z);
 824 }
 825
 826 static inline bool
 827 si_htile_enabled(struct r600_texture *tex, unsigned level)
 828 {
 829         return tex->htile_offset && level == 0;
 830 }
 831
 832 static inline bool
 833 vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level)
 834 {
 835         assert(!tex->tc_compatible_htile || tex->htile_offset);
 836         return tex->tc_compatible_htile && level == 0;
 837 }
 838
 839 #endif