src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef SI_PIPE_H
  27 #define SI_PIPE_H
  28
  29 #include "si_state.h"
  30
  31 #include <llvm-c/TargetMachine.h>
  32
  33 #ifdef PIPE_ARCH_BIG_ENDIAN
  34 #define SI_BIG_ENDIAN 1
  35 #else
  36 #define SI_BIG_ENDIAN 0
  37 #endif
  38
  39 /* The base vertex and primitive restart can be any number, but we must pick
  40  * one which will mean "unknown" for the purpose of state tracking and
  41  * the number shouldn't be a commonly-used one. */
  42 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  43 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  44 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  45 #define SI_GS_PER_ES 128
  46
  47 /* Instruction cache. */
  48 #define SI_CONTEXT_INV_ICACHE           (R600_CONTEXT_PRIVATE_FLAG << 0)
  49 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  50 #define SI_CONTEXT_INV_SMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 1)
  51 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  52 #define SI_CONTEXT_INV_VMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 2)
  53 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  54 #define SI_CONTEXT_INV_GLOBAL_L2        (R600_CONTEXT_PRIVATE_FLAG << 3)
  55 /* Framebuffer caches. */
  56 #define SI_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
  57 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
  58 #define SI_CONTEXT_FLUSH_AND_INV_DB     (R600_CONTEXT_PRIVATE_FLAG << 6)
  59 #define SI_CONTEXT_FLUSH_AND_INV_CB     (R600_CONTEXT_PRIVATE_FLAG << 7)
  60 /* Engine synchronization. */
  61 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 8)
  62 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 9)
  63 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 10)
  64 #define SI_CONTEXT_VGT_FLUSH            (R600_CONTEXT_PRIVATE_FLAG << 11)
  65 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (R600_CONTEXT_PRIVATE_FLAG << 12)
  66
  67 #define SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER (SI_CONTEXT_FLUSH_AND_INV_CB | \
  68                                               SI_CONTEXT_FLUSH_AND_INV_CB_META | \
  69                                               SI_CONTEXT_FLUSH_AND_INV_DB | \
  70                                               SI_CONTEXT_FLUSH_AND_INV_DB_META)
  71
  72 #define SI_ENCODE_TRACE_POINT(id)       (0xcafe0000 | ((id) & 0xffff))
  73 #define SI_IS_TRACE_POINT(x)            (((x) & 0xcafe0000) == 0xcafe0000)
  74 #define SI_GET_TRACE_POINT_ID(x)        ((x) & 0xffff)
  75
  76 #define SI_MAX_BORDER_COLORS    4096
  77
  78 struct si_compute;
  79 struct hash_table;
  80 struct u_suballocator;
  81
  82 struct si_screen {
  83         struct r600_common_screen       b;
  84         unsigned                        gs_table_depth;
  85
  86         /* Whether shaders are monolithic (1-part) or separate (3-part). */
  87         bool                            use_monolithic_shaders;
  88
  89         pipe_mutex                      shader_parts_mutex;
  90         struct si_shader_part           *vs_prologs;
  91         struct si_shader_part           *vs_epilogs;
  92         struct si_shader_part           *tcs_epilogs;
  93         struct si_shader_part           *ps_prologs;
  94         struct si_shader_part           *ps_epilogs;
  95
  96         /* Shader cache in memory.
  97          *
  98          * Design & limitations:
  99          * - The shader cache is per screen (= per process), never saved to
 100          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 101          * - It can only be used with one-variant-per-shader support, in which
 102          *   case only the main (typically middle) part of shaders is cached.
 103          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 104          *   variants of VS and TES are cached, so LS and ES aren't.
 105          * - GS and CS aren't cached, but it's certainly possible to cache
 106          *   those as well.
 107          */
 108         pipe_mutex                      shader_cache_mutex;
 109         struct hash_table               *shader_cache;
 110 };
 111
 112 struct si_blend_color {
 113         struct r600_atom                atom;
 114         struct pipe_blend_color         state;
 115 };
 116
 117 struct si_sampler_view {
 118         struct pipe_sampler_view        base;
 119         struct list_head                list;
 120         /* [0..7] = image descriptor
 121          * [4..7] = buffer descriptor */
 122         uint32_t                        state[8];
 123         uint32_t                        fmask_state[8];
 124         const struct radeon_surf_level  *base_level_info;
 125         unsigned                        base_level;
 126         unsigned                        block_width;
 127         bool is_stencil_sampler;
 128 };
 129
 130 struct si_sampler_state {
 131         uint32_t                        val[4];
 132 };
 133
 134 struct si_cs_shader_state {
 135         struct si_compute               *program;
 136         struct si_compute               *emitted_program;
 137         unsigned                        offset;
 138         bool                            initialized;
 139         bool                            uses_scratch;
 140 };
 141
 142 struct si_textures_info {
 143         struct si_sampler_views         views;
 144         uint32_t                        depth_texture_mask; /* which textures are depth */
 145         uint32_t                        compressed_colortex_mask;
 146 };
 147
 148 struct si_images_info {
 149         struct pipe_image_view          views[SI_NUM_IMAGES];
 150         uint32_t                        compressed_colortex_mask;
 151         unsigned                        enabled_mask;
 152 };
 153
 154 struct si_framebuffer {
 155         struct r600_atom                atom;
 156         struct pipe_framebuffer_state   state;
 157         unsigned                        nr_samples;
 158         unsigned                        log_samples;
 159         unsigned                        cb0_is_integer;
 160         unsigned                        compressed_cb_mask;
 161         unsigned                        spi_shader_col_format;
 162         unsigned                        spi_shader_col_format_alpha;
 163         unsigned                        spi_shader_col_format_blend;
 164         unsigned                        spi_shader_col_format_blend_alpha;
 165         unsigned                        color_is_int8; /* bitmask */
 166         unsigned                        dirty_cbufs;
 167         bool                            dirty_zsbuf;
 168         bool                            any_dst_linear;
 169 };
 170
 171 struct si_clip_state {
 172         struct r600_atom                atom;
 173         struct pipe_clip_state          state;
 174 };
 175
 176 struct si_sample_mask {
 177         struct r600_atom        atom;
 178         uint16_t                sample_mask;
 179 };
 180
 181 /* A shader state consists of the shader selector, which is a constant state
 182  * object shared by multiple contexts and shouldn't be modified, and
 183  * the current shader variant selected for this context.
 184  */
 185 struct si_shader_ctx_state {
 186         struct si_shader_selector       *cso;
 187         struct si_shader                *current;
 188 };
 189
 190 struct si_context {
 191         struct r600_common_context      b;
 192         struct blitter_context          *blitter;
 193         void                            *custom_dsa_flush;
 194         void                            *custom_blend_resolve;
 195         void                            *custom_blend_decompress;
 196         void                            *custom_blend_fastclear;
 197         void                            *custom_blend_dcc_decompress;
 198         struct si_screen                *screen;
 199
 200         struct radeon_winsys_cs         *ce_ib;
 201         struct radeon_winsys_cs         *ce_preamble_ib;
 202         bool                            ce_need_synchronization;
 203         struct u_suballocator           *ce_suballocator;
 204
 205         struct pipe_fence_handle        *last_gfx_fence;
 206         struct si_shader_ctx_state      fixed_func_tcs_shader;
 207         LLVMTargetMachineRef            tm;
 208         bool                            gfx_flush_in_progress;
 209
 210         /* Atoms (direct states). */
 211         union si_state_atoms            atoms;
 212         unsigned                        dirty_atoms; /* mask */
 213         /* PM4 states (precomputed immutable states) */
 214         union si_state                  queued;
 215         union si_state                  emitted;
 216
 217         /* Atom declarations. */
 218         struct r600_atom                cache_flush;
 219         struct si_framebuffer           framebuffer;
 220         struct r600_atom                msaa_sample_locs;
 221         struct r600_atom                db_render_state;
 222         struct r600_atom                msaa_config;
 223         struct si_sample_mask           sample_mask;
 224         struct r600_atom                cb_render_state;
 225         struct si_blend_color           blend_color;
 226         struct r600_atom                clip_regs;
 227         struct si_clip_state            clip_state;
 228         struct si_shader_data           shader_userdata;
 229         struct si_stencil_ref           stencil_ref;
 230         struct r600_atom                spi_map;
 231
 232         /* Precomputed states. */
 233         struct si_pm4_state             *init_config;
 234         struct si_pm4_state             *init_config_gs_rings;
 235         bool                            init_config_has_vgt_flush;
 236         struct si_pm4_state             *vgt_shader_config[4];
 237
 238         /* shaders */
 239         struct si_shader_ctx_state      ps_shader;
 240         struct si_shader_ctx_state      gs_shader;
 241         struct si_shader_ctx_state      vs_shader;
 242         struct si_shader_ctx_state      tcs_shader;
 243         struct si_shader_ctx_state      tes_shader;
 244         struct si_cs_shader_state       cs_shader_state;
 245
 246         /* shader information */
 247         struct si_vertex_element        *vertex_elements;
 248         unsigned                        sprite_coord_enable;
 249         bool                            flatshade;
 250
 251         /* shader descriptors */
 252         struct si_descriptors           vertex_buffers;
 253         struct si_descriptors           descriptors[SI_NUM_DESCS];
 254         unsigned                        descriptors_dirty;
 255         struct si_buffer_resources      rw_buffers;
 256         struct si_buffer_resources      const_buffers[SI_NUM_SHADERS];
 257         struct si_buffer_resources      shader_buffers[SI_NUM_SHADERS];
 258         struct si_textures_info         samplers[SI_NUM_SHADERS];
 259         struct si_images_info           images[SI_NUM_SHADERS];
 260
 261         /* other shader resources */
 262         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 263         struct pipe_resource            *esgs_ring;
 264         struct pipe_resource            *gsvs_ring;
 265         struct pipe_resource            *tf_ring;
 266         struct pipe_resource            *tess_offchip_ring;
 267         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 268         struct r600_resource            *border_color_buffer;
 269         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 270         unsigned                        border_color_count;
 271
 272         /* Vertex and index buffers. */
 273         bool                            vertex_buffers_dirty;
 274         struct pipe_index_buffer        index_buffer;
 275         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 276
 277         /* MSAA config state. */
 278         int                             ps_iter_samples;
 279         bool                            smoothing_enabled;
 280
 281         /* DB render state. */
 282         bool                    dbcb_depth_copy_enabled;
 283         bool                    dbcb_stencil_copy_enabled;
 284         unsigned                dbcb_copy_sample;
 285         bool                    db_flush_depth_inplace;
 286         bool                    db_flush_stencil_inplace;
 287         bool                    db_depth_clear;
 288         bool                    db_depth_disable_expclear;
 289         bool                    db_stencil_clear;
 290         bool                    db_stencil_disable_expclear;
 291         unsigned                ps_db_shader_control;
 292         bool                    occlusion_queries_disabled;
 293
 294         /* Emitted draw state. */
 295         int                     last_base_vertex;
 296         int                     last_start_instance;
 297         int                     last_sh_base_reg;
 298         int                     last_primitive_restart_en;
 299         int                     last_restart_index;
 300         int                     last_gs_out_prim;
 301         int                     last_prim;
 302         int                     last_multi_vgt_param;
 303         int                     last_ls_hs_config;
 304         int                     last_rast_prim;
 305         unsigned                last_sc_line_stipple;
 306         int                     last_vtx_reuse_depth;
 307         int                     current_rast_prim; /* primitive type after TES, GS */
 308         unsigned                last_gsvs_itemsize;
 309
 310         /* Scratch buffer */
 311         struct r600_resource    *scratch_buffer;
 312         boolean                 emit_scratch_reloc;
 313         unsigned                scratch_waves;
 314         unsigned                spi_tmpring_size;
 315
 316         struct r600_resource    *compute_scratch_buffer;
 317
 318         /* Emitted derived tessellation state. */
 319         struct si_shader        *last_ls; /* local shader (VS) */
 320         struct si_shader_selector *last_tcs;
 321         int                     last_num_tcs_input_cp;
 322         int                     last_tes_sh_base;
 323
 324         /* Debug state. */
 325         bool                    is_debug;
 326         struct radeon_saved_cs  last_gfx;
 327         struct r600_resource    *last_trace_buf;
 328         struct r600_resource    *trace_buf;
 329         unsigned                trace_id;
 330         uint64_t                dmesg_timestamp;
 331
 332         /* Other state */
 333         bool need_check_render_feedback;
 334 };
 335
 336 /* cik_sdma.c */
 337 void cik_init_sdma_functions(struct si_context *sctx);
 338
 339 /* si_blit.c */
 340 void si_init_blit_functions(struct si_context *sctx);
 341 void si_decompress_graphics_textures(struct si_context *sctx);
 342 void si_decompress_compute_textures(struct si_context *sctx);
 343 void si_resource_copy_region(struct pipe_context *ctx,
 344                              struct pipe_resource *dst,
 345                              unsigned dst_level,
 346                              unsigned dstx, unsigned dsty, unsigned dstz,
 347                              struct pipe_resource *src,
 348                              unsigned src_level,
 349                              const struct pipe_box *src_box);
 350
 351 /* si_cp_dma.c */
 352 void si_copy_buffer(struct si_context *sctx,
 353                     struct pipe_resource *dst, struct pipe_resource *src,
 354                     uint64_t dst_offset, uint64_t src_offset, unsigned size);
 355 void si_init_cp_dma_functions(struct si_context *sctx);
 356
 357 /* si_debug.c */
 358 void si_init_debug_functions(struct si_context *sctx);
 359 void si_check_vm_faults(struct r600_common_context *ctx,
 360                         struct radeon_saved_cs *saved, enum ring_type ring);
 361 bool si_replace_shader(unsigned num, struct radeon_shader_binary *binary);
 362
 363 /* si_dma.c */
 364 void si_init_dma_functions(struct si_context *sctx);
 365
 366 /* si_hw_context.c */
 367 void si_context_gfx_flush(void *context, unsigned flags,
 368                           struct pipe_fence_handle **fence);
 369 void si_begin_new_cs(struct si_context *ctx);
 370 void si_need_cs_space(struct si_context *ctx);
 371
 372 /* si_compute.c */
 373 void si_init_compute_functions(struct si_context *sctx);
 374
 375 /* si_perfcounters.c */
 376 void si_init_perfcounters(struct si_screen *screen);
 377
 378 /* si_uvd.c */
 379 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 380                                                const struct pipe_video_codec *templ);
 381
 382 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 383                                                  const struct pipe_video_buffer *tmpl);
 384
 385 /*
 386  * common helpers
 387  */
 388
 389 static inline struct r600_resource *
 390 si_resource_create_custom(struct pipe_screen *screen,
 391                           unsigned usage, unsigned size)
 392 {
 393         assert(size);
 394         return r600_resource(pipe_buffer_create(screen,
 395                 PIPE_BIND_CUSTOM, usage, size));
 396 }
 397
 398 static inline void
 399 si_invalidate_draw_sh_constants(struct si_context *sctx)
 400 {
 401         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 402         sctx->last_start_instance = -1; /* reset to an unknown value */
 403         sctx->last_sh_base_reg = -1; /* reset to an unknown value */
 404 }
 405
 406 static inline void
 407 si_set_atom_dirty(struct si_context *sctx,
 408                   struct r600_atom *atom, bool dirty)
 409 {
 410         unsigned bit = 1 << (atom->id - 1);
 411
 412         if (dirty)
 413                 sctx->dirty_atoms |= bit;
 414         else
 415                 sctx->dirty_atoms &= ~bit;
 416 }
 417
 418 static inline bool
 419 si_is_atom_dirty(struct si_context *sctx,
 420                   struct r600_atom *atom)
 421 {
 422         unsigned bit = 1 << (atom->id - 1);
 423
 424         return sctx->dirty_atoms & bit;
 425 }
 426
 427 static inline void
 428 si_mark_atom_dirty(struct si_context *sctx,
 429                    struct r600_atom *atom)
 430 {
 431         si_set_atom_dirty(sctx, atom, true);
 432 }
 433
 434 #endif