2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "si_shader.h"
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
34 #ifdef PIPE_ARCH_BIG_ENDIAN
35 #define SI_BIG_ENDIAN 1
37 #define SI_BIG_ENDIAN 0
40 /* The base vertex and primitive restart can be any number, but we must pick
41 * one which will mean "unknown" for the purpose of state tracking and
42 * the number shouldn't be a commonly-used one. */
43 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
44 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
45 #define SI_NUM_SMOOTH_AA_SAMPLES 8
46 #define SI_GS_PER_ES 128
47 /* Alignment for optimal CP DMA performance. */
48 #define SI_CPDMA_ALIGNMENT 32
50 /* Instruction cache. */
51 #define SI_CONTEXT_INV_ICACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
52 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
53 #define SI_CONTEXT_INV_SMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 1)
54 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
55 #define SI_CONTEXT_INV_VMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 2)
56 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
57 #define SI_CONTEXT_INV_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 3)
58 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
59 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
60 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 4)
61 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
62 * a CB or DB flush. */
63 #define SI_CONTEXT_INV_L2_METADATA (R600_CONTEXT_PRIVATE_FLAG << 5)
65 /* Framebuffer caches. */
66 #define SI_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 7)
67 #define SI_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 8)
68 /* Engine synchronization. */
69 #define SI_CONTEXT_VS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 9)
70 #define SI_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 10)
71 #define SI_CONTEXT_CS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 11)
72 #define SI_CONTEXT_VGT_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 12)
73 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (R600_CONTEXT_PRIVATE_FLAG << 13)
75 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
76 #define SI_PREFETCH_LS (1 << 1)
77 #define SI_PREFETCH_HS (1 << 2)
78 #define SI_PREFETCH_ES (1 << 3)
79 #define SI_PREFETCH_GS (1 << 4)
80 #define SI_PREFETCH_VS (1 << 5)
81 #define SI_PREFETCH_PS (1 << 6)
83 #define SI_MAX_BORDER_COLORS 4096
88 struct u_suballocator
;
91 struct r600_common_screen b
;
92 unsigned gs_table_depth
;
93 unsigned tess_offchip_block_dw_size
;
95 bool has_distributed_tess
;
96 bool has_draw_indirect_multi
;
98 bool has_msaa_sample_loc_bug
;
100 bool llvm_has_working_vgpr_indexing
;
102 /* Whether shaders are monolithic (1-part) or separate (3-part). */
103 bool use_monolithic_shaders
;
106 mtx_t shader_parts_mutex
;
107 struct si_shader_part
*vs_prologs
;
108 struct si_shader_part
*tcs_epilogs
;
109 struct si_shader_part
*gs_prologs
;
110 struct si_shader_part
*ps_prologs
;
111 struct si_shader_part
*ps_epilogs
;
113 /* Shader cache in memory.
115 * Design & limitations:
116 * - The shader cache is per screen (= per process), never saved to
117 * disk, and skips redundant shader compilations from TGSI to bytecode.
118 * - It can only be used with one-variant-per-shader support, in which
119 * case only the main (typically middle) part of shaders is cached.
120 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
121 * variants of VS and TES are cached, so LS and ES aren't.
122 * - GS and CS aren't cached, but it's certainly possible to cache
125 mtx_t shader_cache_mutex
;
126 struct hash_table
*shader_cache
;
128 /* Shader compiler queue for multithreaded compilation. */
129 struct util_queue shader_compiler_queue
;
130 /* Use at most 3 normal compiler threads on quadcore and better.
131 * Hyperthreaded CPUs report the number of threads, but we want
132 * the number of cores. */
133 LLVMTargetMachineRef tm
[3]; /* used by the queue only */
135 struct util_queue shader_compiler_queue_low_priority
;
136 /* Use at most 2 low priority threads on quadcore and better.
137 * We want to minimize the impact on multithreaded Mesa. */
138 LLVMTargetMachineRef tm_low_priority
[2]; /* at most 2 threads */
141 struct si_blend_color
{
142 struct r600_atom atom
;
143 struct pipe_blend_color state
;
147 struct si_sampler_view
{
148 struct pipe_sampler_view base
;
149 /* [0..7] = image descriptor
150 * [4..7] = buffer descriptor */
152 uint32_t fmask_state
[8];
153 const struct legacy_surf_level
*base_level_info
;
156 bool is_stencil_sampler
;
157 bool dcc_incompatible
;
160 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
162 struct si_sampler_state
{
169 struct si_cs_shader_state
{
170 struct si_compute
*program
;
171 struct si_compute
*emitted_program
;
177 struct si_textures_info
{
178 struct si_sampler_views views
;
179 uint32_t needs_depth_decompress_mask
;
180 uint32_t needs_color_decompress_mask
;
183 struct si_images_info
{
184 struct pipe_image_view views
[SI_NUM_IMAGES
];
185 uint32_t needs_color_decompress_mask
;
186 unsigned enabled_mask
;
189 struct si_framebuffer
{
190 struct r600_atom atom
;
191 struct pipe_framebuffer_state state
;
192 unsigned colorbuf_enabled_4bit
;
193 unsigned spi_shader_col_format
;
194 unsigned spi_shader_col_format_alpha
;
195 unsigned spi_shader_col_format_blend
;
196 unsigned spi_shader_col_format_blend_alpha
;
197 ubyte nr_samples
:5; /* at most 16xAA */
198 ubyte log_samples
:3; /* at most 4 = 16xAA */
199 ubyte compressed_cb_mask
;
201 ubyte color_is_int10
;
205 bool CB_has_shader_readable_metadata
;
206 bool DB_has_shader_readable_metadata
;
209 struct si_clip_state
{
210 struct r600_atom atom
;
211 struct pipe_clip_state state
;
215 struct si_sample_locs
{
216 struct r600_atom atom
;
220 struct si_sample_mask
{
221 struct r600_atom atom
;
222 uint16_t sample_mask
;
225 /* A shader state consists of the shader selector, which is a constant state
226 * object shared by multiple contexts and shouldn't be modified, and
227 * the current shader variant selected for this context.
229 struct si_shader_ctx_state
{
230 struct si_shader_selector
*cso
;
231 struct si_shader
*current
;
234 #define SI_NUM_VGT_PARAM_KEY_BITS 12
235 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
237 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
238 * Some fields are set by state-change calls, most are set by draw_vbo.
240 union si_vgt_param_key
{
243 unsigned uses_instancing
:1;
244 unsigned multi_instances_smaller_than_primgroup
:1;
245 unsigned primitive_restart
:1;
246 unsigned count_from_stream_output
:1;
247 unsigned line_stipple_enabled
:1;
248 unsigned uses_tess
:1;
249 unsigned tess_uses_prim_id
:1;
251 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
256 struct si_texture_handle
260 struct pipe_sampler_view
*view
;
261 struct si_sampler_state sstate
;
264 struct si_image_handle
268 struct pipe_image_view view
;
272 struct pipe_reference reference
;
273 struct si_context
*ctx
;
274 struct radeon_saved_cs gfx
;
275 struct r600_resource
*trace_buf
;
278 unsigned gfx_last_dw
;
283 struct r600_common_context b
;
284 struct blitter_context
*blitter
;
285 void *custom_dsa_flush
;
286 void *custom_blend_resolve
;
287 void *custom_blend_fmask_decompress
;
288 void *custom_blend_eliminate_fastclear
;
289 void *custom_blend_dcc_decompress
;
290 struct si_screen
*screen
;
291 LLVMTargetMachineRef tm
; /* only non-threaded compilation */
292 struct si_shader_ctx_state fixed_func_tcs_shader
;
293 struct r600_resource
*wait_mem_scratch
;
294 unsigned wait_mem_number
;
295 uint16_t prefetch_L2_mask
;
297 bool gfx_flush_in_progress
:1;
298 bool compute_is_busy
:1;
300 /* Atoms (direct states). */
301 union si_state_atoms atoms
;
302 unsigned dirty_atoms
; /* mask */
303 /* PM4 states (precomputed immutable states) */
304 unsigned dirty_states
;
305 union si_state queued
;
306 union si_state emitted
;
308 /* Atom declarations. */
309 struct si_framebuffer framebuffer
;
310 struct si_sample_locs msaa_sample_locs
;
311 struct r600_atom db_render_state
;
312 struct r600_atom msaa_config
;
313 struct si_sample_mask sample_mask
;
314 struct r600_atom cb_render_state
;
315 unsigned last_cb_target_mask
;
316 struct si_blend_color blend_color
;
317 struct r600_atom clip_regs
;
318 struct si_clip_state clip_state
;
319 struct si_shader_data shader_pointers
;
320 struct si_stencil_ref stencil_ref
;
321 struct r600_atom spi_map
;
323 /* Precomputed states. */
324 struct si_pm4_state
*init_config
;
325 struct si_pm4_state
*init_config_gs_rings
;
326 bool init_config_has_vgt_flush
;
327 struct si_pm4_state
*vgt_shader_config
[4];
330 struct si_shader_ctx_state ps_shader
;
331 struct si_shader_ctx_state gs_shader
;
332 struct si_shader_ctx_state vs_shader
;
333 struct si_shader_ctx_state tcs_shader
;
334 struct si_shader_ctx_state tes_shader
;
335 struct si_cs_shader_state cs_shader_state
;
337 /* shader information */
338 struct si_vertex_elements
*vertex_elements
;
339 unsigned sprite_coord_enable
;
341 bool do_update_shaders
;
343 /* shader descriptors */
344 struct si_descriptors vertex_buffers
;
345 struct si_descriptors descriptors
[SI_NUM_DESCS
];
346 unsigned descriptors_dirty
;
347 unsigned shader_pointers_dirty
;
348 unsigned shader_needs_decompress_mask
;
349 struct si_buffer_resources rw_buffers
;
350 struct si_buffer_resources const_and_shader_buffers
[SI_NUM_SHADERS
];
351 struct si_textures_info samplers
[SI_NUM_SHADERS
];
352 struct si_images_info images
[SI_NUM_SHADERS
];
354 /* other shader resources */
355 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on CIK */
356 struct pipe_resource
*esgs_ring
;
357 struct pipe_resource
*gsvs_ring
;
358 struct pipe_resource
*tf_ring
;
359 struct pipe_resource
*tess_offchip_ring
;
360 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
361 struct r600_resource
*border_color_buffer
;
362 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
363 unsigned border_color_count
;
365 /* Vertex and index buffers. */
366 bool vertex_buffers_dirty
;
367 bool vertex_buffer_pointer_dirty
;
368 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
370 /* MSAA config state. */
372 bool smoothing_enabled
;
374 /* DB render state. */
375 unsigned ps_db_shader_control
;
376 unsigned dbcb_copy_sample
;
377 bool dbcb_depth_copy_enabled
:1;
378 bool dbcb_stencil_copy_enabled
:1;
379 bool db_flush_depth_inplace
:1;
380 bool db_flush_stencil_inplace
:1;
381 bool db_depth_clear
:1;
382 bool db_depth_disable_expclear
:1;
383 bool db_stencil_clear
:1;
384 bool db_stencil_disable_expclear
:1;
385 bool occlusion_queries_disabled
:1;
386 bool generate_mipmap_for_depth
:1;
388 /* Emitted draw state. */
389 bool gs_tri_strip_adj_fix
:1;
391 int last_base_vertex
;
392 int last_start_instance
;
394 int last_sh_base_reg
;
395 int last_primitive_restart_en
;
396 int last_restart_index
;
397 int last_gs_out_prim
;
399 int last_multi_vgt_param
;
401 unsigned last_sc_line_stipple
;
402 unsigned current_vs_state
;
403 unsigned last_vs_state
;
404 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
407 struct r600_atom scratch_state
;
408 struct r600_resource
*scratch_buffer
;
409 unsigned scratch_waves
;
410 unsigned spi_tmpring_size
;
412 struct r600_resource
*compute_scratch_buffer
;
414 /* Emitted derived tessellation state. */
415 /* Local shader (VS), or HS if LS-HS are merged. */
416 struct si_shader
*last_ls
;
417 struct si_shader_selector
*last_tcs
;
418 int last_num_tcs_input_cp
;
419 int last_tes_sh_base
;
420 bool last_tess_uses_primid
;
421 unsigned last_num_patches
;
425 struct si_saved_cs
*current_saved_cs
;
426 uint64_t dmesg_timestamp
;
427 unsigned apitrace_call_number
;
430 bool need_check_render_feedback
;
431 bool decompression_enabled
;
433 /* Precomputed IA_MULTI_VGT_PARAM */
434 union si_vgt_param_key ia_multi_vgt_param_key
;
435 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
437 /* Bindless descriptors. */
438 struct si_descriptors bindless_descriptors
;
439 struct util_idalloc bindless_used_slots
;
440 unsigned num_bindless_descriptors
;
441 bool bindless_descriptors_dirty
;
442 bool graphics_bindless_pointer_dirty
;
443 bool compute_bindless_pointer_dirty
;
445 /* Allocated bindless handles */
446 struct hash_table
*tex_handles
;
447 struct hash_table
*img_handles
;
449 /* Resident bindless handles */
450 struct util_dynarray resident_tex_handles
;
451 struct util_dynarray resident_img_handles
;
453 /* Resident bindless handles which need decompression */
454 struct util_dynarray resident_tex_needs_color_decompress
;
455 struct util_dynarray resident_img_needs_color_decompress
;
456 struct util_dynarray resident_tex_needs_depth_decompress
;
459 bool uses_bindless_samplers
;
460 bool uses_bindless_images
;
464 void cik_init_sdma_functions(struct si_context
*sctx
);
467 void si_init_blit_functions(struct si_context
*sctx
);
468 void si_decompress_graphics_textures(struct si_context
*sctx
);
469 void si_decompress_compute_textures(struct si_context
*sctx
);
470 void si_resource_copy_region(struct pipe_context
*ctx
,
471 struct pipe_resource
*dst
,
473 unsigned dstx
, unsigned dsty
, unsigned dstz
,
474 struct pipe_resource
*src
,
476 const struct pipe_box
*src_box
);
479 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
480 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
481 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
482 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
483 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
484 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
485 SI_CPDMA_SKIP_SYNC_AFTER | \
486 SI_CPDMA_SKIP_SYNC_BEFORE | \
487 SI_CPDMA_SKIP_GFX_SYNC | \
488 SI_CPDMA_SKIP_BO_LIST_UPDATE)
490 void si_copy_buffer(struct si_context
*sctx
,
491 struct pipe_resource
*dst
, struct pipe_resource
*src
,
492 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
493 unsigned user_flags
);
494 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
495 uint64_t offset
, unsigned size
);
496 void cik_emit_prefetch_L2(struct si_context
*sctx
);
497 void si_init_cp_dma_functions(struct si_context
*sctx
);
500 void si_auto_log_cs(void *data
, struct u_log_context
*log
);
501 void si_log_hw_flush(struct si_context
*sctx
);
502 void si_log_draw_state(struct si_context
*sctx
, struct u_log_context
*log
);
503 void si_log_compute_state(struct si_context
*sctx
, struct u_log_context
*log
);
504 void si_init_debug_functions(struct si_context
*sctx
);
505 void si_check_vm_faults(struct r600_common_context
*ctx
,
506 struct radeon_saved_cs
*saved
, enum ring_type ring
);
507 bool si_replace_shader(unsigned num
, struct ac_shader_binary
*binary
);
510 void si_init_dma_functions(struct si_context
*sctx
);
512 /* si_hw_context.c */
513 void si_destroy_saved_cs(struct si_saved_cs
*scs
);
514 void si_context_gfx_flush(void *context
, unsigned flags
,
515 struct pipe_fence_handle
**fence
);
516 void si_begin_new_cs(struct si_context
*ctx
);
517 void si_need_cs_space(struct si_context
*ctx
);
520 void si_init_compute_functions(struct si_context
*sctx
);
522 /* si_perfcounters.c */
523 void si_init_perfcounters(struct si_screen
*screen
);
526 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
527 const struct pipe_video_codec
*templ
);
529 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
530 const struct pipe_video_buffer
*tmpl
);
537 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
539 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
543 si_set_atom_dirty(struct si_context
*sctx
,
544 struct r600_atom
*atom
, bool dirty
)
546 unsigned bit
= 1 << atom
->id
;
549 sctx
->dirty_atoms
|= bit
;
551 sctx
->dirty_atoms
&= ~bit
;
555 si_is_atom_dirty(struct si_context
*sctx
,
556 struct r600_atom
*atom
)
558 unsigned bit
= 1 << atom
->id
;
560 return sctx
->dirty_atoms
& bit
;
564 si_mark_atom_dirty(struct si_context
*sctx
,
565 struct r600_atom
*atom
)
567 si_set_atom_dirty(sctx
, atom
, true);
570 static inline struct si_shader_ctx_state
*si_get_vs(struct si_context
*sctx
)
572 if (sctx
->gs_shader
.cso
)
573 return &sctx
->gs_shader
;
574 if (sctx
->tes_shader
.cso
)
575 return &sctx
->tes_shader
;
577 return &sctx
->vs_shader
;
580 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
582 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
584 return vs
->cso
? &vs
->cso
->info
: NULL
;
587 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
589 if (sctx
->gs_shader
.cso
)
590 return sctx
->gs_shader
.cso
->gs_copy_shader
;
592 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
593 return vs
->current
? vs
->current
: NULL
;
596 static inline unsigned
597 si_optimal_tcc_alignment(struct si_context
*sctx
, unsigned upload_size
)
599 unsigned alignment
, tcc_cache_line_size
;
601 /* If the upload size is less than the cache line size (e.g. 16, 32),
602 * the whole thing will fit into a cache line if we align it to its size.
603 * The idea is that multiple small uploads can share a cache line.
604 * If the upload size is greater, align it to the cache line size.
606 alignment
= util_next_power_of_two(upload_size
);
607 tcc_cache_line_size
= sctx
->screen
->b
.info
.tcc_cache_line_size
;
608 return MIN2(alignment
, tcc_cache_line_size
);
612 si_saved_cs_reference(struct si_saved_cs
**dst
, struct si_saved_cs
*src
)
614 if (pipe_reference(&(*dst
)->reference
, &src
->reference
))
615 si_destroy_saved_cs(*dst
);
621 si_make_CB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
622 bool shaders_read_metadata
)
624 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
|
625 SI_CONTEXT_INV_VMEM_L1
;
627 if (sctx
->b
.chip_class
>= GFX9
) {
628 /* Single-sample color is coherent with shaders on GFX9, but
629 * L2 metadata must be flushed if shaders read metadata.
632 if (num_samples
>= 2)
633 sctx
->b
.flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
634 else if (shaders_read_metadata
)
635 sctx
->b
.flags
|= SI_CONTEXT_INV_L2_METADATA
;
638 sctx
->b
.flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
643 si_make_DB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
644 bool include_stencil
, bool shaders_read_metadata
)
646 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_DB
|
647 SI_CONTEXT_INV_VMEM_L1
;
649 if (sctx
->b
.chip_class
>= GFX9
) {
650 /* Single-sample depth (not stencil) is coherent with shaders
651 * on GFX9, but L2 metadata must be flushed if shaders read
654 if (num_samples
>= 2 || include_stencil
)
655 sctx
->b
.flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
656 else if (shaders_read_metadata
)
657 sctx
->b
.flags
|= SI_CONTEXT_INV_L2_METADATA
;
660 sctx
->b
.flags
|= SI_CONTEXT_INV_GLOBAL_L2
;