src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef SI_PIPE_H
  27 #define SI_PIPE_H
  28
  29 #include "si_shader.h"
  30
  31 #include "util/u_dynarray.h"
  32
  33 #ifdef PIPE_ARCH_BIG_ENDIAN
  34 #define SI_BIG_ENDIAN 1
  35 #else
  36 #define SI_BIG_ENDIAN 0
  37 #endif
  38
  39 /* The base vertex and primitive restart can be any number, but we must pick
  40  * one which will mean "unknown" for the purpose of state tracking and
  41  * the number shouldn't be a commonly-used one. */
  42 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  43 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  44 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  45 #define SI_GS_PER_ES 128
  46 /* Alignment for optimal CP DMA performance. */
  47 #define SI_CPDMA_ALIGNMENT      32
  48
  49 /* Instruction cache. */
  50 #define SI_CONTEXT_INV_ICACHE           (R600_CONTEXT_PRIVATE_FLAG << 0)
  51 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  52 #define SI_CONTEXT_INV_SMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 1)
  53 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  54 #define SI_CONTEXT_INV_VMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 2)
  55 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  56 #define SI_CONTEXT_INV_GLOBAL_L2        (R600_CONTEXT_PRIVATE_FLAG << 3)
  57 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  58  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
  59 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2  (R600_CONTEXT_PRIVATE_FLAG << 4)
  60 /* gaps */
  61 /* Framebuffer caches. */
  62 #define SI_CONTEXT_FLUSH_AND_INV_DB     (R600_CONTEXT_PRIVATE_FLAG << 7)
  63 #define SI_CONTEXT_FLUSH_AND_INV_CB     (R600_CONTEXT_PRIVATE_FLAG << 8)
  64 /* Engine synchronization. */
  65 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 9)
  66 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 10)
  67 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 11)
  68 #define SI_CONTEXT_VGT_FLUSH            (R600_CONTEXT_PRIVATE_FLAG << 12)
  69 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (R600_CONTEXT_PRIVATE_FLAG << 13)
  70
  71 #define SI_PREFETCH_VBO_DESCRIPTORS     (1 << 0)
  72 #define SI_PREFETCH_LS                  (1 << 1)
  73 #define SI_PREFETCH_HS                  (1 << 2)
  74 #define SI_PREFETCH_ES                  (1 << 3)
  75 #define SI_PREFETCH_GS                  (1 << 4)
  76 #define SI_PREFETCH_VS                  (1 << 5)
  77 #define SI_PREFETCH_PS                  (1 << 6)
  78
  79 #define SI_MAX_BORDER_COLORS    4096
  80 #define SIX_BITS                0x3F
  81
  82 struct si_compute;
  83 struct hash_table;
  84 struct u_suballocator;
  85
  86 struct si_screen {
  87         struct r600_common_screen       b;
  88         unsigned                        gs_table_depth;
  89         unsigned                        tess_offchip_block_dw_size;
  90         bool                            has_clear_state;
  91         bool                            has_distributed_tess;
  92         bool                            has_draw_indirect_multi;
  93         bool                            has_ds_bpermute;
  94         bool                            has_msaa_sample_loc_bug;
  95         bool                            llvm_has_working_vgpr_indexing;
  96
  97         /* Whether shaders are monolithic (1-part) or separate (3-part). */
  98         bool                            use_monolithic_shaders;
  99         bool                            record_llvm_ir;
 100
 101         mtx_t                   shader_parts_mutex;
 102         struct si_shader_part           *vs_prologs;
 103         struct si_shader_part           *tcs_epilogs;
 104         struct si_shader_part           *gs_prologs;
 105         struct si_shader_part           *ps_prologs;
 106         struct si_shader_part           *ps_epilogs;
 107
 108         /* Shader cache in memory.
 109          *
 110          * Design & limitations:
 111          * - The shader cache is per screen (= per process), never saved to
 112          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 113          * - It can only be used with one-variant-per-shader support, in which
 114          *   case only the main (typically middle) part of shaders is cached.
 115          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 116          *   variants of VS and TES are cached, so LS and ES aren't.
 117          * - GS and CS aren't cached, but it's certainly possible to cache
 118          *   those as well.
 119          */
 120         mtx_t                   shader_cache_mutex;
 121         struct hash_table               *shader_cache;
 122
 123         /* Shader compiler queue for multithreaded compilation. */
 124         struct util_queue               shader_compiler_queue;
 125         /* Use at most 3 normal compiler threads on quadcore and better.
 126          * Hyperthreaded CPUs report the number of threads, but we want
 127          * the number of cores. */
 128         LLVMTargetMachineRef            tm[3]; /* used by the queue only */
 129
 130         struct util_queue               shader_compiler_queue_low_priority;
 131         /* Use at most 2 low priority threads on quadcore and better.
 132          * We want to minimize the impact on multithreaded Mesa. */
 133         LLVMTargetMachineRef            tm_low_priority[2]; /* at most 2 threads */
 134 };
 135
 136 struct si_blend_color {
 137         struct r600_atom                atom;
 138         struct pipe_blend_color         state;
 139         bool                            any_nonzeros;
 140 };
 141
 142 struct si_sampler_view {
 143         struct pipe_sampler_view        base;
 144         /* [0..7] = image descriptor
 145          * [4..7] = buffer descriptor */
 146         uint32_t                        state[8];
 147         uint32_t                        fmask_state[8];
 148         const struct legacy_surf_level  *base_level_info;
 149         ubyte                           base_level;
 150         ubyte                           block_width;
 151         bool is_stencil_sampler;
 152         bool dcc_incompatible;
 153 };
 154
 155 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
 156
 157 struct si_sampler_state {
 158 #ifdef DEBUG
 159         unsigned                        magic;
 160 #endif
 161         uint32_t                        val[4];
 162 };
 163
 164 struct si_cs_shader_state {
 165         struct si_compute               *program;
 166         struct si_compute               *emitted_program;
 167         unsigned                        offset;
 168         bool                            initialized;
 169         bool                            uses_scratch;
 170 };
 171
 172 struct si_textures_info {
 173         struct si_sampler_views         views;
 174         uint32_t                        needs_depth_decompress_mask;
 175         uint32_t                        needs_color_decompress_mask;
 176 };
 177
 178 struct si_images_info {
 179         struct pipe_image_view          views[SI_NUM_IMAGES];
 180         uint32_t                        needs_color_decompress_mask;
 181         unsigned                        enabled_mask;
 182 };
 183
 184 struct si_framebuffer {
 185         struct r600_atom                atom;
 186         struct pipe_framebuffer_state   state;
 187         unsigned                        colorbuf_enabled_4bit;
 188         unsigned                        spi_shader_col_format;
 189         unsigned                        spi_shader_col_format_alpha;
 190         unsigned                        spi_shader_col_format_blend;
 191         unsigned                        spi_shader_col_format_blend_alpha;
 192         ubyte                           nr_samples:5; /* at most 16xAA */
 193         ubyte                           log_samples:3; /* at most 4 = 16xAA */
 194         ubyte                           compressed_cb_mask;
 195         ubyte                           color_is_int8;
 196         ubyte                           color_is_int10;
 197         ubyte                           dirty_cbufs;
 198         bool                            dirty_zsbuf;
 199         bool                            any_dst_linear;
 200 };
 201
 202 struct si_clip_state {
 203         struct r600_atom                atom;
 204         struct pipe_clip_state          state;
 205         bool                            any_nonzeros;
 206 };
 207
 208 struct si_sample_locs {
 209         struct r600_atom        atom;
 210         unsigned                nr_samples;
 211 };
 212
 213 struct si_sample_mask {
 214         struct r600_atom        atom;
 215         uint16_t                sample_mask;
 216 };
 217
 218 /* A shader state consists of the shader selector, which is a constant state
 219  * object shared by multiple contexts and shouldn't be modified, and
 220  * the current shader variant selected for this context.
 221  */
 222 struct si_shader_ctx_state {
 223         struct si_shader_selector       *cso;
 224         struct si_shader                *current;
 225 };
 226
 227 #define SI_NUM_VGT_PARAM_KEY_BITS 12
 228 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
 229
 230 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
 231  * Some fields are set by state-change calls, most are set by draw_vbo.
 232  */
 233 union si_vgt_param_key {
 234         struct {
 235                 unsigned prim:4;
 236                 unsigned uses_instancing:1;
 237                 unsigned multi_instances_smaller_than_primgroup:1;
 238                 unsigned primitive_restart:1;
 239                 unsigned count_from_stream_output:1;
 240                 unsigned line_stipple_enabled:1;
 241                 unsigned uses_tess:1;
 242                 unsigned tess_uses_prim_id:1;
 243                 unsigned uses_gs:1;
 244                 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
 245         } u;
 246         uint32_t index;
 247 };
 248
 249 struct si_bindless_descriptor
 250 {
 251         struct pb_slab_entry            entry;
 252         struct r600_resource            *buffer;
 253         unsigned                        offset;
 254         uint32_t                        desc_list[16];
 255         bool                            dirty;
 256 };
 257
 258 struct si_texture_handle
 259 {
 260         struct si_bindless_descriptor   *desc;
 261         struct pipe_sampler_view        *view;
 262         struct si_sampler_state         sstate;
 263 };
 264
 265 struct si_image_handle
 266 {
 267         struct si_bindless_descriptor   *desc;
 268         struct pipe_image_view          view;
 269 };
 270
 271 struct si_context {
 272         struct r600_common_context      b;
 273         struct blitter_context          *blitter;
 274         void                            *custom_dsa_flush;
 275         void                            *custom_blend_resolve;
 276         void                            *custom_blend_fmask_decompress;
 277         void                            *custom_blend_eliminate_fastclear;
 278         void                            *custom_blend_dcc_decompress;
 279         struct si_screen                *screen;
 280         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 281         struct si_shader_ctx_state      fixed_func_tcs_shader;
 282         struct r600_resource            *wait_mem_scratch;
 283         unsigned                        wait_mem_number;
 284
 285         struct radeon_winsys_cs         *ce_ib;
 286         struct radeon_winsys_cs         *ce_preamble_ib;
 287         struct r600_resource            *ce_ram_saved_buffer;
 288         struct u_suballocator           *ce_suballocator;
 289         unsigned                        ce_ram_saved_offset;
 290         uint16_t                        total_ce_ram_allocated;
 291         uint16_t                        prefetch_L2_mask;
 292         bool                            ce_need_synchronization:1;
 293
 294         bool                            gfx_flush_in_progress:1;
 295         bool                            compute_is_busy:1;
 296
 297         /* Atoms (direct states). */
 298         union si_state_atoms            atoms;
 299         unsigned                        dirty_atoms; /* mask */
 300         /* PM4 states (precomputed immutable states) */
 301         unsigned                        dirty_states;
 302         union si_state                  queued;
 303         union si_state                  emitted;
 304
 305         /* Atom declarations. */
 306         struct si_framebuffer           framebuffer;
 307         struct si_sample_locs           msaa_sample_locs;
 308         struct r600_atom                db_render_state;
 309         struct r600_atom                msaa_config;
 310         struct si_sample_mask           sample_mask;
 311         struct r600_atom                cb_render_state;
 312         unsigned                        last_cb_target_mask;
 313         struct si_blend_color           blend_color;
 314         struct r600_atom                clip_regs;
 315         struct si_clip_state            clip_state;
 316         struct si_shader_data           shader_pointers;
 317         struct si_stencil_ref           stencil_ref;
 318         struct r600_atom                spi_map;
 319
 320         /* Precomputed states. */
 321         struct si_pm4_state             *init_config;
 322         struct si_pm4_state             *init_config_gs_rings;
 323         bool                            init_config_has_vgt_flush;
 324         struct si_pm4_state             *vgt_shader_config[4];
 325
 326         /* shaders */
 327         struct si_shader_ctx_state      ps_shader;
 328         struct si_shader_ctx_state      gs_shader;
 329         struct si_shader_ctx_state      vs_shader;
 330         struct si_shader_ctx_state      tcs_shader;
 331         struct si_shader_ctx_state      tes_shader;
 332         struct si_cs_shader_state       cs_shader_state;
 333
 334         /* shader information */
 335         struct si_vertex_elements       *vertex_elements;
 336         unsigned                        sprite_coord_enable;
 337         bool                            flatshade;
 338         bool                            do_update_shaders;
 339
 340         /* shader descriptors */
 341         struct si_descriptors           vertex_buffers;
 342         struct si_descriptors           descriptors[SI_NUM_DESCS];
 343         unsigned                        descriptors_dirty;
 344         unsigned                        shader_pointers_dirty;
 345         unsigned                        shader_needs_decompress_mask;
 346         struct si_buffer_resources      rw_buffers;
 347         struct si_buffer_resources      const_and_shader_buffers[SI_NUM_SHADERS];
 348         struct si_textures_info         samplers[SI_NUM_SHADERS];
 349         struct si_images_info           images[SI_NUM_SHADERS];
 350
 351         /* other shader resources */
 352         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 353         struct pipe_resource            *esgs_ring;
 354         struct pipe_resource            *gsvs_ring;
 355         struct pipe_resource            *tf_ring;
 356         struct pipe_resource            *tess_offchip_ring;
 357         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 358         struct r600_resource            *border_color_buffer;
 359         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 360         unsigned                        border_color_count;
 361
 362         /* Vertex and index buffers. */
 363         bool                            vertex_buffers_dirty;
 364         bool                            vertex_buffer_pointer_dirty;
 365         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 366
 367         /* MSAA config state. */
 368         int                             ps_iter_samples;
 369         bool                            smoothing_enabled;
 370
 371         /* DB render state. */
 372         unsigned                ps_db_shader_control;
 373         unsigned                dbcb_copy_sample;
 374         bool                    dbcb_depth_copy_enabled:1;
 375         bool                    dbcb_stencil_copy_enabled:1;
 376         bool                    db_flush_depth_inplace:1;
 377         bool                    db_flush_stencil_inplace:1;
 378         bool                    db_depth_clear:1;
 379         bool                    db_depth_disable_expclear:1;
 380         bool                    db_stencil_clear:1;
 381         bool                    db_stencil_disable_expclear:1;
 382         bool                    occlusion_queries_disabled:1;
 383         bool                    generate_mipmap_for_depth:1;
 384
 385         /* Emitted draw state. */
 386         bool                    gs_tri_strip_adj_fix:1;
 387         int                     last_index_size;
 388         int                     last_base_vertex;
 389         int                     last_start_instance;
 390         int                     last_drawid;
 391         int                     last_sh_base_reg;
 392         int                     last_primitive_restart_en;
 393         int                     last_restart_index;
 394         int                     last_gs_out_prim;
 395         int                     last_prim;
 396         int                     last_multi_vgt_param;
 397         int                     last_rast_prim;
 398         unsigned                last_sc_line_stipple;
 399         unsigned                current_vs_state;
 400         unsigned                last_vs_state;
 401         enum pipe_prim_type     current_rast_prim; /* primitive type after TES, GS */
 402
 403         /* Scratch buffer */
 404         struct r600_atom        scratch_state;
 405         struct r600_resource    *scratch_buffer;
 406         unsigned                scratch_waves;
 407         unsigned                spi_tmpring_size;
 408
 409         struct r600_resource    *compute_scratch_buffer;
 410
 411         /* Emitted derived tessellation state. */
 412         /* Local shader (VS), or HS if LS-HS are merged. */
 413         struct si_shader        *last_ls;
 414         struct si_shader_selector *last_tcs;
 415         int                     last_num_tcs_input_cp;
 416         int                     last_tes_sh_base;
 417         bool                    last_tess_uses_primid;
 418         unsigned                last_num_patches;
 419
 420         /* Debug state. */
 421         bool                    is_debug;
 422         struct radeon_saved_cs  last_gfx;
 423         struct radeon_saved_cs  last_ce;
 424         struct r600_resource    *last_trace_buf;
 425         struct r600_resource    *trace_buf;
 426         unsigned                trace_id;
 427         uint64_t                dmesg_timestamp;
 428         unsigned                apitrace_call_number;
 429
 430         /* Other state */
 431         bool need_check_render_feedback;
 432         bool                    decompression_enabled;
 433
 434         /* Precomputed IA_MULTI_VGT_PARAM */
 435         union si_vgt_param_key  ia_multi_vgt_param_key;
 436         unsigned                ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
 437
 438         /* Slab allocator for bindless descriptors. */
 439         struct pb_slabs         bindless_descriptor_slabs;
 440
 441         /* Bindless descriptors. */
 442         struct util_dynarray    bindless_descriptors;
 443         bool                    bindless_descriptors_dirty;
 444
 445         /* Allocated bindless handles */
 446         struct hash_table       *tex_handles;
 447         struct hash_table       *img_handles;
 448
 449         /* Resident bindless handles */
 450         struct util_dynarray    resident_tex_handles;
 451         struct util_dynarray    resident_img_handles;
 452
 453         /* Resident bindless handles which need decompression */
 454         struct util_dynarray    resident_tex_needs_color_decompress;
 455         struct util_dynarray    resident_img_needs_color_decompress;
 456         struct util_dynarray    resident_tex_needs_depth_decompress;
 457
 458         /* Bindless state */
 459         bool                    uses_bindless_samplers;
 460         bool                    uses_bindless_images;
 461 };
 462
 463 /* cik_sdma.c */
 464 void cik_init_sdma_functions(struct si_context *sctx);
 465
 466 /* si_blit.c */
 467 void si_init_blit_functions(struct si_context *sctx);
 468 void si_decompress_graphics_textures(struct si_context *sctx);
 469 void si_decompress_compute_textures(struct si_context *sctx);
 470 void si_resource_copy_region(struct pipe_context *ctx,
 471                              struct pipe_resource *dst,
 472                              unsigned dst_level,
 473                              unsigned dstx, unsigned dsty, unsigned dstz,
 474                              struct pipe_resource *src,
 475                              unsigned src_level,
 476                              const struct pipe_box *src_box);
 477
 478 /* si_cp_dma.c */
 479 #define SI_CPDMA_SKIP_CHECK_CS_SPACE    (1 << 0) /* don't call need_cs_space */
 480 #define SI_CPDMA_SKIP_SYNC_AFTER        (1 << 1) /* don't wait for DMA after the copy */
 481 #define SI_CPDMA_SKIP_SYNC_BEFORE       (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
 482 #define SI_CPDMA_SKIP_GFX_SYNC          (1 << 3) /* don't flush caches and don't wait for PS/CS */
 483 #define SI_CPDMA_SKIP_BO_LIST_UPDATE    (1 << 4) /* don't update the BO list */
 484 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
 485                            SI_CPDMA_SKIP_SYNC_AFTER | \
 486                            SI_CPDMA_SKIP_SYNC_BEFORE | \
 487                            SI_CPDMA_SKIP_GFX_SYNC | \
 488                            SI_CPDMA_SKIP_BO_LIST_UPDATE)
 489
 490 void si_copy_buffer(struct si_context *sctx,
 491                     struct pipe_resource *dst, struct pipe_resource *src,
 492                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 493                     unsigned user_flags);
 494 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 495                               uint64_t offset, unsigned size);
 496 void cik_emit_prefetch_L2(struct si_context *sctx);
 497 void si_init_cp_dma_functions(struct si_context *sctx);
 498
 499 /* si_debug.c */
 500 void si_init_debug_functions(struct si_context *sctx);
 501 void si_check_vm_faults(struct r600_common_context *ctx,
 502                         struct radeon_saved_cs *saved, enum ring_type ring);
 503 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
 504
 505 /* si_dma.c */
 506 void si_init_dma_functions(struct si_context *sctx);
 507
 508 /* si_hw_context.c */
 509 void si_context_gfx_flush(void *context, unsigned flags,
 510                           struct pipe_fence_handle **fence);
 511 void si_begin_new_cs(struct si_context *ctx);
 512 void si_need_cs_space(struct si_context *ctx);
 513
 514 /* si_compute.c */
 515 void si_init_compute_functions(struct si_context *sctx);
 516
 517 /* si_perfcounters.c */
 518 void si_init_perfcounters(struct si_screen *screen);
 519
 520 /* si_uvd.c */
 521 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 522                                                const struct pipe_video_codec *templ);
 523
 524 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 525                                                  const struct pipe_video_buffer *tmpl);
 526
 527 /*
 528  * common helpers
 529  */
 530
 531 static inline void
 532 si_invalidate_draw_sh_constants(struct si_context *sctx)
 533 {
 534         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 535 }
 536
 537 static inline void
 538 si_set_atom_dirty(struct si_context *sctx,
 539                   struct r600_atom *atom, bool dirty)
 540 {
 541         unsigned bit = 1 << atom->id;
 542
 543         if (dirty)
 544                 sctx->dirty_atoms |= bit;
 545         else
 546                 sctx->dirty_atoms &= ~bit;
 547 }
 548
 549 static inline bool
 550 si_is_atom_dirty(struct si_context *sctx,
 551                   struct r600_atom *atom)
 552 {
 553         unsigned bit = 1 << atom->id;
 554
 555         return sctx->dirty_atoms & bit;
 556 }
 557
 558 static inline void
 559 si_mark_atom_dirty(struct si_context *sctx,
 560                    struct r600_atom *atom)
 561 {
 562         si_set_atom_dirty(sctx, atom, true);
 563 }
 564
 565 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
 566 {
 567         if (sctx->gs_shader.cso)
 568                 return &sctx->gs_shader;
 569         if (sctx->tes_shader.cso)
 570                 return &sctx->tes_shader;
 571
 572         return &sctx->vs_shader;
 573 }
 574
 575 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 576 {
 577         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 578
 579         return vs->cso ? &vs->cso->info : NULL;
 580 }
 581
 582 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 583 {
 584         if (sctx->gs_shader.cso)
 585                 return sctx->gs_shader.cso->gs_copy_shader;
 586
 587         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 588         return vs->current ? vs->current : NULL;
 589 }
 590
 591 static inline unsigned
 592 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
 593 {
 594         unsigned alignment, tcc_cache_line_size;
 595
 596         /* If the upload size is less than the cache line size (e.g. 16, 32),
 597          * the whole thing will fit into a cache line if we align it to its size.
 598          * The idea is that multiple small uploads can share a cache line.
 599          * If the upload size is greater, align it to the cache line size.
 600          */
 601         alignment = util_next_power_of_two(upload_size);
 602         tcc_cache_line_size = sctx->screen->b.info.tcc_cache_line_size;
 603         return MIN2(alignment, tcc_cache_line_size);
 604 }
 605
 606 #endif