src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef SI_PIPE_H
  27 #define SI_PIPE_H
  28
  29 #include "si_shader.h"
  30
  31 #include "util/u_dynarray.h"
  32 #include "util/u_idalloc.h"
  33
  34 #ifdef PIPE_ARCH_BIG_ENDIAN
  35 #define SI_BIG_ENDIAN 1
  36 #else
  37 #define SI_BIG_ENDIAN 0
  38 #endif
  39
  40 /* The base vertex and primitive restart can be any number, but we must pick
  41  * one which will mean "unknown" for the purpose of state tracking and
  42  * the number shouldn't be a commonly-used one. */
  43 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  44 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  45 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  46 #define SI_GS_PER_ES 128
  47 /* Alignment for optimal CP DMA performance. */
  48 #define SI_CPDMA_ALIGNMENT      32
  49
  50 /* Instruction cache. */
  51 #define SI_CONTEXT_INV_ICACHE           (R600_CONTEXT_PRIVATE_FLAG << 0)
  52 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  53 #define SI_CONTEXT_INV_SMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 1)
  54 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  55 #define SI_CONTEXT_INV_VMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 2)
  56 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  57 #define SI_CONTEXT_INV_GLOBAL_L2        (R600_CONTEXT_PRIVATE_FLAG << 3)
  58 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  59  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
  60 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2  (R600_CONTEXT_PRIVATE_FLAG << 4)
  61 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
  62  * a CB or DB flush. */
  63 #define SI_CONTEXT_INV_L2_METADATA      (R600_CONTEXT_PRIVATE_FLAG << 5)
  64 /* Framebuffer caches. */
  65 #define SI_CONTEXT_FLUSH_AND_INV_DB     (R600_CONTEXT_PRIVATE_FLAG << 6)
  66 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 7)
  67 #define SI_CONTEXT_FLUSH_AND_INV_CB     (R600_CONTEXT_PRIVATE_FLAG << 8)
  68 /* Engine synchronization. */
  69 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 9)
  70 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 10)
  71 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 11)
  72 #define SI_CONTEXT_VGT_FLUSH            (R600_CONTEXT_PRIVATE_FLAG << 12)
  73 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (R600_CONTEXT_PRIVATE_FLAG << 13)
  74
  75 #define SI_PREFETCH_VBO_DESCRIPTORS     (1 << 0)
  76 #define SI_PREFETCH_LS                  (1 << 1)
  77 #define SI_PREFETCH_HS                  (1 << 2)
  78 #define SI_PREFETCH_ES                  (1 << 3)
  79 #define SI_PREFETCH_GS                  (1 << 4)
  80 #define SI_PREFETCH_VS                  (1 << 5)
  81 #define SI_PREFETCH_PS                  (1 << 6)
  82
  83 #define SI_MAX_BORDER_COLORS    4096
  84 #define SI_MAX_VIEWPORTS        16
  85 #define SIX_BITS                0x3F
  86
  87 struct si_compute;
  88 struct hash_table;
  89 struct u_suballocator;
  90
  91 struct si_screen {
  92         struct r600_common_screen       b;
  93         unsigned                        gs_table_depth;
  94         unsigned                        tess_offchip_block_dw_size;
  95         bool                            has_clear_state;
  96         bool                            has_distributed_tess;
  97         bool                            has_draw_indirect_multi;
  98         bool                            has_out_of_order_rast;
  99         bool                            assume_no_z_fights;
 100         bool                            commutative_blend_add;
 101         bool                            has_msaa_sample_loc_bug;
 102         bool                            dpbb_allowed;
 103         bool                            dfsm_allowed;
 104         bool                            llvm_has_working_vgpr_indexing;
 105
 106         /* Whether shaders are monolithic (1-part) or separate (3-part). */
 107         bool                            use_monolithic_shaders;
 108         bool                            record_llvm_ir;
 109
 110         mtx_t                   shader_parts_mutex;
 111         struct si_shader_part           *vs_prologs;
 112         struct si_shader_part           *tcs_epilogs;
 113         struct si_shader_part           *gs_prologs;
 114         struct si_shader_part           *ps_prologs;
 115         struct si_shader_part           *ps_epilogs;
 116
 117         /* Shader cache in memory.
 118          *
 119          * Design & limitations:
 120          * - The shader cache is per screen (= per process), never saved to
 121          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 122          * - It can only be used with one-variant-per-shader support, in which
 123          *   case only the main (typically middle) part of shaders is cached.
 124          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 125          *   variants of VS and TES are cached, so LS and ES aren't.
 126          * - GS and CS aren't cached, but it's certainly possible to cache
 127          *   those as well.
 128          */
 129         mtx_t                   shader_cache_mutex;
 130         struct hash_table               *shader_cache;
 131
 132         /* Shader compiler queue for multithreaded compilation. */
 133         struct util_queue               shader_compiler_queue;
 134         /* Use at most 3 normal compiler threads on quadcore and better.
 135          * Hyperthreaded CPUs report the number of threads, but we want
 136          * the number of cores. */
 137         LLVMTargetMachineRef            tm[3]; /* used by the queue only */
 138
 139         struct util_queue               shader_compiler_queue_low_priority;
 140         /* Use at most 2 low priority threads on quadcore and better.
 141          * We want to minimize the impact on multithreaded Mesa. */
 142         LLVMTargetMachineRef            tm_low_priority[2]; /* at most 2 threads */
 143 };
 144
 145 struct si_blend_color {
 146         struct r600_atom                atom;
 147         struct pipe_blend_color         state;
 148         bool                            any_nonzeros;
 149 };
 150
 151 struct si_sampler_view {
 152         struct pipe_sampler_view        base;
 153         /* [0..7] = image descriptor
 154          * [4..7] = buffer descriptor */
 155         uint32_t                        state[8];
 156         uint32_t                        fmask_state[8];
 157         const struct legacy_surf_level  *base_level_info;
 158         ubyte                           base_level;
 159         ubyte                           block_width;
 160         bool is_stencil_sampler;
 161         bool is_integer;
 162         bool dcc_incompatible;
 163 };
 164
 165 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
 166
 167 struct si_sampler_state {
 168 #ifdef DEBUG
 169         unsigned                        magic;
 170 #endif
 171         uint32_t                        val[4];
 172         uint32_t                        integer_val[4];
 173         uint32_t                        upgraded_depth_val[4];
 174 };
 175
 176 struct si_cs_shader_state {
 177         struct si_compute               *program;
 178         struct si_compute               *emitted_program;
 179         unsigned                        offset;
 180         bool                            initialized;
 181         bool                            uses_scratch;
 182 };
 183
 184 struct si_samplers {
 185         struct pipe_sampler_view        *views[SI_NUM_SAMPLERS];
 186         struct si_sampler_state         *sampler_states[SI_NUM_SAMPLERS];
 187
 188         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 189         unsigned                        enabled_mask;
 190         uint32_t                        needs_depth_decompress_mask;
 191         uint32_t                        needs_color_decompress_mask;
 192 };
 193
 194 struct si_images {
 195         struct pipe_image_view          views[SI_NUM_IMAGES];
 196         uint32_t                        needs_color_decompress_mask;
 197         unsigned                        enabled_mask;
 198 };
 199
 200 struct si_framebuffer {
 201         struct r600_atom                atom;
 202         struct pipe_framebuffer_state   state;
 203         unsigned                        colorbuf_enabled_4bit;
 204         unsigned                        spi_shader_col_format;
 205         unsigned                        spi_shader_col_format_alpha;
 206         unsigned                        spi_shader_col_format_blend;
 207         unsigned                        spi_shader_col_format_blend_alpha;
 208         ubyte                           nr_samples:5; /* at most 16xAA */
 209         ubyte                           log_samples:3; /* at most 4 = 16xAA */
 210         ubyte                           compressed_cb_mask;
 211         ubyte                           color_is_int8;
 212         ubyte                           color_is_int10;
 213         ubyte                           dirty_cbufs;
 214         bool                            dirty_zsbuf;
 215         bool                            any_dst_linear;
 216         bool                            CB_has_shader_readable_metadata;
 217         bool                            DB_has_shader_readable_metadata;
 218 };
 219
 220 struct si_signed_scissor {
 221         int minx;
 222         int miny;
 223         int maxx;
 224         int maxy;
 225 };
 226
 227 struct si_scissors {
 228         struct r600_atom                atom;
 229         unsigned                        dirty_mask;
 230         struct pipe_scissor_state       states[SI_MAX_VIEWPORTS];
 231 };
 232
 233 struct si_viewports {
 234         struct r600_atom                atom;
 235         unsigned                        dirty_mask;
 236         unsigned                        depth_range_dirty_mask;
 237         struct pipe_viewport_state      states[SI_MAX_VIEWPORTS];
 238         struct si_signed_scissor        as_scissor[SI_MAX_VIEWPORTS];
 239 };
 240
 241 struct si_clip_state {
 242         struct r600_atom                atom;
 243         struct pipe_clip_state          state;
 244         bool                            any_nonzeros;
 245 };
 246
 247 struct si_sample_locs {
 248         struct r600_atom        atom;
 249         unsigned                nr_samples;
 250 };
 251
 252 struct si_sample_mask {
 253         struct r600_atom        atom;
 254         uint16_t                sample_mask;
 255 };
 256
 257 /* A shader state consists of the shader selector, which is a constant state
 258  * object shared by multiple contexts and shouldn't be modified, and
 259  * the current shader variant selected for this context.
 260  */
 261 struct si_shader_ctx_state {
 262         struct si_shader_selector       *cso;
 263         struct si_shader                *current;
 264 };
 265
 266 #define SI_NUM_VGT_PARAM_KEY_BITS 12
 267 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
 268
 269 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
 270  * Some fields are set by state-change calls, most are set by draw_vbo.
 271  */
 272 union si_vgt_param_key {
 273         struct {
 274                 unsigned prim:4;
 275                 unsigned uses_instancing:1;
 276                 unsigned multi_instances_smaller_than_primgroup:1;
 277                 unsigned primitive_restart:1;
 278                 unsigned count_from_stream_output:1;
 279                 unsigned line_stipple_enabled:1;
 280                 unsigned uses_tess:1;
 281                 unsigned tess_uses_prim_id:1;
 282                 unsigned uses_gs:1;
 283                 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
 284         } u;
 285         uint32_t index;
 286 };
 287
 288 struct si_texture_handle
 289 {
 290         unsigned                        desc_slot;
 291         bool                            desc_dirty;
 292         struct pipe_sampler_view        *view;
 293         struct si_sampler_state         sstate;
 294 };
 295
 296 struct si_image_handle
 297 {
 298         unsigned                        desc_slot;
 299         bool                            desc_dirty;
 300         struct pipe_image_view          view;
 301 };
 302
 303 struct si_saved_cs {
 304         struct pipe_reference   reference;
 305         struct si_context       *ctx;
 306         struct radeon_saved_cs  gfx;
 307         struct r600_resource    *trace_buf;
 308         unsigned                trace_id;
 309
 310         unsigned                gfx_last_dw;
 311         bool                    flushed;
 312 };
 313
 314 struct si_context {
 315         struct r600_common_context      b;
 316         struct blitter_context          *blitter;
 317         void                            *custom_dsa_flush;
 318         void                            *custom_blend_resolve;
 319         void                            *custom_blend_fmask_decompress;
 320         void                            *custom_blend_eliminate_fastclear;
 321         void                            *custom_blend_dcc_decompress;
 322         struct si_screen                *screen;
 323         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 324         struct si_shader_ctx_state      fixed_func_tcs_shader;
 325         struct r600_resource            *wait_mem_scratch;
 326         unsigned                        wait_mem_number;
 327         uint16_t                        prefetch_L2_mask;
 328
 329         bool                            gfx_flush_in_progress:1;
 330         bool                            compute_is_busy:1;
 331
 332         /* Atoms (direct states). */
 333         union si_state_atoms            atoms;
 334         unsigned                        dirty_atoms; /* mask */
 335         /* PM4 states (precomputed immutable states) */
 336         unsigned                        dirty_states;
 337         union si_state                  queued;
 338         union si_state                  emitted;
 339
 340         /* Atom declarations. */
 341         struct si_framebuffer           framebuffer;
 342         struct si_sample_locs           msaa_sample_locs;
 343         struct r600_atom                db_render_state;
 344         struct r600_atom                dpbb_state;
 345         struct r600_atom                msaa_config;
 346         struct si_sample_mask           sample_mask;
 347         struct r600_atom                cb_render_state;
 348         unsigned                        last_cb_target_mask;
 349         struct si_blend_color           blend_color;
 350         struct r600_atom                clip_regs;
 351         struct si_clip_state            clip_state;
 352         struct si_shader_data           shader_pointers;
 353         struct si_stencil_ref           stencil_ref;
 354         struct r600_atom                spi_map;
 355         struct si_scissors              scissors;
 356         struct si_viewports             viewports;
 357
 358         /* Precomputed states. */
 359         struct si_pm4_state             *init_config;
 360         struct si_pm4_state             *init_config_gs_rings;
 361         bool                            init_config_has_vgt_flush;
 362         struct si_pm4_state             *vgt_shader_config[4];
 363
 364         /* shaders */
 365         struct si_shader_ctx_state      ps_shader;
 366         struct si_shader_ctx_state      gs_shader;
 367         struct si_shader_ctx_state      vs_shader;
 368         struct si_shader_ctx_state      tcs_shader;
 369         struct si_shader_ctx_state      tes_shader;
 370         struct si_cs_shader_state       cs_shader_state;
 371
 372         /* shader information */
 373         struct si_vertex_elements       *vertex_elements;
 374         unsigned                        sprite_coord_enable;
 375         bool                            flatshade;
 376         bool                            do_update_shaders;
 377
 378         /* shader descriptors */
 379         struct si_descriptors           vertex_buffers;
 380         struct si_descriptors           descriptors[SI_NUM_DESCS];
 381         unsigned                        descriptors_dirty;
 382         unsigned                        shader_pointers_dirty;
 383         unsigned                        shader_needs_decompress_mask;
 384         struct si_buffer_resources      rw_buffers;
 385         struct si_buffer_resources      const_and_shader_buffers[SI_NUM_SHADERS];
 386         struct si_samplers              samplers[SI_NUM_SHADERS];
 387         struct si_images                images[SI_NUM_SHADERS];
 388
 389         /* other shader resources */
 390         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 391         struct pipe_resource            *esgs_ring;
 392         struct pipe_resource            *gsvs_ring;
 393         struct pipe_resource            *tf_ring;
 394         struct pipe_resource            *tess_offchip_ring;
 395         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 396         struct r600_resource            *border_color_buffer;
 397         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 398         unsigned                        border_color_count;
 399
 400         /* Vertex and index buffers. */
 401         bool                            vertex_buffers_dirty;
 402         bool                            vertex_buffer_pointer_dirty;
 403         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 404
 405         /* MSAA config state. */
 406         int                             ps_iter_samples;
 407         bool                            smoothing_enabled;
 408
 409         /* DB render state. */
 410         unsigned                ps_db_shader_control;
 411         unsigned                dbcb_copy_sample;
 412         bool                    dbcb_depth_copy_enabled:1;
 413         bool                    dbcb_stencil_copy_enabled:1;
 414         bool                    db_flush_depth_inplace:1;
 415         bool                    db_flush_stencil_inplace:1;
 416         bool                    db_depth_clear:1;
 417         bool                    db_depth_disable_expclear:1;
 418         bool                    db_stencil_clear:1;
 419         bool                    db_stencil_disable_expclear:1;
 420         bool                    occlusion_queries_disabled:1;
 421         bool                    generate_mipmap_for_depth:1;
 422
 423         /* Emitted draw state. */
 424         bool                    gs_tri_strip_adj_fix:1;
 425         bool                    ls_vgpr_fix:1;
 426         int                     last_index_size;
 427         int                     last_base_vertex;
 428         int                     last_start_instance;
 429         int                     last_drawid;
 430         int                     last_sh_base_reg;
 431         int                     last_primitive_restart_en;
 432         int                     last_restart_index;
 433         int                     last_gs_out_prim;
 434         int                     last_prim;
 435         int                     last_multi_vgt_param;
 436         int                     last_rast_prim;
 437         unsigned                last_sc_line_stipple;
 438         unsigned                current_vs_state;
 439         unsigned                last_vs_state;
 440         enum pipe_prim_type     current_rast_prim; /* primitive type after TES, GS */
 441
 442         /* Scratch buffer */
 443         struct r600_atom        scratch_state;
 444         struct r600_resource    *scratch_buffer;
 445         unsigned                scratch_waves;
 446         unsigned                spi_tmpring_size;
 447
 448         struct r600_resource    *compute_scratch_buffer;
 449
 450         /* Emitted derived tessellation state. */
 451         /* Local shader (VS), or HS if LS-HS are merged. */
 452         struct si_shader        *last_ls;
 453         struct si_shader_selector *last_tcs;
 454         int                     last_num_tcs_input_cp;
 455         int                     last_tes_sh_base;
 456         bool                    last_tess_uses_primid;
 457         unsigned                last_num_patches;
 458
 459         /* Debug state. */
 460         bool                    is_debug;
 461         struct si_saved_cs      *current_saved_cs;
 462         uint64_t                dmesg_timestamp;
 463         unsigned                apitrace_call_number;
 464
 465         /* Other state */
 466         bool need_check_render_feedback;
 467         bool                    decompression_enabled;
 468
 469         bool                    vs_writes_viewport_index;
 470         bool                    vs_disables_clipping_viewport;
 471
 472         /* Precomputed IA_MULTI_VGT_PARAM */
 473         union si_vgt_param_key  ia_multi_vgt_param_key;
 474         unsigned                ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
 475
 476         /* Bindless descriptors. */
 477         struct si_descriptors   bindless_descriptors;
 478         struct util_idalloc     bindless_used_slots;
 479         unsigned                num_bindless_descriptors;
 480         bool                    bindless_descriptors_dirty;
 481         bool                    graphics_bindless_pointer_dirty;
 482         bool                    compute_bindless_pointer_dirty;
 483
 484         /* Allocated bindless handles */
 485         struct hash_table       *tex_handles;
 486         struct hash_table       *img_handles;
 487
 488         /* Resident bindless handles */
 489         struct util_dynarray    resident_tex_handles;
 490         struct util_dynarray    resident_img_handles;
 491
 492         /* Resident bindless handles which need decompression */
 493         struct util_dynarray    resident_tex_needs_color_decompress;
 494         struct util_dynarray    resident_img_needs_color_decompress;
 495         struct util_dynarray    resident_tex_needs_depth_decompress;
 496
 497         /* Bindless state */
 498         bool                    uses_bindless_samplers;
 499         bool                    uses_bindless_images;
 500 };
 501
 502 /* cik_sdma.c */
 503 void cik_init_sdma_functions(struct si_context *sctx);
 504
 505 /* si_blit.c */
 506 void si_init_blit_functions(struct si_context *sctx);
 507 void si_decompress_graphics_textures(struct si_context *sctx);
 508 void si_decompress_compute_textures(struct si_context *sctx);
 509 void si_resource_copy_region(struct pipe_context *ctx,
 510                              struct pipe_resource *dst,
 511                              unsigned dst_level,
 512                              unsigned dstx, unsigned dsty, unsigned dstz,
 513                              struct pipe_resource *src,
 514                              unsigned src_level,
 515                              const struct pipe_box *src_box);
 516
 517 /* si_cp_dma.c */
 518 #define SI_CPDMA_SKIP_CHECK_CS_SPACE    (1 << 0) /* don't call need_cs_space */
 519 #define SI_CPDMA_SKIP_SYNC_AFTER        (1 << 1) /* don't wait for DMA after the copy */
 520 #define SI_CPDMA_SKIP_SYNC_BEFORE       (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
 521 #define SI_CPDMA_SKIP_GFX_SYNC          (1 << 3) /* don't flush caches and don't wait for PS/CS */
 522 #define SI_CPDMA_SKIP_BO_LIST_UPDATE    (1 << 4) /* don't update the BO list */
 523 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
 524                            SI_CPDMA_SKIP_SYNC_AFTER | \
 525                            SI_CPDMA_SKIP_SYNC_BEFORE | \
 526                            SI_CPDMA_SKIP_GFX_SYNC | \
 527                            SI_CPDMA_SKIP_BO_LIST_UPDATE)
 528
 529 void si_copy_buffer(struct si_context *sctx,
 530                     struct pipe_resource *dst, struct pipe_resource *src,
 531                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 532                     unsigned user_flags);
 533 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 534                               uint64_t offset, unsigned size);
 535 void cik_emit_prefetch_L2(struct si_context *sctx);
 536 void si_init_cp_dma_functions(struct si_context *sctx);
 537
 538 /* si_debug.c */
 539 void si_auto_log_cs(void *data, struct u_log_context *log);
 540 void si_log_hw_flush(struct si_context *sctx);
 541 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
 542 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
 543 void si_init_debug_functions(struct si_context *sctx);
 544 void si_check_vm_faults(struct r600_common_context *ctx,
 545                         struct radeon_saved_cs *saved, enum ring_type ring);
 546 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
 547
 548 /* si_dma.c */
 549 void si_init_dma_functions(struct si_context *sctx);
 550
 551 /* si_hw_context.c */
 552 void si_destroy_saved_cs(struct si_saved_cs *scs);
 553 void si_context_gfx_flush(void *context, unsigned flags,
 554                           struct pipe_fence_handle **fence);
 555 void si_begin_new_cs(struct si_context *ctx);
 556 void si_need_cs_space(struct si_context *ctx);
 557
 558 /* si_compute.c */
 559 void si_init_compute_functions(struct si_context *sctx);
 560
 561 /* si_perfcounters.c */
 562 void si_init_perfcounters(struct si_screen *screen);
 563
 564 /* si_uvd.c */
 565 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 566                                                const struct pipe_video_codec *templ);
 567
 568 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 569                                                  const struct pipe_video_buffer *tmpl);
 570
 571 /* si_viewport.c */
 572 void si_update_vs_writes_viewport_index(struct si_context *ctx);
 573 void si_init_viewport_functions(struct si_context *ctx);
 574
 575
 576 /*
 577  * common helpers
 578  */
 579
 580 static inline void
 581 si_invalidate_draw_sh_constants(struct si_context *sctx)
 582 {
 583         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 584 }
 585
 586 static inline void
 587 si_set_atom_dirty(struct si_context *sctx,
 588                   struct r600_atom *atom, bool dirty)
 589 {
 590         unsigned bit = 1 << atom->id;
 591
 592         if (dirty)
 593                 sctx->dirty_atoms |= bit;
 594         else
 595                 sctx->dirty_atoms &= ~bit;
 596 }
 597
 598 static inline bool
 599 si_is_atom_dirty(struct si_context *sctx,
 600                   struct r600_atom *atom)
 601 {
 602         unsigned bit = 1 << atom->id;
 603
 604         return sctx->dirty_atoms & bit;
 605 }
 606
 607 static inline void
 608 si_mark_atom_dirty(struct si_context *sctx,
 609                    struct r600_atom *atom)
 610 {
 611         si_set_atom_dirty(sctx, atom, true);
 612 }
 613
 614 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
 615 {
 616         if (sctx->gs_shader.cso)
 617                 return &sctx->gs_shader;
 618         if (sctx->tes_shader.cso)
 619                 return &sctx->tes_shader;
 620
 621         return &sctx->vs_shader;
 622 }
 623
 624 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 625 {
 626         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 627
 628         return vs->cso ? &vs->cso->info : NULL;
 629 }
 630
 631 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 632 {
 633         if (sctx->gs_shader.cso)
 634                 return sctx->gs_shader.cso->gs_copy_shader;
 635
 636         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 637         return vs->current ? vs->current : NULL;
 638 }
 639
 640 static inline unsigned
 641 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
 642 {
 643         unsigned alignment, tcc_cache_line_size;
 644
 645         /* If the upload size is less than the cache line size (e.g. 16, 32),
 646          * the whole thing will fit into a cache line if we align it to its size.
 647          * The idea is that multiple small uploads can share a cache line.
 648          * If the upload size is greater, align it to the cache line size.
 649          */
 650         alignment = util_next_power_of_two(upload_size);
 651         tcc_cache_line_size = sctx->screen->b.info.tcc_cache_line_size;
 652         return MIN2(alignment, tcc_cache_line_size);
 653 }
 654
 655 static inline void
 656 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
 657 {
 658         if (pipe_reference(&(*dst)->reference, &src->reference))
 659                 si_destroy_saved_cs(*dst);
 660
 661         *dst = src;
 662 }
 663
 664 static inline void
 665 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 666                            bool shaders_read_metadata)
 667 {
 668         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
 669                          SI_CONTEXT_INV_VMEM_L1;
 670
 671         if (sctx->b.chip_class >= GFX9) {
 672                 /* Single-sample color is coherent with shaders on GFX9, but
 673                  * L2 metadata must be flushed if shaders read metadata.
 674                  * (DCC, CMASK).
 675                  */
 676                 if (num_samples >= 2)
 677                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 678                 else if (shaders_read_metadata)
 679                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 680         } else {
 681                 /* SI-CI-VI */
 682                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 683         }
 684 }
 685
 686 static inline void
 687 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 688                            bool include_stencil, bool shaders_read_metadata)
 689 {
 690         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
 691                          SI_CONTEXT_INV_VMEM_L1;
 692
 693         if (sctx->b.chip_class >= GFX9) {
 694                 /* Single-sample depth (not stencil) is coherent with shaders
 695                  * on GFX9, but L2 metadata must be flushed if shaders read
 696                  * metadata.
 697                  */
 698                 if (num_samples >= 2 || include_stencil)
 699                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 700                 else if (shaders_read_metadata)
 701                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 702         } else {
 703                 /* SI-CI-VI */
 704                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 705         }
 706 }
 707
 708 #endif