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radeonsi: implement mechanism for IBs without partial flushes at the end (v6)
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29
30 #include "util/u_dynarray.h"
31 #include "util/u_idalloc.h"
32
33 #ifdef PIPE_ARCH_BIG_ENDIAN
34 #define SI_BIG_ENDIAN 1
35 #else
36 #define SI_BIG_ENDIAN 0
37 #endif
38
39 #define ATI_VENDOR_ID 0x1002
40
41 #define SI_NOT_QUERY 0xffffffff
42
43 /* The base vertex and primitive restart can be any number, but we must pick
44 * one which will mean "unknown" for the purpose of state tracking and
45 * the number shouldn't be a commonly-used one. */
46 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
47 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
48 #define SI_NUM_SMOOTH_AA_SAMPLES 8
49 #define SI_GS_PER_ES 128
50 /* Alignment for optimal CP DMA performance. */
51 #define SI_CPDMA_ALIGNMENT 32
52
53 /* Pipeline & streamout query controls. */
54 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
55 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
56 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
57 /* Instruction cache. */
58 #define SI_CONTEXT_INV_ICACHE (1 << 3)
59 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
60 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
61 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
62 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
63 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
64 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
65 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
66 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
67 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
68 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
69 * a CB or DB flush. */
70 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
71 /* Framebuffer caches. */
72 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
73 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
74 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
75 /* Engine synchronization. */
76 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
77 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
78 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
79 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
80 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
81
82 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
83 #define SI_PREFETCH_LS (1 << 1)
84 #define SI_PREFETCH_HS (1 << 2)
85 #define SI_PREFETCH_ES (1 << 3)
86 #define SI_PREFETCH_GS (1 << 4)
87 #define SI_PREFETCH_VS (1 << 5)
88 #define SI_PREFETCH_PS (1 << 6)
89
90 #define SI_MAX_BORDER_COLORS 4096
91 #define SI_MAX_VIEWPORTS 16
92 #define SIX_BITS 0x3F
93 #define SI_MAP_BUFFER_ALIGNMENT 64
94 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
95
96 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
97 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
98 #define SI_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
99 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
100 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
101 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
102 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
103
104 /* Debug flags. */
105 enum {
106 /* Shader logging options: */
107 DBG_VS = PIPE_SHADER_VERTEX,
108 DBG_PS = PIPE_SHADER_FRAGMENT,
109 DBG_GS = PIPE_SHADER_GEOMETRY,
110 DBG_TCS = PIPE_SHADER_TESS_CTRL,
111 DBG_TES = PIPE_SHADER_TESS_EVAL,
112 DBG_CS = PIPE_SHADER_COMPUTE,
113 DBG_NO_IR,
114 DBG_NO_TGSI,
115 DBG_NO_ASM,
116 DBG_PREOPT_IR,
117
118 /* Shader compiler options the shader cache should be aware of: */
119 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
120 DBG_UNSAFE_MATH,
121 DBG_SI_SCHED,
122
123 /* Shader compiler options (with no effect on the shader cache): */
124 DBG_CHECK_IR,
125 DBG_NIR,
126 DBG_MONOLITHIC_SHADERS,
127 DBG_NO_OPT_VARIANT,
128
129 /* Information logging options: */
130 DBG_INFO,
131 DBG_TEX,
132 DBG_COMPUTE,
133 DBG_VM,
134
135 /* Driver options: */
136 DBG_FORCE_DMA,
137 DBG_NO_ASYNC_DMA,
138 DBG_NO_WC,
139 DBG_CHECK_VM,
140 DBG_RESERVE_VMID,
141
142 /* 3D engine options: */
143 DBG_SWITCH_ON_EOP,
144 DBG_NO_OUT_OF_ORDER,
145 DBG_NO_DPBB,
146 DBG_NO_DFSM,
147 DBG_DPBB,
148 DBG_DFSM,
149 DBG_NO_HYPERZ,
150 DBG_NO_RB_PLUS,
151 DBG_NO_2D_TILING,
152 DBG_NO_TILING,
153 DBG_NO_DCC,
154 DBG_NO_DCC_CLEAR,
155 DBG_NO_DCC_FB,
156 DBG_NO_DCC_MSAA,
157 DBG_DCC_MSAA,
158 DBG_NO_FMASK,
159
160 /* Tests: */
161 DBG_TEST_DMA,
162 DBG_TEST_VMFAULT_CP,
163 DBG_TEST_VMFAULT_SDMA,
164 DBG_TEST_VMFAULT_SHADER,
165 };
166
167 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
168 #define DBG(name) (1ull << DBG_##name)
169
170 struct si_compute;
171 struct hash_table;
172 struct u_suballocator;
173
174 struct si_screen {
175 struct pipe_screen b;
176 struct radeon_winsys *ws;
177 struct disk_cache *disk_shader_cache;
178
179 struct radeon_info info;
180 uint64_t debug_flags;
181 char renderer_string[100];
182
183 unsigned gs_table_depth;
184 unsigned tess_offchip_block_dw_size;
185 unsigned tess_offchip_ring_size;
186 unsigned tess_factor_ring_size;
187 unsigned vgt_hs_offchip_param;
188 bool has_clear_state;
189 bool has_distributed_tess;
190 bool has_draw_indirect_multi;
191 bool has_out_of_order_rast;
192 bool assume_no_z_fights;
193 bool commutative_blend_add;
194 bool clear_db_cache_before_clear;
195 bool has_msaa_sample_loc_bug;
196 bool has_ls_vgpr_init_bug;
197 bool dpbb_allowed;
198 bool dfsm_allowed;
199 bool llvm_has_working_vgpr_indexing;
200
201 /* Whether shaders are monolithic (1-part) or separate (3-part). */
202 bool use_monolithic_shaders;
203 bool record_llvm_ir;
204 bool has_rbplus; /* if RB+ registers exist */
205 bool rbplus_allowed; /* if RB+ is allowed */
206 bool dcc_msaa_allowed;
207 bool cpdma_prefetch_writes_memory;
208
209 struct slab_parent_pool pool_transfers;
210
211 /* Texture filter settings. */
212 int force_aniso; /* -1 = disabled */
213
214 /* Auxiliary context. Mainly used to initialize resources.
215 * It must be locked prior to using and flushed before unlocking. */
216 struct pipe_context *aux_context;
217 mtx_t aux_context_lock;
218
219 /* This must be in the screen, because UE4 uses one context for
220 * compilation and another one for rendering.
221 */
222 unsigned num_compilations;
223 /* Along with ST_DEBUG=precompile, this should show if applications
224 * are loading shaders on demand. This is a monotonic counter.
225 */
226 unsigned num_shaders_created;
227 unsigned num_shader_cache_hits;
228
229 /* GPU load thread. */
230 mtx_t gpu_load_mutex;
231 thrd_t gpu_load_thread;
232 union si_mmio_counters mmio_counters;
233 volatile unsigned gpu_load_stop_thread; /* bool */
234
235 /* Performance counters. */
236 struct si_perfcounters *perfcounters;
237
238 /* If pipe_screen wants to recompute and re-emit the framebuffer,
239 * sampler, and image states of all contexts, it should atomically
240 * increment this.
241 *
242 * Each context will compare this with its own last known value of
243 * the counter before drawing and re-emit the states accordingly.
244 */
245 unsigned dirty_tex_counter;
246
247 /* Atomically increment this counter when an existing texture's
248 * metadata is enabled or disabled in a way that requires changing
249 * contexts' compressed texture binding masks.
250 */
251 unsigned compressed_colortex_counter;
252
253 struct {
254 /* Context flags to set so that all writes from earlier jobs
255 * in the CP are seen by L2 clients.
256 */
257 unsigned cp_to_L2;
258
259 /* Context flags to set so that all writes from earlier jobs
260 * that end in L2 are seen by CP.
261 */
262 unsigned L2_to_cp;
263 } barrier_flags;
264
265 mtx_t shader_parts_mutex;
266 struct si_shader_part *vs_prologs;
267 struct si_shader_part *tcs_epilogs;
268 struct si_shader_part *gs_prologs;
269 struct si_shader_part *ps_prologs;
270 struct si_shader_part *ps_epilogs;
271
272 /* Shader cache in memory.
273 *
274 * Design & limitations:
275 * - The shader cache is per screen (= per process), never saved to
276 * disk, and skips redundant shader compilations from TGSI to bytecode.
277 * - It can only be used with one-variant-per-shader support, in which
278 * case only the main (typically middle) part of shaders is cached.
279 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
280 * variants of VS and TES are cached, so LS and ES aren't.
281 * - GS and CS aren't cached, but it's certainly possible to cache
282 * those as well.
283 */
284 mtx_t shader_cache_mutex;
285 struct hash_table *shader_cache;
286
287 /* Shader compiler queue for multithreaded compilation. */
288 struct util_queue shader_compiler_queue;
289 /* Use at most 3 normal compiler threads on quadcore and better.
290 * Hyperthreaded CPUs report the number of threads, but we want
291 * the number of cores. */
292 LLVMTargetMachineRef tm[3]; /* used by the queue only */
293
294 struct util_queue shader_compiler_queue_low_priority;
295 /* Use at most 2 low priority threads on quadcore and better.
296 * We want to minimize the impact on multithreaded Mesa. */
297 LLVMTargetMachineRef tm_low_priority[2]; /* at most 2 threads */
298 };
299
300 struct si_blend_color {
301 struct r600_atom atom;
302 struct pipe_blend_color state;
303 bool any_nonzeros;
304 };
305
306 struct si_sampler_view {
307 struct pipe_sampler_view base;
308 /* [0..7] = image descriptor
309 * [4..7] = buffer descriptor */
310 uint32_t state[8];
311 uint32_t fmask_state[8];
312 const struct legacy_surf_level *base_level_info;
313 ubyte base_level;
314 ubyte block_width;
315 bool is_stencil_sampler;
316 bool is_integer;
317 bool dcc_incompatible;
318 };
319
320 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
321
322 struct si_sampler_state {
323 #ifdef DEBUG
324 unsigned magic;
325 #endif
326 uint32_t val[4];
327 uint32_t integer_val[4];
328 uint32_t upgraded_depth_val[4];
329 };
330
331 struct si_cs_shader_state {
332 struct si_compute *program;
333 struct si_compute *emitted_program;
334 unsigned offset;
335 bool initialized;
336 bool uses_scratch;
337 };
338
339 struct si_samplers {
340 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
341 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
342
343 /* The i-th bit is set if that element is enabled (non-NULL resource). */
344 unsigned enabled_mask;
345 uint32_t needs_depth_decompress_mask;
346 uint32_t needs_color_decompress_mask;
347 };
348
349 struct si_images {
350 struct pipe_image_view views[SI_NUM_IMAGES];
351 uint32_t needs_color_decompress_mask;
352 unsigned enabled_mask;
353 };
354
355 struct si_framebuffer {
356 struct r600_atom atom;
357 struct pipe_framebuffer_state state;
358 unsigned colorbuf_enabled_4bit;
359 unsigned spi_shader_col_format;
360 unsigned spi_shader_col_format_alpha;
361 unsigned spi_shader_col_format_blend;
362 unsigned spi_shader_col_format_blend_alpha;
363 ubyte nr_samples:5; /* at most 16xAA */
364 ubyte log_samples:3; /* at most 4 = 16xAA */
365 ubyte compressed_cb_mask;
366 ubyte uncompressed_cb_mask;
367 ubyte color_is_int8;
368 ubyte color_is_int10;
369 ubyte dirty_cbufs;
370 bool dirty_zsbuf;
371 bool any_dst_linear;
372 bool CB_has_shader_readable_metadata;
373 bool DB_has_shader_readable_metadata;
374 };
375
376 struct si_signed_scissor {
377 int minx;
378 int miny;
379 int maxx;
380 int maxy;
381 };
382
383 struct si_scissors {
384 struct r600_atom atom;
385 unsigned dirty_mask;
386 struct pipe_scissor_state states[SI_MAX_VIEWPORTS];
387 };
388
389 struct si_viewports {
390 struct r600_atom atom;
391 unsigned dirty_mask;
392 unsigned depth_range_dirty_mask;
393 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
394 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
395 };
396
397 struct si_clip_state {
398 struct r600_atom atom;
399 struct pipe_clip_state state;
400 bool any_nonzeros;
401 };
402
403 struct si_sample_locs {
404 struct r600_atom atom;
405 unsigned nr_samples;
406 };
407
408 struct si_sample_mask {
409 struct r600_atom atom;
410 uint16_t sample_mask;
411 };
412
413 struct si_streamout_target {
414 struct pipe_stream_output_target b;
415
416 /* The buffer where BUFFER_FILLED_SIZE is stored. */
417 struct r600_resource *buf_filled_size;
418 unsigned buf_filled_size_offset;
419 bool buf_filled_size_valid;
420
421 unsigned stride_in_dw;
422 };
423
424 struct si_streamout {
425 struct r600_atom begin_atom;
426 bool begin_emitted;
427
428 unsigned enabled_mask;
429 unsigned num_targets;
430 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
431
432 unsigned append_bitmask;
433 bool suspended;
434
435 /* External state which comes from the vertex shader,
436 * it must be set explicitly when binding a shader. */
437 uint16_t *stride_in_dw;
438 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
439
440 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
441 unsigned hw_enabled_mask;
442
443 /* The state of VGT_STRMOUT_(CONFIG|EN). */
444 struct r600_atom enable_atom;
445 bool streamout_enabled;
446 bool prims_gen_query_enabled;
447 int num_prims_gen_queries;
448 };
449
450 /* A shader state consists of the shader selector, which is a constant state
451 * object shared by multiple contexts and shouldn't be modified, and
452 * the current shader variant selected for this context.
453 */
454 struct si_shader_ctx_state {
455 struct si_shader_selector *cso;
456 struct si_shader *current;
457 };
458
459 #define SI_NUM_VGT_PARAM_KEY_BITS 12
460 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
461
462 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
463 * Some fields are set by state-change calls, most are set by draw_vbo.
464 */
465 union si_vgt_param_key {
466 struct {
467 #ifdef PIPE_ARCH_LITTLE_ENDIAN
468 unsigned prim:4;
469 unsigned uses_instancing:1;
470 unsigned multi_instances_smaller_than_primgroup:1;
471 unsigned primitive_restart:1;
472 unsigned count_from_stream_output:1;
473 unsigned line_stipple_enabled:1;
474 unsigned uses_tess:1;
475 unsigned tess_uses_prim_id:1;
476 unsigned uses_gs:1;
477 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
478 #else /* PIPE_ARCH_BIG_ENDIAN */
479 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
480 unsigned uses_gs:1;
481 unsigned tess_uses_prim_id:1;
482 unsigned uses_tess:1;
483 unsigned line_stipple_enabled:1;
484 unsigned count_from_stream_output:1;
485 unsigned primitive_restart:1;
486 unsigned multi_instances_smaller_than_primgroup:1;
487 unsigned uses_instancing:1;
488 unsigned prim:4;
489 #endif
490 } u;
491 uint32_t index;
492 };
493
494 struct si_texture_handle
495 {
496 unsigned desc_slot;
497 bool desc_dirty;
498 struct pipe_sampler_view *view;
499 struct si_sampler_state sstate;
500 };
501
502 struct si_image_handle
503 {
504 unsigned desc_slot;
505 bool desc_dirty;
506 struct pipe_image_view view;
507 };
508
509 struct si_saved_cs {
510 struct pipe_reference reference;
511 struct si_context *ctx;
512 struct radeon_saved_cs gfx;
513 struct r600_resource *trace_buf;
514 unsigned trace_id;
515
516 unsigned gfx_last_dw;
517 bool flushed;
518 int64_t time_flush;
519 };
520
521 struct si_context {
522 struct pipe_context b; /* base class */
523
524 enum radeon_family family;
525 enum chip_class chip_class;
526
527 struct radeon_winsys *ws;
528 struct radeon_winsys_ctx *ctx;
529 struct radeon_winsys_cs *gfx_cs;
530 struct radeon_winsys_cs *dma_cs;
531 struct pipe_fence_handle *last_gfx_fence;
532 struct pipe_fence_handle *last_sdma_fence;
533 struct r600_resource *eop_bug_scratch;
534 struct u_upload_mgr *cached_gtt_allocator;
535 struct threaded_context *tc;
536 struct u_suballocator *allocator_zeroed_memory;
537 struct slab_child_pool pool_transfers;
538 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
539 struct pipe_device_reset_callback device_reset_callback;
540 struct u_log_context *log;
541 void *query_result_shader;
542 struct blitter_context *blitter;
543 void *custom_dsa_flush;
544 void *custom_blend_resolve;
545 void *custom_blend_fmask_decompress;
546 void *custom_blend_eliminate_fastclear;
547 void *custom_blend_dcc_decompress;
548 void *vs_blit_pos;
549 void *vs_blit_pos_layered;
550 void *vs_blit_color;
551 void *vs_blit_color_layered;
552 void *vs_blit_texcoord;
553 struct si_screen *screen;
554 struct pipe_debug_callback debug;
555 LLVMTargetMachineRef tm; /* only non-threaded compilation */
556 struct si_shader_ctx_state fixed_func_tcs_shader;
557 struct r600_resource *wait_mem_scratch;
558 unsigned wait_mem_number;
559 uint16_t prefetch_L2_mask;
560
561 bool gfx_flush_in_progress:1;
562 bool gfx_last_ib_is_busy:1;
563 bool compute_is_busy:1;
564
565 unsigned num_gfx_cs_flushes;
566 unsigned initial_gfx_cs_size;
567 unsigned gpu_reset_counter;
568 unsigned last_dirty_tex_counter;
569 unsigned last_compressed_colortex_counter;
570 unsigned last_num_draw_calls;
571 unsigned flags; /* flush flags */
572 /* Current unaccounted memory usage. */
573 uint64_t vram;
574 uint64_t gtt;
575
576 /* Atoms (direct states). */
577 union si_state_atoms atoms;
578 unsigned dirty_atoms; /* mask */
579 /* PM4 states (precomputed immutable states) */
580 unsigned dirty_states;
581 union si_state queued;
582 union si_state emitted;
583
584 /* Atom declarations. */
585 struct si_framebuffer framebuffer;
586 struct si_sample_locs msaa_sample_locs;
587 struct r600_atom db_render_state;
588 struct r600_atom dpbb_state;
589 struct r600_atom msaa_config;
590 struct si_sample_mask sample_mask;
591 struct r600_atom cb_render_state;
592 unsigned last_cb_target_mask;
593 struct si_blend_color blend_color;
594 struct r600_atom clip_regs;
595 struct si_clip_state clip_state;
596 struct si_shader_data shader_pointers;
597 struct si_stencil_ref stencil_ref;
598 struct r600_atom spi_map;
599 struct si_scissors scissors;
600 struct si_streamout streamout;
601 struct si_viewports viewports;
602
603 /* Precomputed states. */
604 struct si_pm4_state *init_config;
605 struct si_pm4_state *init_config_gs_rings;
606 bool init_config_has_vgt_flush;
607 struct si_pm4_state *vgt_shader_config[4];
608
609 /* shaders */
610 struct si_shader_ctx_state ps_shader;
611 struct si_shader_ctx_state gs_shader;
612 struct si_shader_ctx_state vs_shader;
613 struct si_shader_ctx_state tcs_shader;
614 struct si_shader_ctx_state tes_shader;
615 struct si_cs_shader_state cs_shader_state;
616
617 /* shader information */
618 struct si_vertex_elements *vertex_elements;
619 unsigned sprite_coord_enable;
620 bool flatshade;
621 bool do_update_shaders;
622
623 /* vertex buffer descriptors */
624 uint32_t *vb_descriptors_gpu_list;
625 struct r600_resource *vb_descriptors_buffer;
626 unsigned vb_descriptors_offset;
627
628 /* shader descriptors */
629 struct si_descriptors descriptors[SI_NUM_DESCS];
630 unsigned descriptors_dirty;
631 unsigned shader_pointers_dirty;
632 unsigned shader_needs_decompress_mask;
633 struct si_buffer_resources rw_buffers;
634 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
635 struct si_samplers samplers[SI_NUM_SHADERS];
636 struct si_images images[SI_NUM_SHADERS];
637
638 /* other shader resources */
639 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
640 struct pipe_resource *esgs_ring;
641 struct pipe_resource *gsvs_ring;
642 struct pipe_resource *tess_rings;
643 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
644 struct r600_resource *border_color_buffer;
645 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
646 unsigned border_color_count;
647 unsigned num_vs_blit_sgprs;
648 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
649
650 /* Vertex and index buffers. */
651 bool vertex_buffers_dirty;
652 bool vertex_buffer_pointer_dirty;
653 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
654
655 /* MSAA config state. */
656 int ps_iter_samples;
657 bool ps_uses_fbfetch;
658 bool smoothing_enabled;
659
660 /* DB render state. */
661 unsigned ps_db_shader_control;
662 unsigned dbcb_copy_sample;
663 bool dbcb_depth_copy_enabled:1;
664 bool dbcb_stencil_copy_enabled:1;
665 bool db_flush_depth_inplace:1;
666 bool db_flush_stencil_inplace:1;
667 bool db_depth_clear:1;
668 bool db_depth_disable_expclear:1;
669 bool db_stencil_clear:1;
670 bool db_stencil_disable_expclear:1;
671 bool occlusion_queries_disabled:1;
672 bool generate_mipmap_for_depth:1;
673
674 /* Emitted draw state. */
675 bool gs_tri_strip_adj_fix:1;
676 bool ls_vgpr_fix:1;
677 int last_index_size;
678 int last_base_vertex;
679 int last_start_instance;
680 int last_drawid;
681 int last_sh_base_reg;
682 int last_primitive_restart_en;
683 int last_restart_index;
684 int last_gs_out_prim;
685 int last_prim;
686 int last_multi_vgt_param;
687 int last_rast_prim;
688 unsigned last_sc_line_stipple;
689 unsigned current_vs_state;
690 unsigned last_vs_state;
691 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
692
693 /* Scratch buffer */
694 struct r600_atom scratch_state;
695 struct r600_resource *scratch_buffer;
696 unsigned scratch_waves;
697 unsigned spi_tmpring_size;
698
699 struct r600_resource *compute_scratch_buffer;
700
701 /* Emitted derived tessellation state. */
702 /* Local shader (VS), or HS if LS-HS are merged. */
703 struct si_shader *last_ls;
704 struct si_shader_selector *last_tcs;
705 int last_num_tcs_input_cp;
706 int last_tes_sh_base;
707 bool last_tess_uses_primid;
708 unsigned last_num_patches;
709
710 /* Debug state. */
711 bool is_debug;
712 struct si_saved_cs *current_saved_cs;
713 uint64_t dmesg_timestamp;
714 unsigned apitrace_call_number;
715
716 /* Other state */
717 bool need_check_render_feedback;
718 bool decompression_enabled;
719
720 bool vs_writes_viewport_index;
721 bool vs_disables_clipping_viewport;
722
723 /* Precomputed IA_MULTI_VGT_PARAM */
724 union si_vgt_param_key ia_multi_vgt_param_key;
725 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
726
727 /* Bindless descriptors. */
728 struct si_descriptors bindless_descriptors;
729 struct util_idalloc bindless_used_slots;
730 unsigned num_bindless_descriptors;
731 bool bindless_descriptors_dirty;
732 bool graphics_bindless_pointer_dirty;
733 bool compute_bindless_pointer_dirty;
734
735 /* Allocated bindless handles */
736 struct hash_table *tex_handles;
737 struct hash_table *img_handles;
738
739 /* Resident bindless handles */
740 struct util_dynarray resident_tex_handles;
741 struct util_dynarray resident_img_handles;
742
743 /* Resident bindless handles which need decompression */
744 struct util_dynarray resident_tex_needs_color_decompress;
745 struct util_dynarray resident_img_needs_color_decompress;
746 struct util_dynarray resident_tex_needs_depth_decompress;
747
748 /* Bindless state */
749 bool uses_bindless_samplers;
750 bool uses_bindless_images;
751
752 /* MSAA sample locations.
753 * The first index is the sample index.
754 * The second index is the coordinate: X, Y. */
755 float sample_locations_1x[1][2];
756 float sample_locations_2x[2][2];
757 float sample_locations_4x[4][2];
758 float sample_locations_8x[8][2];
759 float sample_locations_16x[16][2];
760
761 /* Misc stats. */
762 unsigned num_draw_calls;
763 unsigned num_decompress_calls;
764 unsigned num_mrt_draw_calls;
765 unsigned num_prim_restart_calls;
766 unsigned num_spill_draw_calls;
767 unsigned num_compute_calls;
768 unsigned num_spill_compute_calls;
769 unsigned num_dma_calls;
770 unsigned num_cp_dma_calls;
771 unsigned num_vs_flushes;
772 unsigned num_ps_flushes;
773 unsigned num_cs_flushes;
774 unsigned num_cb_cache_flushes;
775 unsigned num_db_cache_flushes;
776 unsigned num_L2_invalidates;
777 unsigned num_L2_writebacks;
778 unsigned num_resident_handles;
779 uint64_t num_alloc_tex_transfer_bytes;
780 unsigned last_tex_ps_draw_ratio; /* for query */
781
782 /* Queries. */
783 /* Maintain the list of active queries for pausing between IBs. */
784 int num_occlusion_queries;
785 int num_perfect_occlusion_queries;
786 struct list_head active_queries;
787 unsigned num_cs_dw_queries_suspend;
788
789 /* Render condition. */
790 struct r600_atom render_cond_atom;
791 struct pipe_query *render_cond;
792 unsigned render_cond_mode;
793 bool render_cond_invert;
794 bool render_cond_force_off; /* for u_blitter */
795
796 /* Statistics gathering for the DCC enablement heuristic. It can't be
797 * in r600_texture because r600_texture can be shared by multiple
798 * contexts. This is for back buffers only. We shouldn't get too many
799 * of those.
800 *
801 * X11 DRI3 rotates among a finite set of back buffers. They should
802 * all fit in this array. If they don't, separate DCC might never be
803 * enabled by DCC stat gathering.
804 */
805 struct {
806 struct r600_texture *tex;
807 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
808 struct pipe_query *ps_stats[3];
809 /* If all slots are used and another slot is needed,
810 * the least recently used slot is evicted based on this. */
811 int64_t last_use_timestamp;
812 bool query_active;
813 } dcc_stats[5];
814
815 /* Copy one resource to another using async DMA. */
816 void (*dma_copy)(struct pipe_context *ctx,
817 struct pipe_resource *dst,
818 unsigned dst_level,
819 unsigned dst_x, unsigned dst_y, unsigned dst_z,
820 struct pipe_resource *src,
821 unsigned src_level,
822 const struct pipe_box *src_box);
823
824 void (*dma_clear_buffer)(struct si_context *sctx, struct pipe_resource *dst,
825 uint64_t offset, uint64_t size, unsigned value);
826 };
827
828 /* cik_sdma.c */
829 void cik_init_sdma_functions(struct si_context *sctx);
830
831 /* si_blit.c */
832 enum si_blitter_op /* bitmask */
833 {
834 SI_SAVE_TEXTURES = 1,
835 SI_SAVE_FRAMEBUFFER = 2,
836 SI_SAVE_FRAGMENT_STATE = 4,
837 SI_DISABLE_RENDER_COND = 8,
838 };
839
840 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
841 void si_blitter_end(struct si_context *sctx);
842 void si_init_blit_functions(struct si_context *sctx);
843 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
844 void si_resource_copy_region(struct pipe_context *ctx,
845 struct pipe_resource *dst,
846 unsigned dst_level,
847 unsigned dstx, unsigned dsty, unsigned dstz,
848 struct pipe_resource *src,
849 unsigned src_level,
850 const struct pipe_box *src_box);
851 void si_decompress_dcc(struct si_context *sctx, struct r600_texture *rtex);
852 void si_blit_decompress_depth(struct pipe_context *ctx,
853 struct r600_texture *texture,
854 struct r600_texture *staging,
855 unsigned first_level, unsigned last_level,
856 unsigned first_layer, unsigned last_layer,
857 unsigned first_sample, unsigned last_sample);
858
859 /* si_buffer.c */
860 bool si_rings_is_buffer_referenced(struct si_context *sctx,
861 struct pb_buffer *buf,
862 enum radeon_bo_usage usage);
863 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
864 struct r600_resource *resource,
865 unsigned usage);
866 void si_init_resource_fields(struct si_screen *sscreen,
867 struct r600_resource *res,
868 uint64_t size, unsigned alignment);
869 bool si_alloc_resource(struct si_screen *sscreen,
870 struct r600_resource *res);
871 struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
872 unsigned flags,
873 unsigned usage,
874 unsigned size,
875 unsigned alignment);
876 void si_replace_buffer_storage(struct pipe_context *ctx,
877 struct pipe_resource *dst,
878 struct pipe_resource *src);
879 void si_init_screen_buffer_functions(struct si_screen *sscreen);
880 void si_init_buffer_functions(struct si_context *sctx);
881
882 /* si_clear.c */
883 void vi_dcc_clear_level(struct si_context *sctx,
884 struct r600_texture *rtex,
885 unsigned level, unsigned clear_value);
886 void si_init_clear_functions(struct si_context *sctx);
887
888 /* si_cp_dma.c */
889 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
890 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
891 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
892 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
893 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
894 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
895 SI_CPDMA_SKIP_SYNC_AFTER | \
896 SI_CPDMA_SKIP_SYNC_BEFORE | \
897 SI_CPDMA_SKIP_GFX_SYNC | \
898 SI_CPDMA_SKIP_BO_LIST_UPDATE)
899
900 enum si_coherency {
901 SI_COHERENCY_NONE, /* no cache flushes needed */
902 SI_COHERENCY_SHADER,
903 SI_COHERENCY_CB_META,
904 };
905
906 void si_cp_dma_wait_for_idle(struct si_context *sctx);
907 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
908 uint64_t offset, uint64_t size, unsigned value,
909 enum si_coherency coher);
910 void si_copy_buffer(struct si_context *sctx,
911 struct pipe_resource *dst, struct pipe_resource *src,
912 uint64_t dst_offset, uint64_t src_offset, unsigned size,
913 unsigned user_flags);
914 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
915 uint64_t offset, unsigned size);
916 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
917 void si_init_cp_dma_functions(struct si_context *sctx);
918
919 /* si_debug.c */
920 void si_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
921 struct radeon_saved_cs *saved, bool get_buffer_list);
922 void si_clear_saved_cs(struct radeon_saved_cs *saved);
923 void si_destroy_saved_cs(struct si_saved_cs *scs);
924 void si_auto_log_cs(void *data, struct u_log_context *log);
925 void si_log_hw_flush(struct si_context *sctx);
926 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
927 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
928 void si_init_debug_functions(struct si_context *sctx);
929 void si_check_vm_faults(struct si_context *sctx,
930 struct radeon_saved_cs *saved, enum ring_type ring);
931 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
932
933 /* si_dma.c */
934 void si_init_dma_functions(struct si_context *sctx);
935
936 /* si_dma_cs.c */
937 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
938 struct r600_resource *dst, struct r600_resource *src);
939 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
940 struct pipe_fence_handle **fence);
941 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
942 uint64_t offset, uint64_t size, unsigned value);
943
944 /* si_fence.c */
945 void si_gfx_write_event_eop(struct si_context *ctx,
946 unsigned event, unsigned event_flags,
947 unsigned data_sel,
948 struct r600_resource *buf, uint64_t va,
949 uint32_t new_fence, unsigned query_type);
950 unsigned si_gfx_write_fence_dwords(struct si_screen *screen);
951 void si_gfx_wait_fence(struct si_context *ctx,
952 uint64_t va, uint32_t ref, uint32_t mask);
953 void si_init_fence_functions(struct si_context *ctx);
954 void si_init_screen_fence_functions(struct si_screen *screen);
955 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
956 struct tc_unflushed_batch_token *tc_token);
957
958 /* si_get.c */
959 const char *si_get_family_name(const struct si_screen *sscreen);
960 void si_init_screen_get_functions(struct si_screen *sscreen);
961
962 /* si_gfx_cs.c */
963 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
964 struct pipe_fence_handle **fence);
965 void si_begin_new_gfx_cs(struct si_context *ctx);
966 void si_need_gfx_cs_space(struct si_context *ctx);
967
968 /* r600_gpu_load.c */
969 void si_gpu_load_kill_thread(struct si_screen *sscreen);
970 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
971 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
972 uint64_t begin);
973
974 /* si_compute.c */
975 void si_init_compute_functions(struct si_context *sctx);
976
977 /* si_perfcounters.c */
978 void si_init_perfcounters(struct si_screen *screen);
979
980 /* si_pipe.c */
981 bool si_check_device_reset(struct si_context *sctx);
982
983 /* si_query.c */
984 void si_init_screen_query_functions(struct si_screen *sscreen);
985 void si_init_query_functions(struct si_context *sctx);
986 void si_suspend_queries(struct si_context *sctx);
987 void si_resume_queries(struct si_context *sctx);
988
989 /* si_test_dma.c */
990 void si_test_dma(struct si_screen *sscreen);
991
992 /* si_uvd.c */
993 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
994 const struct pipe_video_codec *templ);
995
996 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
997 const struct pipe_video_buffer *tmpl);
998
999 /* si_viewport.c */
1000 void si_update_vs_viewport_state(struct si_context *ctx);
1001 void si_init_viewport_functions(struct si_context *ctx);
1002
1003 /* r600_texture.c */
1004 bool si_prepare_for_dma_blit(struct si_context *sctx,
1005 struct r600_texture *rdst,
1006 unsigned dst_level, unsigned dstx,
1007 unsigned dsty, unsigned dstz,
1008 struct r600_texture *rsrc,
1009 unsigned src_level,
1010 const struct pipe_box *src_box);
1011 void si_texture_get_fmask_info(struct si_screen *sscreen,
1012 struct r600_texture *rtex,
1013 unsigned nr_samples,
1014 struct r600_fmask_info *out);
1015 void si_texture_get_cmask_info(struct si_screen *sscreen,
1016 struct r600_texture *rtex,
1017 struct r600_cmask_info *out);
1018 void si_eliminate_fast_color_clear(struct si_context *sctx,
1019 struct r600_texture *rtex);
1020 void si_texture_discard_cmask(struct si_screen *sscreen,
1021 struct r600_texture *rtex);
1022 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1023 struct pipe_resource *texture,
1024 struct r600_texture **staging);
1025 void si_print_texture_info(struct si_screen *sscreen,
1026 struct r600_texture *rtex, struct u_log_context *log);
1027 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1028 const struct pipe_resource *templ);
1029 bool vi_dcc_formats_compatible(enum pipe_format format1,
1030 enum pipe_format format2);
1031 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1032 unsigned level,
1033 enum pipe_format view_format);
1034 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1035 struct pipe_resource *tex,
1036 unsigned level,
1037 enum pipe_format view_format);
1038 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1039 struct pipe_resource *texture,
1040 const struct pipe_surface *templ,
1041 unsigned width0, unsigned height0,
1042 unsigned width, unsigned height);
1043 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1044 void vi_separate_dcc_try_enable(struct si_context *sctx,
1045 struct r600_texture *tex);
1046 void vi_separate_dcc_start_query(struct si_context *sctx,
1047 struct r600_texture *tex);
1048 void vi_separate_dcc_stop_query(struct si_context *sctx,
1049 struct r600_texture *tex);
1050 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1051 struct r600_texture *tex);
1052 bool si_texture_disable_dcc(struct si_context *sctx,
1053 struct r600_texture *rtex);
1054 void si_init_screen_texture_functions(struct si_screen *sscreen);
1055 void si_init_context_texture_functions(struct si_context *sctx);
1056
1057
1058 /*
1059 * common helpers
1060 */
1061
1062 static inline void
1063 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1064 {
1065 struct r600_resource *res = (struct r600_resource *)r;
1066
1067 if (res) {
1068 /* Add memory usage for need_gfx_cs_space */
1069 sctx->vram += res->vram_usage;
1070 sctx->gtt += res->gart_usage;
1071 }
1072 }
1073
1074 static inline void
1075 si_invalidate_draw_sh_constants(struct si_context *sctx)
1076 {
1077 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1078 }
1079
1080 static inline void
1081 si_set_atom_dirty(struct si_context *sctx,
1082 struct r600_atom *atom, bool dirty)
1083 {
1084 unsigned bit = 1 << atom->id;
1085
1086 if (dirty)
1087 sctx->dirty_atoms |= bit;
1088 else
1089 sctx->dirty_atoms &= ~bit;
1090 }
1091
1092 static inline bool
1093 si_is_atom_dirty(struct si_context *sctx,
1094 struct r600_atom *atom)
1095 {
1096 unsigned bit = 1 << atom->id;
1097
1098 return sctx->dirty_atoms & bit;
1099 }
1100
1101 static inline void
1102 si_mark_atom_dirty(struct si_context *sctx,
1103 struct r600_atom *atom)
1104 {
1105 si_set_atom_dirty(sctx, atom, true);
1106 }
1107
1108 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1109 {
1110 if (sctx->gs_shader.cso)
1111 return &sctx->gs_shader;
1112 if (sctx->tes_shader.cso)
1113 return &sctx->tes_shader;
1114
1115 return &sctx->vs_shader;
1116 }
1117
1118 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1119 {
1120 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1121
1122 return vs->cso ? &vs->cso->info : NULL;
1123 }
1124
1125 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1126 {
1127 if (sctx->gs_shader.cso)
1128 return sctx->gs_shader.cso->gs_copy_shader;
1129
1130 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1131 return vs->current ? vs->current : NULL;
1132 }
1133
1134 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1135 unsigned processor)
1136 {
1137 return sscreen->debug_flags & (1 << processor);
1138 }
1139
1140 static inline bool si_extra_shader_checks(struct si_screen *sscreen,
1141 unsigned processor)
1142 {
1143 return (sscreen->debug_flags & DBG(CHECK_IR)) ||
1144 si_can_dump_shader(sscreen, processor);
1145 }
1146
1147 static inline bool si_get_strmout_en(struct si_context *sctx)
1148 {
1149 return sctx->streamout.streamout_enabled ||
1150 sctx->streamout.prims_gen_query_enabled;
1151 }
1152
1153 static inline unsigned
1154 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1155 {
1156 unsigned alignment, tcc_cache_line_size;
1157
1158 /* If the upload size is less than the cache line size (e.g. 16, 32),
1159 * the whole thing will fit into a cache line if we align it to its size.
1160 * The idea is that multiple small uploads can share a cache line.
1161 * If the upload size is greater, align it to the cache line size.
1162 */
1163 alignment = util_next_power_of_two(upload_size);
1164 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1165 return MIN2(alignment, tcc_cache_line_size);
1166 }
1167
1168 static inline void
1169 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1170 {
1171 if (pipe_reference(&(*dst)->reference, &src->reference))
1172 si_destroy_saved_cs(*dst);
1173
1174 *dst = src;
1175 }
1176
1177 static inline void
1178 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1179 bool shaders_read_metadata)
1180 {
1181 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1182 SI_CONTEXT_INV_VMEM_L1;
1183
1184 if (sctx->chip_class >= GFX9) {
1185 /* Single-sample color is coherent with shaders on GFX9, but
1186 * L2 metadata must be flushed if shaders read metadata.
1187 * (DCC, CMASK).
1188 */
1189 if (num_samples >= 2)
1190 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1191 else if (shaders_read_metadata)
1192 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1193 } else {
1194 /* SI-CI-VI */
1195 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1196 }
1197 }
1198
1199 static inline void
1200 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1201 bool include_stencil, bool shaders_read_metadata)
1202 {
1203 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1204 SI_CONTEXT_INV_VMEM_L1;
1205
1206 if (sctx->chip_class >= GFX9) {
1207 /* Single-sample depth (not stencil) is coherent with shaders
1208 * on GFX9, but L2 metadata must be flushed if shaders read
1209 * metadata.
1210 */
1211 if (num_samples >= 2 || include_stencil)
1212 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1213 else if (shaders_read_metadata)
1214 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1215 } else {
1216 /* SI-CI-VI */
1217 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1218 }
1219 }
1220
1221 static inline bool
1222 si_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
1223 {
1224 return (stencil_sampler && tex->can_sample_s) ||
1225 (!stencil_sampler && tex->can_sample_z);
1226 }
1227
1228 static inline bool
1229 si_htile_enabled(struct r600_texture *tex, unsigned level)
1230 {
1231 return tex->htile_offset && level == 0;
1232 }
1233
1234 static inline bool
1235 vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level)
1236 {
1237 assert(!tex->tc_compatible_htile || tex->htile_offset);
1238 return tex->tc_compatible_htile && level == 0;
1239 }
1240
1241 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1242 {
1243 if (sctx->ps_uses_fbfetch)
1244 return sctx->framebuffer.nr_samples;
1245
1246 return sctx->ps_iter_samples;
1247 }
1248
1249 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1250 {
1251 if (sctx->queued.named.rasterizer->rasterizer_discard)
1252 return 0;
1253
1254 struct si_shader_selector *ps = sctx->ps_shader.cso;
1255 if (!ps)
1256 return 0;
1257
1258 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1259 sctx->queued.named.blend->cb_target_mask;
1260
1261 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1262 colormask &= ps->colors_written_4bit;
1263 else if (!ps->colors_written_4bit)
1264 colormask = 0; /* color0 writes all cbufs, but it's not written */
1265
1266 return colormask;
1267 }
1268
1269 /**
1270 * Return true if there is enough memory in VRAM and GTT for the buffers
1271 * added so far.
1272 *
1273 * \param vram VRAM memory size not added to the buffer list yet
1274 * \param gtt GTT memory size not added to the buffer list yet
1275 */
1276 static inline bool
1277 radeon_cs_memory_below_limit(struct si_screen *screen,
1278 struct radeon_winsys_cs *cs,
1279 uint64_t vram, uint64_t gtt)
1280 {
1281 vram += cs->used_vram;
1282 gtt += cs->used_gart;
1283
1284 /* Anything that goes above the VRAM size should go to GTT. */
1285 if (vram > screen->info.vram_size)
1286 gtt += vram - screen->info.vram_size;
1287
1288 /* Now we just need to check if we have enough GTT. */
1289 return gtt < screen->info.gart_size * 0.7;
1290 }
1291
1292 /**
1293 * Add a buffer to the buffer list for the given command stream (CS).
1294 *
1295 * All buffers used by a CS must be added to the list. This tells the kernel
1296 * driver which buffers are used by GPU commands. Other buffers can
1297 * be swapped out (not accessible) during execution.
1298 *
1299 * The buffer list becomes empty after every context flush and must be
1300 * rebuilt.
1301 */
1302 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1303 struct radeon_winsys_cs *cs,
1304 struct r600_resource *rbo,
1305 enum radeon_bo_usage usage,
1306 enum radeon_bo_priority priority)
1307 {
1308 assert(usage);
1309 sctx->ws->cs_add_buffer(
1310 cs, rbo->buf,
1311 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1312 rbo->domains, priority);
1313 }
1314
1315 /**
1316 * Same as above, but also checks memory usage and flushes the context
1317 * accordingly.
1318 *
1319 * When this SHOULD NOT be used:
1320 *
1321 * - if si_context_add_resource_size has been called for the buffer
1322 * followed by *_need_cs_space for checking the memory usage
1323 *
1324 * - if si_need_dma_space has been called for the buffer
1325 *
1326 * - when emitting state packets and draw packets (because preceding packets
1327 * can't be re-emitted at that point)
1328 *
1329 * - if shader resource "enabled_mask" is not up-to-date or there is
1330 * a different constraint disallowing a context flush
1331 */
1332 static inline void
1333 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1334 struct r600_resource *rbo,
1335 enum radeon_bo_usage usage,
1336 enum radeon_bo_priority priority,
1337 bool check_mem)
1338 {
1339 if (check_mem &&
1340 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1341 sctx->vram + rbo->vram_usage,
1342 sctx->gtt + rbo->gart_usage))
1343 si_flush_gfx_cs(sctx, PIPE_FLUSH_ASYNC, NULL);
1344
1345 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, rbo, usage, priority);
1346 }
1347
1348 #define PRINT_ERR(fmt, args...) \
1349 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1350
1351 #endif