src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef SI_PIPE_H
  24 #define SI_PIPE_H
  25
  26 #include "si_shader.h"
  27
  28 #include "util/u_dynarray.h"
  29 #include "util/u_idalloc.h"
  30
  31 #ifdef PIPE_ARCH_BIG_ENDIAN
  32 #define SI_BIG_ENDIAN 1
  33 #else
  34 #define SI_BIG_ENDIAN 0
  35 #endif
  36
  37 #define ATI_VENDOR_ID 0x1002
  38
  39 #define SI_NOT_QUERY            0xffffffff
  40
  41 /* The base vertex and primitive restart can be any number, but we must pick
  42  * one which will mean "unknown" for the purpose of state tracking and
  43  * the number shouldn't be a commonly-used one. */
  44 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  45 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  46 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  47 #define SI_GS_PER_ES 128
  48 /* Alignment for optimal CP DMA performance. */
  49 #define SI_CPDMA_ALIGNMENT      32
  50
  51 /* Pipeline & streamout query controls. */
  52 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
  53 #define SI_CONTEXT_STOP_PIPELINE_STATS  (1 << 1)
  54 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
  55 /* Instruction cache. */
  56 #define SI_CONTEXT_INV_ICACHE           (1 << 3)
  57 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  58 #define SI_CONTEXT_INV_SMEM_L1          (1 << 4)
  59 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  60 #define SI_CONTEXT_INV_VMEM_L1          (1 << 5)
  61 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  62 #define SI_CONTEXT_INV_GLOBAL_L2        (1 << 6)
  63 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  64  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
  65 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2  (1 << 7)
  66 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
  67  * a CB or DB flush. */
  68 #define SI_CONTEXT_INV_L2_METADATA      (1 << 8)
  69 /* Framebuffer caches. */
  70 #define SI_CONTEXT_FLUSH_AND_INV_DB     (1 << 9)
  71 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
  72 #define SI_CONTEXT_FLUSH_AND_INV_CB     (1 << 11)
  73 /* Engine synchronization. */
  74 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (1 << 12)
  75 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (1 << 13)
  76 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (1 << 14)
  77 #define SI_CONTEXT_VGT_FLUSH            (1 << 15)
  78 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (1 << 16)
  79
  80 #define SI_PREFETCH_VBO_DESCRIPTORS     (1 << 0)
  81 #define SI_PREFETCH_LS                  (1 << 1)
  82 #define SI_PREFETCH_HS                  (1 << 2)
  83 #define SI_PREFETCH_ES                  (1 << 3)
  84 #define SI_PREFETCH_GS                  (1 << 4)
  85 #define SI_PREFETCH_VS                  (1 << 5)
  86 #define SI_PREFETCH_PS                  (1 << 6)
  87
  88 #define SI_MAX_BORDER_COLORS    4096
  89 #define SI_MAX_VIEWPORTS        16
  90 #define SIX_BITS                0x3F
  91
  92 struct si_compute;
  93 struct hash_table;
  94 struct u_suballocator;
  95
  96 struct si_screen {
  97         struct r600_common_screen       b;
  98         unsigned                        gs_table_depth;
  99         unsigned                        tess_offchip_block_dw_size;
 100         bool                            has_clear_state;
 101         bool                            has_distributed_tess;
 102         bool                            has_draw_indirect_multi;
 103         bool                            has_out_of_order_rast;
 104         bool                            assume_no_z_fights;
 105         bool                            commutative_blend_add;
 106         bool                            clear_db_cache_before_clear;
 107         bool                            has_msaa_sample_loc_bug;
 108         bool                            has_ls_vgpr_init_bug;
 109         bool                            dpbb_allowed;
 110         bool                            dfsm_allowed;
 111         bool                            llvm_has_working_vgpr_indexing;
 112
 113         /* Whether shaders are monolithic (1-part) or separate (3-part). */
 114         bool                            use_monolithic_shaders;
 115         bool                            record_llvm_ir;
 116
 117         mtx_t                   shader_parts_mutex;
 118         struct si_shader_part           *vs_prologs;
 119         struct si_shader_part           *tcs_epilogs;
 120         struct si_shader_part           *gs_prologs;
 121         struct si_shader_part           *ps_prologs;
 122         struct si_shader_part           *ps_epilogs;
 123
 124         /* Shader cache in memory.
 125          *
 126          * Design & limitations:
 127          * - The shader cache is per screen (= per process), never saved to
 128          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 129          * - It can only be used with one-variant-per-shader support, in which
 130          *   case only the main (typically middle) part of shaders is cached.
 131          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 132          *   variants of VS and TES are cached, so LS and ES aren't.
 133          * - GS and CS aren't cached, but it's certainly possible to cache
 134          *   those as well.
 135          */
 136         mtx_t                   shader_cache_mutex;
 137         struct hash_table               *shader_cache;
 138
 139         /* Shader compiler queue for multithreaded compilation. */
 140         struct util_queue               shader_compiler_queue;
 141         /* Use at most 3 normal compiler threads on quadcore and better.
 142          * Hyperthreaded CPUs report the number of threads, but we want
 143          * the number of cores. */
 144         LLVMTargetMachineRef            tm[3]; /* used by the queue only */
 145
 146         struct util_queue               shader_compiler_queue_low_priority;
 147         /* Use at most 2 low priority threads on quadcore and better.
 148          * We want to minimize the impact on multithreaded Mesa. */
 149         LLVMTargetMachineRef            tm_low_priority[2]; /* at most 2 threads */
 150 };
 151
 152 struct si_blend_color {
 153         struct r600_atom                atom;
 154         struct pipe_blend_color         state;
 155         bool                            any_nonzeros;
 156 };
 157
 158 struct si_sampler_view {
 159         struct pipe_sampler_view        base;
 160         /* [0..7] = image descriptor
 161          * [4..7] = buffer descriptor */
 162         uint32_t                        state[8];
 163         uint32_t                        fmask_state[8];
 164         const struct legacy_surf_level  *base_level_info;
 165         ubyte                           base_level;
 166         ubyte                           block_width;
 167         bool is_stencil_sampler;
 168         bool is_integer;
 169         bool dcc_incompatible;
 170 };
 171
 172 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
 173
 174 struct si_sampler_state {
 175 #ifdef DEBUG
 176         unsigned                        magic;
 177 #endif
 178         uint32_t                        val[4];
 179         uint32_t                        integer_val[4];
 180         uint32_t                        upgraded_depth_val[4];
 181 };
 182
 183 struct si_cs_shader_state {
 184         struct si_compute               *program;
 185         struct si_compute               *emitted_program;
 186         unsigned                        offset;
 187         bool                            initialized;
 188         bool                            uses_scratch;
 189 };
 190
 191 struct si_samplers {
 192         struct pipe_sampler_view        *views[SI_NUM_SAMPLERS];
 193         struct si_sampler_state         *sampler_states[SI_NUM_SAMPLERS];
 194
 195         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 196         unsigned                        enabled_mask;
 197         uint32_t                        needs_depth_decompress_mask;
 198         uint32_t                        needs_color_decompress_mask;
 199 };
 200
 201 struct si_images {
 202         struct pipe_image_view          views[SI_NUM_IMAGES];
 203         uint32_t                        needs_color_decompress_mask;
 204         unsigned                        enabled_mask;
 205 };
 206
 207 struct si_framebuffer {
 208         struct r600_atom                atom;
 209         struct pipe_framebuffer_state   state;
 210         unsigned                        colorbuf_enabled_4bit;
 211         unsigned                        spi_shader_col_format;
 212         unsigned                        spi_shader_col_format_alpha;
 213         unsigned                        spi_shader_col_format_blend;
 214         unsigned                        spi_shader_col_format_blend_alpha;
 215         ubyte                           nr_samples:5; /* at most 16xAA */
 216         ubyte                           log_samples:3; /* at most 4 = 16xAA */
 217         ubyte                           compressed_cb_mask;
 218         ubyte                           color_is_int8;
 219         ubyte                           color_is_int10;
 220         ubyte                           dirty_cbufs;
 221         bool                            dirty_zsbuf;
 222         bool                            any_dst_linear;
 223         bool                            CB_has_shader_readable_metadata;
 224         bool                            DB_has_shader_readable_metadata;
 225 };
 226
 227 struct si_signed_scissor {
 228         int minx;
 229         int miny;
 230         int maxx;
 231         int maxy;
 232 };
 233
 234 struct si_scissors {
 235         struct r600_atom                atom;
 236         unsigned                        dirty_mask;
 237         struct pipe_scissor_state       states[SI_MAX_VIEWPORTS];
 238 };
 239
 240 struct si_viewports {
 241         struct r600_atom                atom;
 242         unsigned                        dirty_mask;
 243         unsigned                        depth_range_dirty_mask;
 244         struct pipe_viewport_state      states[SI_MAX_VIEWPORTS];
 245         struct si_signed_scissor        as_scissor[SI_MAX_VIEWPORTS];
 246 };
 247
 248 struct si_clip_state {
 249         struct r600_atom                atom;
 250         struct pipe_clip_state          state;
 251         bool                            any_nonzeros;
 252 };
 253
 254 struct si_sample_locs {
 255         struct r600_atom        atom;
 256         unsigned                nr_samples;
 257 };
 258
 259 struct si_sample_mask {
 260         struct r600_atom        atom;
 261         uint16_t                sample_mask;
 262 };
 263
 264 struct si_streamout_target {
 265         struct pipe_stream_output_target b;
 266
 267         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 268         struct r600_resource    *buf_filled_size;
 269         unsigned                buf_filled_size_offset;
 270         bool                    buf_filled_size_valid;
 271
 272         unsigned                stride_in_dw;
 273 };
 274
 275 struct si_streamout {
 276         struct r600_atom                begin_atom;
 277         bool                            begin_emitted;
 278
 279         unsigned                        enabled_mask;
 280         unsigned                        num_targets;
 281         struct si_streamout_target      *targets[PIPE_MAX_SO_BUFFERS];
 282
 283         unsigned                        append_bitmask;
 284         bool                            suspended;
 285
 286         /* External state which comes from the vertex shader,
 287          * it must be set explicitly when binding a shader. */
 288         uint16_t                        *stride_in_dw;
 289         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 290
 291         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 292         unsigned                        hw_enabled_mask;
 293
 294         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 295         struct r600_atom                enable_atom;
 296         bool                            streamout_enabled;
 297         bool                            prims_gen_query_enabled;
 298         int                             num_prims_gen_queries;
 299 };
 300
 301 /* A shader state consists of the shader selector, which is a constant state
 302  * object shared by multiple contexts and shouldn't be modified, and
 303  * the current shader variant selected for this context.
 304  */
 305 struct si_shader_ctx_state {
 306         struct si_shader_selector       *cso;
 307         struct si_shader                *current;
 308 };
 309
 310 #define SI_NUM_VGT_PARAM_KEY_BITS 12
 311 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
 312
 313 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
 314  * Some fields are set by state-change calls, most are set by draw_vbo.
 315  */
 316 union si_vgt_param_key {
 317         struct {
 318                 unsigned prim:4;
 319                 unsigned uses_instancing:1;
 320                 unsigned multi_instances_smaller_than_primgroup:1;
 321                 unsigned primitive_restart:1;
 322                 unsigned count_from_stream_output:1;
 323                 unsigned line_stipple_enabled:1;
 324                 unsigned uses_tess:1;
 325                 unsigned tess_uses_prim_id:1;
 326                 unsigned uses_gs:1;
 327                 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
 328         } u;
 329         uint32_t index;
 330 };
 331
 332 struct si_texture_handle
 333 {
 334         unsigned                        desc_slot;
 335         bool                            desc_dirty;
 336         struct pipe_sampler_view        *view;
 337         struct si_sampler_state         sstate;
 338 };
 339
 340 struct si_image_handle
 341 {
 342         unsigned                        desc_slot;
 343         bool                            desc_dirty;
 344         struct pipe_image_view          view;
 345 };
 346
 347 struct si_saved_cs {
 348         struct pipe_reference   reference;
 349         struct si_context       *ctx;
 350         struct radeon_saved_cs  gfx;
 351         struct r600_resource    *trace_buf;
 352         unsigned                trace_id;
 353
 354         unsigned                gfx_last_dw;
 355         bool                    flushed;
 356         int64_t                 time_flush;
 357 };
 358
 359 struct si_context {
 360         struct r600_common_context      b;
 361         struct blitter_context          *blitter;
 362         void                            *custom_dsa_flush;
 363         void                            *custom_blend_resolve;
 364         void                            *custom_blend_fmask_decompress;
 365         void                            *custom_blend_eliminate_fastclear;
 366         void                            *custom_blend_dcc_decompress;
 367         void                            *vs_blit_pos;
 368         void                            *vs_blit_pos_layered;
 369         void                            *vs_blit_color;
 370         void                            *vs_blit_color_layered;
 371         void                            *vs_blit_texcoord;
 372         struct si_screen                *screen;
 373         struct pipe_debug_callback      debug;
 374         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 375         struct si_shader_ctx_state      fixed_func_tcs_shader;
 376         struct r600_resource            *wait_mem_scratch;
 377         unsigned                        wait_mem_number;
 378         uint16_t                        prefetch_L2_mask;
 379
 380         bool                            gfx_flush_in_progress:1;
 381         bool                            compute_is_busy:1;
 382
 383         /* Atoms (direct states). */
 384         union si_state_atoms            atoms;
 385         unsigned                        dirty_atoms; /* mask */
 386         /* PM4 states (precomputed immutable states) */
 387         unsigned                        dirty_states;
 388         union si_state                  queued;
 389         union si_state                  emitted;
 390
 391         /* Atom declarations. */
 392         struct si_framebuffer           framebuffer;
 393         struct si_sample_locs           msaa_sample_locs;
 394         struct r600_atom                db_render_state;
 395         struct r600_atom                dpbb_state;
 396         struct r600_atom                msaa_config;
 397         struct si_sample_mask           sample_mask;
 398         struct r600_atom                cb_render_state;
 399         unsigned                        last_cb_target_mask;
 400         struct si_blend_color           blend_color;
 401         struct r600_atom                clip_regs;
 402         struct si_clip_state            clip_state;
 403         struct si_shader_data           shader_pointers;
 404         struct si_stencil_ref           stencil_ref;
 405         struct r600_atom                spi_map;
 406         struct si_scissors              scissors;
 407         struct si_streamout             streamout;
 408         struct si_viewports             viewports;
 409
 410         /* Precomputed states. */
 411         struct si_pm4_state             *init_config;
 412         struct si_pm4_state             *init_config_gs_rings;
 413         bool                            init_config_has_vgt_flush;
 414         struct si_pm4_state             *vgt_shader_config[4];
 415
 416         /* shaders */
 417         struct si_shader_ctx_state      ps_shader;
 418         struct si_shader_ctx_state      gs_shader;
 419         struct si_shader_ctx_state      vs_shader;
 420         struct si_shader_ctx_state      tcs_shader;
 421         struct si_shader_ctx_state      tes_shader;
 422         struct si_cs_shader_state       cs_shader_state;
 423
 424         /* shader information */
 425         struct si_vertex_elements       *vertex_elements;
 426         unsigned                        sprite_coord_enable;
 427         bool                            flatshade;
 428         bool                            do_update_shaders;
 429
 430         /* shader descriptors */
 431         struct si_descriptors           vertex_buffers;
 432         struct si_descriptors           descriptors[SI_NUM_DESCS];
 433         unsigned                        descriptors_dirty;
 434         unsigned                        shader_pointers_dirty;
 435         unsigned                        shader_needs_decompress_mask;
 436         struct si_buffer_resources      rw_buffers;
 437         struct si_buffer_resources      const_and_shader_buffers[SI_NUM_SHADERS];
 438         struct si_samplers              samplers[SI_NUM_SHADERS];
 439         struct si_images                images[SI_NUM_SHADERS];
 440
 441         /* other shader resources */
 442         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 443         struct pipe_resource            *esgs_ring;
 444         struct pipe_resource            *gsvs_ring;
 445         struct pipe_resource            *tf_ring;
 446         struct pipe_resource            *tess_offchip_ring;
 447         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 448         struct r600_resource            *border_color_buffer;
 449         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 450         unsigned                        border_color_count;
 451         unsigned                        num_vs_blit_sgprs;
 452         uint32_t                        vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
 453
 454         /* Vertex and index buffers. */
 455         bool                            vertex_buffers_dirty;
 456         bool                            vertex_buffer_pointer_dirty;
 457         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 458
 459         /* MSAA config state. */
 460         int                             ps_iter_samples;
 461         bool                            smoothing_enabled;
 462
 463         /* DB render state. */
 464         unsigned                ps_db_shader_control;
 465         unsigned                dbcb_copy_sample;
 466         bool                    dbcb_depth_copy_enabled:1;
 467         bool                    dbcb_stencil_copy_enabled:1;
 468         bool                    db_flush_depth_inplace:1;
 469         bool                    db_flush_stencil_inplace:1;
 470         bool                    db_depth_clear:1;
 471         bool                    db_depth_disable_expclear:1;
 472         bool                    db_stencil_clear:1;
 473         bool                    db_stencil_disable_expclear:1;
 474         bool                    occlusion_queries_disabled:1;
 475         bool                    generate_mipmap_for_depth:1;
 476
 477         /* Emitted draw state. */
 478         bool                    gs_tri_strip_adj_fix:1;
 479         bool                    ls_vgpr_fix:1;
 480         int                     last_index_size;
 481         int                     last_base_vertex;
 482         int                     last_start_instance;
 483         int                     last_drawid;
 484         int                     last_sh_base_reg;
 485         int                     last_primitive_restart_en;
 486         int                     last_restart_index;
 487         int                     last_gs_out_prim;
 488         int                     last_prim;
 489         int                     last_multi_vgt_param;
 490         int                     last_rast_prim;
 491         unsigned                last_sc_line_stipple;
 492         unsigned                current_vs_state;
 493         unsigned                last_vs_state;
 494         enum pipe_prim_type     current_rast_prim; /* primitive type after TES, GS */
 495
 496         /* Scratch buffer */
 497         struct r600_atom        scratch_state;
 498         struct r600_resource    *scratch_buffer;
 499         unsigned                scratch_waves;
 500         unsigned                spi_tmpring_size;
 501
 502         struct r600_resource    *compute_scratch_buffer;
 503
 504         /* Emitted derived tessellation state. */
 505         /* Local shader (VS), or HS if LS-HS are merged. */
 506         struct si_shader        *last_ls;
 507         struct si_shader_selector *last_tcs;
 508         int                     last_num_tcs_input_cp;
 509         int                     last_tes_sh_base;
 510         bool                    last_tess_uses_primid;
 511         unsigned                last_num_patches;
 512
 513         /* Debug state. */
 514         bool                    is_debug;
 515         struct si_saved_cs      *current_saved_cs;
 516         uint64_t                dmesg_timestamp;
 517         unsigned                apitrace_call_number;
 518
 519         /* Other state */
 520         bool need_check_render_feedback;
 521         bool                    decompression_enabled;
 522
 523         bool                    vs_writes_viewport_index;
 524         bool                    vs_disables_clipping_viewport;
 525
 526         /* Precomputed IA_MULTI_VGT_PARAM */
 527         union si_vgt_param_key  ia_multi_vgt_param_key;
 528         unsigned                ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
 529
 530         /* Bindless descriptors. */
 531         struct si_descriptors   bindless_descriptors;
 532         struct util_idalloc     bindless_used_slots;
 533         unsigned                num_bindless_descriptors;
 534         bool                    bindless_descriptors_dirty;
 535         bool                    graphics_bindless_pointer_dirty;
 536         bool                    compute_bindless_pointer_dirty;
 537
 538         /* Allocated bindless handles */
 539         struct hash_table       *tex_handles;
 540         struct hash_table       *img_handles;
 541
 542         /* Resident bindless handles */
 543         struct util_dynarray    resident_tex_handles;
 544         struct util_dynarray    resident_img_handles;
 545
 546         /* Resident bindless handles which need decompression */
 547         struct util_dynarray    resident_tex_needs_color_decompress;
 548         struct util_dynarray    resident_img_needs_color_decompress;
 549         struct util_dynarray    resident_tex_needs_depth_decompress;
 550
 551         /* Bindless state */
 552         bool                    uses_bindless_samplers;
 553         bool                    uses_bindless_images;
 554
 555         /* MSAA sample locations.
 556          * The first index is the sample index.
 557          * The second index is the coordinate: X, Y. */
 558         float                   sample_locations_1x[1][2];
 559         float                   sample_locations_2x[2][2];
 560         float                   sample_locations_4x[4][2];
 561         float                   sample_locations_8x[8][2];
 562         float                   sample_locations_16x[16][2];
 563 };
 564
 565 /* cik_sdma.c */
 566 void cik_init_sdma_functions(struct si_context *sctx);
 567
 568 /* si_blit.c */
 569 enum si_blitter_op /* bitmask */
 570 {
 571         SI_SAVE_TEXTURES      = 1,
 572         SI_SAVE_FRAMEBUFFER   = 2,
 573         SI_SAVE_FRAGMENT_STATE = 4,
 574         SI_DISABLE_RENDER_COND = 8,
 575 };
 576
 577 void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op);
 578 void si_blitter_end(struct pipe_context *ctx);
 579 void si_init_blit_functions(struct si_context *sctx);
 580 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
 581 void si_resource_copy_region(struct pipe_context *ctx,
 582                              struct pipe_resource *dst,
 583                              unsigned dst_level,
 584                              unsigned dstx, unsigned dsty, unsigned dstz,
 585                              struct pipe_resource *src,
 586                              unsigned src_level,
 587                              const struct pipe_box *src_box);
 588
 589 /* si_clear.c */
 590 void vi_dcc_clear_level(struct si_context *sctx,
 591                         struct r600_texture *rtex,
 592                         unsigned level, unsigned clear_value);
 593 void si_init_clear_functions(struct si_context *sctx);
 594
 595 /* si_cp_dma.c */
 596 #define SI_CPDMA_SKIP_CHECK_CS_SPACE    (1 << 0) /* don't call need_cs_space */
 597 #define SI_CPDMA_SKIP_SYNC_AFTER        (1 << 1) /* don't wait for DMA after the copy */
 598 #define SI_CPDMA_SKIP_SYNC_BEFORE       (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
 599 #define SI_CPDMA_SKIP_GFX_SYNC          (1 << 3) /* don't flush caches and don't wait for PS/CS */
 600 #define SI_CPDMA_SKIP_BO_LIST_UPDATE    (1 << 4) /* don't update the BO list */
 601 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
 602                            SI_CPDMA_SKIP_SYNC_AFTER | \
 603                            SI_CPDMA_SKIP_SYNC_BEFORE | \
 604                            SI_CPDMA_SKIP_GFX_SYNC | \
 605                            SI_CPDMA_SKIP_BO_LIST_UPDATE)
 606
 607 enum r600_coherency {
 608         R600_COHERENCY_NONE, /* no cache flushes needed */
 609         R600_COHERENCY_SHADER,
 610         R600_COHERENCY_CB_META,
 611 };
 612
 613 void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
 614                      uint64_t offset, uint64_t size, unsigned value,
 615                      enum r600_coherency coher);
 616 void si_copy_buffer(struct si_context *sctx,
 617                     struct pipe_resource *dst, struct pipe_resource *src,
 618                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 619                     unsigned user_flags);
 620 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 621                               uint64_t offset, unsigned size);
 622 void cik_emit_prefetch_L2(struct si_context *sctx);
 623 void si_init_cp_dma_functions(struct si_context *sctx);
 624
 625 /* si_debug.c */
 626 void si_auto_log_cs(void *data, struct u_log_context *log);
 627 void si_log_hw_flush(struct si_context *sctx);
 628 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
 629 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
 630 void si_init_debug_functions(struct si_context *sctx);
 631 void si_check_vm_faults(struct r600_common_context *ctx,
 632                         struct radeon_saved_cs *saved, enum ring_type ring);
 633 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
 634
 635 /* si_dma.c */
 636 void si_init_dma_functions(struct si_context *sctx);
 637
 638 /* si_fence.c */
 639 void si_init_fence_functions(struct si_context *ctx);
 640 void si_init_screen_fence_functions(struct si_screen *screen);
 641 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
 642                                           struct tc_unflushed_batch_token *tc_token);
 643
 644 /* si_get.c */
 645 const char *si_get_family_name(const struct si_screen *sscreen);
 646 void si_init_screen_get_functions(struct si_screen *sscreen);
 647
 648 /* si_hw_context.c */
 649 void si_destroy_saved_cs(struct si_saved_cs *scs);
 650 void si_context_gfx_flush(void *context, unsigned flags,
 651                           struct pipe_fence_handle **fence);
 652 void si_begin_new_cs(struct si_context *ctx);
 653 void si_need_cs_space(struct si_context *ctx);
 654
 655 /* si_compute.c */
 656 void si_init_compute_functions(struct si_context *sctx);
 657
 658 /* si_perfcounters.c */
 659 void si_init_perfcounters(struct si_screen *screen);
 660
 661 /* si_test_dma.c */
 662 void si_test_dma(struct si_screen *sscreen);
 663
 664 /* si_uvd.c */
 665 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 666                                                const struct pipe_video_codec *templ);
 667
 668 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 669                                                  const struct pipe_video_buffer *tmpl);
 670
 671 /* si_viewport.c */
 672 void si_update_vs_viewport_state(struct si_context *ctx);
 673 void si_init_viewport_functions(struct si_context *ctx);
 674
 675
 676 /*
 677  * common helpers
 678  */
 679
 680 static inline void
 681 si_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 682 {
 683         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 684         struct r600_resource *res = (struct r600_resource *)r;
 685
 686         if (res) {
 687                 /* Add memory usage for need_gfx_cs_space */
 688                 rctx->vram += res->vram_usage;
 689                 rctx->gtt += res->gart_usage;
 690         }
 691 }
 692
 693 static inline void
 694 si_invalidate_draw_sh_constants(struct si_context *sctx)
 695 {
 696         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 697 }
 698
 699 static inline void
 700 si_set_atom_dirty(struct si_context *sctx,
 701                   struct r600_atom *atom, bool dirty)
 702 {
 703         unsigned bit = 1 << atom->id;
 704
 705         if (dirty)
 706                 sctx->dirty_atoms |= bit;
 707         else
 708                 sctx->dirty_atoms &= ~bit;
 709 }
 710
 711 static inline bool
 712 si_is_atom_dirty(struct si_context *sctx,
 713                   struct r600_atom *atom)
 714 {
 715         unsigned bit = 1 << atom->id;
 716
 717         return sctx->dirty_atoms & bit;
 718 }
 719
 720 static inline void
 721 si_mark_atom_dirty(struct si_context *sctx,
 722                    struct r600_atom *atom)
 723 {
 724         si_set_atom_dirty(sctx, atom, true);
 725 }
 726
 727 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
 728 {
 729         if (sctx->gs_shader.cso)
 730                 return &sctx->gs_shader;
 731         if (sctx->tes_shader.cso)
 732                 return &sctx->tes_shader;
 733
 734         return &sctx->vs_shader;
 735 }
 736
 737 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 738 {
 739         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 740
 741         return vs->cso ? &vs->cso->info : NULL;
 742 }
 743
 744 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 745 {
 746         if (sctx->gs_shader.cso)
 747                 return sctx->gs_shader.cso->gs_copy_shader;
 748
 749         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 750         return vs->current ? vs->current : NULL;
 751 }
 752
 753 static inline bool si_can_dump_shader(struct si_screen *sscreen,
 754                                       unsigned processor)
 755 {
 756         return sscreen->b.debug_flags & (1 << processor);
 757 }
 758
 759 static inline bool si_extra_shader_checks(struct si_screen *sscreen,
 760                                           unsigned processor)
 761 {
 762         return (sscreen->b.debug_flags & DBG(CHECK_IR)) ||
 763                si_can_dump_shader(sscreen, processor);
 764 }
 765
 766 static inline bool si_get_strmout_en(struct si_context *sctx)
 767 {
 768         return sctx->streamout.streamout_enabled ||
 769                sctx->streamout.prims_gen_query_enabled;
 770 }
 771
 772 static inline unsigned
 773 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
 774 {
 775         unsigned alignment, tcc_cache_line_size;
 776
 777         /* If the upload size is less than the cache line size (e.g. 16, 32),
 778          * the whole thing will fit into a cache line if we align it to its size.
 779          * The idea is that multiple small uploads can share a cache line.
 780          * If the upload size is greater, align it to the cache line size.
 781          */
 782         alignment = util_next_power_of_two(upload_size);
 783         tcc_cache_line_size = sctx->screen->b.info.tcc_cache_line_size;
 784         return MIN2(alignment, tcc_cache_line_size);
 785 }
 786
 787 static inline void
 788 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
 789 {
 790         if (pipe_reference(&(*dst)->reference, &src->reference))
 791                 si_destroy_saved_cs(*dst);
 792
 793         *dst = src;
 794 }
 795
 796 static inline void
 797 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 798                            bool shaders_read_metadata)
 799 {
 800         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
 801                          SI_CONTEXT_INV_VMEM_L1;
 802
 803         if (sctx->b.chip_class >= GFX9) {
 804                 /* Single-sample color is coherent with shaders on GFX9, but
 805                  * L2 metadata must be flushed if shaders read metadata.
 806                  * (DCC, CMASK).
 807                  */
 808                 if (num_samples >= 2)
 809                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 810                 else if (shaders_read_metadata)
 811                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 812         } else {
 813                 /* SI-CI-VI */
 814                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 815         }
 816 }
 817
 818 static inline void
 819 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 820                            bool include_stencil, bool shaders_read_metadata)
 821 {
 822         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
 823                          SI_CONTEXT_INV_VMEM_L1;
 824
 825         if (sctx->b.chip_class >= GFX9) {
 826                 /* Single-sample depth (not stencil) is coherent with shaders
 827                  * on GFX9, but L2 metadata must be flushed if shaders read
 828                  * metadata.
 829                  */
 830                 if (num_samples >= 2 || include_stencil)
 831                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 832                 else if (shaders_read_metadata)
 833                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 834         } else {
 835                 /* SI-CI-VI */
 836                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 837         }
 838 }
 839
 840 static inline bool
 841 si_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
 842 {
 843         return (stencil_sampler && tex->can_sample_s) ||
 844                (!stencil_sampler && tex->can_sample_z);
 845 }
 846
 847 static inline bool
 848 si_htile_enabled(struct r600_texture *tex, unsigned level)
 849 {
 850         return tex->htile_offset && level == 0;
 851 }
 852
 853 static inline bool
 854 vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level)
 855 {
 856         assert(!tex->tc_compatible_htile || tex->htile_offset);
 857         return tex->tc_compatible_htile && level == 0;
 858 }
 859
 860 #endif