src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef SI_PIPE_H
  24 #define SI_PIPE_H
  25
  26 #include "si_shader.h"
  27
  28 #include "util/u_dynarray.h"
  29 #include "util/u_idalloc.h"
  30
  31 #ifdef PIPE_ARCH_BIG_ENDIAN
  32 #define SI_BIG_ENDIAN 1
  33 #else
  34 #define SI_BIG_ENDIAN 0
  35 #endif
  36
  37 /* The base vertex and primitive restart can be any number, but we must pick
  38  * one which will mean "unknown" for the purpose of state tracking and
  39  * the number shouldn't be a commonly-used one. */
  40 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  41 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  42 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  43 #define SI_GS_PER_ES 128
  44 /* Alignment for optimal CP DMA performance. */
  45 #define SI_CPDMA_ALIGNMENT      32
  46
  47 /* Instruction cache. */
  48 #define SI_CONTEXT_INV_ICACHE           (R600_CONTEXT_PRIVATE_FLAG << 0)
  49 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  50 #define SI_CONTEXT_INV_SMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 1)
  51 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  52 #define SI_CONTEXT_INV_VMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 2)
  53 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  54 #define SI_CONTEXT_INV_GLOBAL_L2        (R600_CONTEXT_PRIVATE_FLAG << 3)
  55 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  56  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
  57 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2  (R600_CONTEXT_PRIVATE_FLAG << 4)
  58 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
  59  * a CB or DB flush. */
  60 #define SI_CONTEXT_INV_L2_METADATA      (R600_CONTEXT_PRIVATE_FLAG << 5)
  61 /* Framebuffer caches. */
  62 #define SI_CONTEXT_FLUSH_AND_INV_DB     (R600_CONTEXT_PRIVATE_FLAG << 6)
  63 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 7)
  64 #define SI_CONTEXT_FLUSH_AND_INV_CB     (R600_CONTEXT_PRIVATE_FLAG << 8)
  65 /* Engine synchronization. */
  66 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 9)
  67 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 10)
  68 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 11)
  69 #define SI_CONTEXT_VGT_FLUSH            (R600_CONTEXT_PRIVATE_FLAG << 12)
  70 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (R600_CONTEXT_PRIVATE_FLAG << 13)
  71
  72 #define SI_PREFETCH_VBO_DESCRIPTORS     (1 << 0)
  73 #define SI_PREFETCH_LS                  (1 << 1)
  74 #define SI_PREFETCH_HS                  (1 << 2)
  75 #define SI_PREFETCH_ES                  (1 << 3)
  76 #define SI_PREFETCH_GS                  (1 << 4)
  77 #define SI_PREFETCH_VS                  (1 << 5)
  78 #define SI_PREFETCH_PS                  (1 << 6)
  79
  80 #define SI_MAX_BORDER_COLORS    4096
  81 #define SI_MAX_VIEWPORTS        16
  82 #define SIX_BITS                0x3F
  83
  84 struct si_compute;
  85 struct hash_table;
  86 struct u_suballocator;
  87
  88 struct si_screen {
  89         struct r600_common_screen       b;
  90         unsigned                        gs_table_depth;
  91         unsigned                        tess_offchip_block_dw_size;
  92         bool                            has_clear_state;
  93         bool                            has_distributed_tess;
  94         bool                            has_draw_indirect_multi;
  95         bool                            has_out_of_order_rast;
  96         bool                            assume_no_z_fights;
  97         bool                            commutative_blend_add;
  98         bool                            clear_db_cache_before_clear;
  99         bool                            has_msaa_sample_loc_bug;
 100         bool                            has_ls_vgpr_init_bug;
 101         bool                            dpbb_allowed;
 102         bool                            dfsm_allowed;
 103         bool                            llvm_has_working_vgpr_indexing;
 104
 105         /* Whether shaders are monolithic (1-part) or separate (3-part). */
 106         bool                            use_monolithic_shaders;
 107         bool                            record_llvm_ir;
 108
 109         mtx_t                   shader_parts_mutex;
 110         struct si_shader_part           *vs_prologs;
 111         struct si_shader_part           *tcs_epilogs;
 112         struct si_shader_part           *gs_prologs;
 113         struct si_shader_part           *ps_prologs;
 114         struct si_shader_part           *ps_epilogs;
 115
 116         /* Shader cache in memory.
 117          *
 118          * Design & limitations:
 119          * - The shader cache is per screen (= per process), never saved to
 120          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 121          * - It can only be used with one-variant-per-shader support, in which
 122          *   case only the main (typically middle) part of shaders is cached.
 123          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 124          *   variants of VS and TES are cached, so LS and ES aren't.
 125          * - GS and CS aren't cached, but it's certainly possible to cache
 126          *   those as well.
 127          */
 128         mtx_t                   shader_cache_mutex;
 129         struct hash_table               *shader_cache;
 130
 131         /* Shader compiler queue for multithreaded compilation. */
 132         struct util_queue               shader_compiler_queue;
 133         /* Use at most 3 normal compiler threads on quadcore and better.
 134          * Hyperthreaded CPUs report the number of threads, but we want
 135          * the number of cores. */
 136         LLVMTargetMachineRef            tm[3]; /* used by the queue only */
 137
 138         struct util_queue               shader_compiler_queue_low_priority;
 139         /* Use at most 2 low priority threads on quadcore and better.
 140          * We want to minimize the impact on multithreaded Mesa. */
 141         LLVMTargetMachineRef            tm_low_priority[2]; /* at most 2 threads */
 142 };
 143
 144 struct si_blend_color {
 145         struct r600_atom                atom;
 146         struct pipe_blend_color         state;
 147         bool                            any_nonzeros;
 148 };
 149
 150 struct si_sampler_view {
 151         struct pipe_sampler_view        base;
 152         /* [0..7] = image descriptor
 153          * [4..7] = buffer descriptor */
 154         uint32_t                        state[8];
 155         uint32_t                        fmask_state[8];
 156         const struct legacy_surf_level  *base_level_info;
 157         ubyte                           base_level;
 158         ubyte                           block_width;
 159         bool is_stencil_sampler;
 160         bool is_integer;
 161         bool dcc_incompatible;
 162 };
 163
 164 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
 165
 166 struct si_sampler_state {
 167 #ifdef DEBUG
 168         unsigned                        magic;
 169 #endif
 170         uint32_t                        val[4];
 171         uint32_t                        integer_val[4];
 172         uint32_t                        upgraded_depth_val[4];
 173 };
 174
 175 struct si_cs_shader_state {
 176         struct si_compute               *program;
 177         struct si_compute               *emitted_program;
 178         unsigned                        offset;
 179         bool                            initialized;
 180         bool                            uses_scratch;
 181 };
 182
 183 struct si_samplers {
 184         struct pipe_sampler_view        *views[SI_NUM_SAMPLERS];
 185         struct si_sampler_state         *sampler_states[SI_NUM_SAMPLERS];
 186
 187         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 188         unsigned                        enabled_mask;
 189         uint32_t                        needs_depth_decompress_mask;
 190         uint32_t                        needs_color_decompress_mask;
 191 };
 192
 193 struct si_images {
 194         struct pipe_image_view          views[SI_NUM_IMAGES];
 195         uint32_t                        needs_color_decompress_mask;
 196         unsigned                        enabled_mask;
 197 };
 198
 199 struct si_framebuffer {
 200         struct r600_atom                atom;
 201         struct pipe_framebuffer_state   state;
 202         unsigned                        colorbuf_enabled_4bit;
 203         unsigned                        spi_shader_col_format;
 204         unsigned                        spi_shader_col_format_alpha;
 205         unsigned                        spi_shader_col_format_blend;
 206         unsigned                        spi_shader_col_format_blend_alpha;
 207         ubyte                           nr_samples:5; /* at most 16xAA */
 208         ubyte                           log_samples:3; /* at most 4 = 16xAA */
 209         ubyte                           compressed_cb_mask;
 210         ubyte                           color_is_int8;
 211         ubyte                           color_is_int10;
 212         ubyte                           dirty_cbufs;
 213         bool                            dirty_zsbuf;
 214         bool                            any_dst_linear;
 215         bool                            CB_has_shader_readable_metadata;
 216         bool                            DB_has_shader_readable_metadata;
 217 };
 218
 219 struct si_signed_scissor {
 220         int minx;
 221         int miny;
 222         int maxx;
 223         int maxy;
 224 };
 225
 226 struct si_scissors {
 227         struct r600_atom                atom;
 228         unsigned                        dirty_mask;
 229         struct pipe_scissor_state       states[SI_MAX_VIEWPORTS];
 230 };
 231
 232 struct si_viewports {
 233         struct r600_atom                atom;
 234         unsigned                        dirty_mask;
 235         unsigned                        depth_range_dirty_mask;
 236         struct pipe_viewport_state      states[SI_MAX_VIEWPORTS];
 237         struct si_signed_scissor        as_scissor[SI_MAX_VIEWPORTS];
 238 };
 239
 240 struct si_clip_state {
 241         struct r600_atom                atom;
 242         struct pipe_clip_state          state;
 243         bool                            any_nonzeros;
 244 };
 245
 246 struct si_sample_locs {
 247         struct r600_atom        atom;
 248         unsigned                nr_samples;
 249 };
 250
 251 struct si_sample_mask {
 252         struct r600_atom        atom;
 253         uint16_t                sample_mask;
 254 };
 255
 256 struct si_streamout_target {
 257         struct pipe_stream_output_target b;
 258
 259         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 260         struct r600_resource    *buf_filled_size;
 261         unsigned                buf_filled_size_offset;
 262         bool                    buf_filled_size_valid;
 263
 264         unsigned                stride_in_dw;
 265 };
 266
 267 struct si_streamout {
 268         struct r600_atom                begin_atom;
 269         bool                            begin_emitted;
 270
 271         unsigned                        enabled_mask;
 272         unsigned                        num_targets;
 273         struct si_streamout_target      *targets[PIPE_MAX_SO_BUFFERS];
 274
 275         unsigned                        append_bitmask;
 276         bool                            suspended;
 277
 278         /* External state which comes from the vertex shader,
 279          * it must be set explicitly when binding a shader. */
 280         uint16_t                        *stride_in_dw;
 281         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 282
 283         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 284         unsigned                        hw_enabled_mask;
 285
 286         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 287         struct r600_atom                enable_atom;
 288         bool                            streamout_enabled;
 289         bool                            prims_gen_query_enabled;
 290         int                             num_prims_gen_queries;
 291 };
 292
 293 /* A shader state consists of the shader selector, which is a constant state
 294  * object shared by multiple contexts and shouldn't be modified, and
 295  * the current shader variant selected for this context.
 296  */
 297 struct si_shader_ctx_state {
 298         struct si_shader_selector       *cso;
 299         struct si_shader                *current;
 300 };
 301
 302 #define SI_NUM_VGT_PARAM_KEY_BITS 12
 303 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
 304
 305 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
 306  * Some fields are set by state-change calls, most are set by draw_vbo.
 307  */
 308 union si_vgt_param_key {
 309         struct {
 310                 unsigned prim:4;
 311                 unsigned uses_instancing:1;
 312                 unsigned multi_instances_smaller_than_primgroup:1;
 313                 unsigned primitive_restart:1;
 314                 unsigned count_from_stream_output:1;
 315                 unsigned line_stipple_enabled:1;
 316                 unsigned uses_tess:1;
 317                 unsigned tess_uses_prim_id:1;
 318                 unsigned uses_gs:1;
 319                 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
 320         } u;
 321         uint32_t index;
 322 };
 323
 324 struct si_texture_handle
 325 {
 326         unsigned                        desc_slot;
 327         bool                            desc_dirty;
 328         struct pipe_sampler_view        *view;
 329         struct si_sampler_state         sstate;
 330 };
 331
 332 struct si_image_handle
 333 {
 334         unsigned                        desc_slot;
 335         bool                            desc_dirty;
 336         struct pipe_image_view          view;
 337 };
 338
 339 struct si_saved_cs {
 340         struct pipe_reference   reference;
 341         struct si_context       *ctx;
 342         struct radeon_saved_cs  gfx;
 343         struct r600_resource    *trace_buf;
 344         unsigned                trace_id;
 345
 346         unsigned                gfx_last_dw;
 347         bool                    flushed;
 348 };
 349
 350 struct si_context {
 351         struct r600_common_context      b;
 352         struct blitter_context          *blitter;
 353         void                            *custom_dsa_flush;
 354         void                            *custom_blend_resolve;
 355         void                            *custom_blend_fmask_decompress;
 356         void                            *custom_blend_eliminate_fastclear;
 357         void                            *custom_blend_dcc_decompress;
 358         void                            *vs_blit_pos;
 359         void                            *vs_blit_pos_layered;
 360         void                            *vs_blit_color;
 361         void                            *vs_blit_color_layered;
 362         void                            *vs_blit_texcoord;
 363         struct si_screen                *screen;
 364         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 365         struct si_shader_ctx_state      fixed_func_tcs_shader;
 366         struct r600_resource            *wait_mem_scratch;
 367         unsigned                        wait_mem_number;
 368         uint16_t                        prefetch_L2_mask;
 369
 370         bool                            gfx_flush_in_progress:1;
 371         bool                            compute_is_busy:1;
 372
 373         /* Atoms (direct states). */
 374         union si_state_atoms            atoms;
 375         unsigned                        dirty_atoms; /* mask */
 376         /* PM4 states (precomputed immutable states) */
 377         unsigned                        dirty_states;
 378         union si_state                  queued;
 379         union si_state                  emitted;
 380
 381         /* Atom declarations. */
 382         struct si_framebuffer           framebuffer;
 383         struct si_sample_locs           msaa_sample_locs;
 384         struct r600_atom                db_render_state;
 385         struct r600_atom                dpbb_state;
 386         struct r600_atom                msaa_config;
 387         struct si_sample_mask           sample_mask;
 388         struct r600_atom                cb_render_state;
 389         unsigned                        last_cb_target_mask;
 390         struct si_blend_color           blend_color;
 391         struct r600_atom                clip_regs;
 392         struct si_clip_state            clip_state;
 393         struct si_shader_data           shader_pointers;
 394         struct si_stencil_ref           stencil_ref;
 395         struct r600_atom                spi_map;
 396         struct si_scissors              scissors;
 397         struct si_streamout             streamout;
 398         struct si_viewports             viewports;
 399
 400         /* Precomputed states. */
 401         struct si_pm4_state             *init_config;
 402         struct si_pm4_state             *init_config_gs_rings;
 403         bool                            init_config_has_vgt_flush;
 404         struct si_pm4_state             *vgt_shader_config[4];
 405
 406         /* shaders */
 407         struct si_shader_ctx_state      ps_shader;
 408         struct si_shader_ctx_state      gs_shader;
 409         struct si_shader_ctx_state      vs_shader;
 410         struct si_shader_ctx_state      tcs_shader;
 411         struct si_shader_ctx_state      tes_shader;
 412         struct si_cs_shader_state       cs_shader_state;
 413
 414         /* shader information */
 415         struct si_vertex_elements       *vertex_elements;
 416         unsigned                        sprite_coord_enable;
 417         bool                            flatshade;
 418         bool                            do_update_shaders;
 419
 420         /* shader descriptors */
 421         struct si_descriptors           vertex_buffers;
 422         struct si_descriptors           descriptors[SI_NUM_DESCS];
 423         unsigned                        descriptors_dirty;
 424         unsigned                        shader_pointers_dirty;
 425         unsigned                        shader_needs_decompress_mask;
 426         struct si_buffer_resources      rw_buffers;
 427         struct si_buffer_resources      const_and_shader_buffers[SI_NUM_SHADERS];
 428         struct si_samplers              samplers[SI_NUM_SHADERS];
 429         struct si_images                images[SI_NUM_SHADERS];
 430
 431         /* other shader resources */
 432         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 433         struct pipe_resource            *esgs_ring;
 434         struct pipe_resource            *gsvs_ring;
 435         struct pipe_resource            *tf_ring;
 436         struct pipe_resource            *tess_offchip_ring;
 437         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 438         struct r600_resource            *border_color_buffer;
 439         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 440         unsigned                        border_color_count;
 441         unsigned                        num_vs_blit_sgprs;
 442         uint32_t                        vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
 443
 444         /* Vertex and index buffers. */
 445         bool                            vertex_buffers_dirty;
 446         bool                            vertex_buffer_pointer_dirty;
 447         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 448
 449         /* MSAA config state. */
 450         int                             ps_iter_samples;
 451         bool                            smoothing_enabled;
 452
 453         /* DB render state. */
 454         unsigned                ps_db_shader_control;
 455         unsigned                dbcb_copy_sample;
 456         bool                    dbcb_depth_copy_enabled:1;
 457         bool                    dbcb_stencil_copy_enabled:1;
 458         bool                    db_flush_depth_inplace:1;
 459         bool                    db_flush_stencil_inplace:1;
 460         bool                    db_depth_clear:1;
 461         bool                    db_depth_disable_expclear:1;
 462         bool                    db_stencil_clear:1;
 463         bool                    db_stencil_disable_expclear:1;
 464         bool                    occlusion_queries_disabled:1;
 465         bool                    generate_mipmap_for_depth:1;
 466
 467         /* Emitted draw state. */
 468         bool                    gs_tri_strip_adj_fix:1;
 469         bool                    ls_vgpr_fix:1;
 470         int                     last_index_size;
 471         int                     last_base_vertex;
 472         int                     last_start_instance;
 473         int                     last_drawid;
 474         int                     last_sh_base_reg;
 475         int                     last_primitive_restart_en;
 476         int                     last_restart_index;
 477         int                     last_gs_out_prim;
 478         int                     last_prim;
 479         int                     last_multi_vgt_param;
 480         int                     last_rast_prim;
 481         unsigned                last_sc_line_stipple;
 482         unsigned                current_vs_state;
 483         unsigned                last_vs_state;
 484         enum pipe_prim_type     current_rast_prim; /* primitive type after TES, GS */
 485
 486         /* Scratch buffer */
 487         struct r600_atom        scratch_state;
 488         struct r600_resource    *scratch_buffer;
 489         unsigned                scratch_waves;
 490         unsigned                spi_tmpring_size;
 491
 492         struct r600_resource    *compute_scratch_buffer;
 493
 494         /* Emitted derived tessellation state. */
 495         /* Local shader (VS), or HS if LS-HS are merged. */
 496         struct si_shader        *last_ls;
 497         struct si_shader_selector *last_tcs;
 498         int                     last_num_tcs_input_cp;
 499         int                     last_tes_sh_base;
 500         bool                    last_tess_uses_primid;
 501         unsigned                last_num_patches;
 502
 503         /* Debug state. */
 504         bool                    is_debug;
 505         struct si_saved_cs      *current_saved_cs;
 506         uint64_t                dmesg_timestamp;
 507         unsigned                apitrace_call_number;
 508
 509         /* Other state */
 510         bool need_check_render_feedback;
 511         bool                    decompression_enabled;
 512
 513         bool                    vs_writes_viewport_index;
 514         bool                    vs_disables_clipping_viewport;
 515
 516         /* Precomputed IA_MULTI_VGT_PARAM */
 517         union si_vgt_param_key  ia_multi_vgt_param_key;
 518         unsigned                ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
 519
 520         /* Bindless descriptors. */
 521         struct si_descriptors   bindless_descriptors;
 522         struct util_idalloc     bindless_used_slots;
 523         unsigned                num_bindless_descriptors;
 524         bool                    bindless_descriptors_dirty;
 525         bool                    graphics_bindless_pointer_dirty;
 526         bool                    compute_bindless_pointer_dirty;
 527
 528         /* Allocated bindless handles */
 529         struct hash_table       *tex_handles;
 530         struct hash_table       *img_handles;
 531
 532         /* Resident bindless handles */
 533         struct util_dynarray    resident_tex_handles;
 534         struct util_dynarray    resident_img_handles;
 535
 536         /* Resident bindless handles which need decompression */
 537         struct util_dynarray    resident_tex_needs_color_decompress;
 538         struct util_dynarray    resident_img_needs_color_decompress;
 539         struct util_dynarray    resident_tex_needs_depth_decompress;
 540
 541         /* Bindless state */
 542         bool                    uses_bindless_samplers;
 543         bool                    uses_bindless_images;
 544
 545         /* MSAA sample locations.
 546          * The first index is the sample index.
 547          * The second index is the coordinate: X, Y. */
 548         float                   sample_locations_1x[1][2];
 549         float                   sample_locations_2x[2][2];
 550         float                   sample_locations_4x[4][2];
 551         float                   sample_locations_8x[8][2];
 552         float                   sample_locations_16x[16][2];
 553 };
 554
 555 /* cik_sdma.c */
 556 void cik_init_sdma_functions(struct si_context *sctx);
 557
 558 /* si_blit.c */
 559 void si_init_blit_functions(struct si_context *sctx);
 560 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
 561 void si_resource_copy_region(struct pipe_context *ctx,
 562                              struct pipe_resource *dst,
 563                              unsigned dst_level,
 564                              unsigned dstx, unsigned dsty, unsigned dstz,
 565                              struct pipe_resource *src,
 566                              unsigned src_level,
 567                              const struct pipe_box *src_box);
 568
 569 /* si_cp_dma.c */
 570 #define SI_CPDMA_SKIP_CHECK_CS_SPACE    (1 << 0) /* don't call need_cs_space */
 571 #define SI_CPDMA_SKIP_SYNC_AFTER        (1 << 1) /* don't wait for DMA after the copy */
 572 #define SI_CPDMA_SKIP_SYNC_BEFORE       (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
 573 #define SI_CPDMA_SKIP_GFX_SYNC          (1 << 3) /* don't flush caches and don't wait for PS/CS */
 574 #define SI_CPDMA_SKIP_BO_LIST_UPDATE    (1 << 4) /* don't update the BO list */
 575 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
 576                            SI_CPDMA_SKIP_SYNC_AFTER | \
 577                            SI_CPDMA_SKIP_SYNC_BEFORE | \
 578                            SI_CPDMA_SKIP_GFX_SYNC | \
 579                            SI_CPDMA_SKIP_BO_LIST_UPDATE)
 580
 581 void si_copy_buffer(struct si_context *sctx,
 582                     struct pipe_resource *dst, struct pipe_resource *src,
 583                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 584                     unsigned user_flags);
 585 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 586                               uint64_t offset, unsigned size);
 587 void cik_emit_prefetch_L2(struct si_context *sctx);
 588 void si_init_cp_dma_functions(struct si_context *sctx);
 589
 590 /* si_debug.c */
 591 void si_auto_log_cs(void *data, struct u_log_context *log);
 592 void si_log_hw_flush(struct si_context *sctx);
 593 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
 594 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
 595 void si_init_debug_functions(struct si_context *sctx);
 596 void si_check_vm_faults(struct r600_common_context *ctx,
 597                         struct radeon_saved_cs *saved, enum ring_type ring);
 598 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
 599
 600 /* si_dma.c */
 601 void si_init_dma_functions(struct si_context *sctx);
 602
 603 /* si_hw_context.c */
 604 void si_destroy_saved_cs(struct si_saved_cs *scs);
 605 void si_context_gfx_flush(void *context, unsigned flags,
 606                           struct pipe_fence_handle **fence);
 607 void si_begin_new_cs(struct si_context *ctx);
 608 void si_need_cs_space(struct si_context *ctx);
 609
 610 /* si_compute.c */
 611 void si_init_compute_functions(struct si_context *sctx);
 612
 613 /* si_perfcounters.c */
 614 void si_init_perfcounters(struct si_screen *screen);
 615
 616 /* si_uvd.c */
 617 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 618                                                const struct pipe_video_codec *templ);
 619
 620 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 621                                                  const struct pipe_video_buffer *tmpl);
 622
 623 /* si_viewport.c */
 624 void si_update_vs_viewport_state(struct si_context *ctx);
 625 void si_init_viewport_functions(struct si_context *ctx);
 626
 627
 628 /*
 629  * common helpers
 630  */
 631
 632 static inline void
 633 si_invalidate_draw_sh_constants(struct si_context *sctx)
 634 {
 635         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 636 }
 637
 638 static inline void
 639 si_set_atom_dirty(struct si_context *sctx,
 640                   struct r600_atom *atom, bool dirty)
 641 {
 642         unsigned bit = 1 << atom->id;
 643
 644         if (dirty)
 645                 sctx->dirty_atoms |= bit;
 646         else
 647                 sctx->dirty_atoms &= ~bit;
 648 }
 649
 650 static inline bool
 651 si_is_atom_dirty(struct si_context *sctx,
 652                   struct r600_atom *atom)
 653 {
 654         unsigned bit = 1 << atom->id;
 655
 656         return sctx->dirty_atoms & bit;
 657 }
 658
 659 static inline void
 660 si_mark_atom_dirty(struct si_context *sctx,
 661                    struct r600_atom *atom)
 662 {
 663         si_set_atom_dirty(sctx, atom, true);
 664 }
 665
 666 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
 667 {
 668         if (sctx->gs_shader.cso)
 669                 return &sctx->gs_shader;
 670         if (sctx->tes_shader.cso)
 671                 return &sctx->tes_shader;
 672
 673         return &sctx->vs_shader;
 674 }
 675
 676 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 677 {
 678         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 679
 680         return vs->cso ? &vs->cso->info : NULL;
 681 }
 682
 683 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 684 {
 685         if (sctx->gs_shader.cso)
 686                 return sctx->gs_shader.cso->gs_copy_shader;
 687
 688         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 689         return vs->current ? vs->current : NULL;
 690 }
 691
 692 static inline bool si_get_strmout_en(struct si_context *sctx)
 693 {
 694         return sctx->streamout.streamout_enabled ||
 695                sctx->streamout.prims_gen_query_enabled;
 696 }
 697
 698 static inline unsigned
 699 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
 700 {
 701         unsigned alignment, tcc_cache_line_size;
 702
 703         /* If the upload size is less than the cache line size (e.g. 16, 32),
 704          * the whole thing will fit into a cache line if we align it to its size.
 705          * The idea is that multiple small uploads can share a cache line.
 706          * If the upload size is greater, align it to the cache line size.
 707          */
 708         alignment = util_next_power_of_two(upload_size);
 709         tcc_cache_line_size = sctx->screen->b.info.tcc_cache_line_size;
 710         return MIN2(alignment, tcc_cache_line_size);
 711 }
 712
 713 static inline void
 714 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
 715 {
 716         if (pipe_reference(&(*dst)->reference, &src->reference))
 717                 si_destroy_saved_cs(*dst);
 718
 719         *dst = src;
 720 }
 721
 722 static inline void
 723 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 724                            bool shaders_read_metadata)
 725 {
 726         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
 727                          SI_CONTEXT_INV_VMEM_L1;
 728
 729         if (sctx->b.chip_class >= GFX9) {
 730                 /* Single-sample color is coherent with shaders on GFX9, but
 731                  * L2 metadata must be flushed if shaders read metadata.
 732                  * (DCC, CMASK).
 733                  */
 734                 if (num_samples >= 2)
 735                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 736                 else if (shaders_read_metadata)
 737                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 738         } else {
 739                 /* SI-CI-VI */
 740                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 741         }
 742 }
 743
 744 static inline void
 745 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 746                            bool include_stencil, bool shaders_read_metadata)
 747 {
 748         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
 749                          SI_CONTEXT_INV_VMEM_L1;
 750
 751         if (sctx->b.chip_class >= GFX9) {
 752                 /* Single-sample depth (not stencil) is coherent with shaders
 753                  * on GFX9, but L2 metadata must be flushed if shaders read
 754                  * metadata.
 755                  */
 756                 if (num_samples >= 2 || include_stencil)
 757                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 758                 else if (shaders_read_metadata)
 759                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 760         } else {
 761                 /* SI-CI-VI */
 762                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 763         }
 764 }
 765
 766 #endif