src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef SI_PIPE_H
  27 #define SI_PIPE_H
  28
  29 #include "si_shader.h"
  30
  31 #include "util/u_dynarray.h"
  32 #include "util/u_idalloc.h"
  33
  34 #ifdef PIPE_ARCH_BIG_ENDIAN
  35 #define SI_BIG_ENDIAN 1
  36 #else
  37 #define SI_BIG_ENDIAN 0
  38 #endif
  39
  40 /* The base vertex and primitive restart can be any number, but we must pick
  41  * one which will mean "unknown" for the purpose of state tracking and
  42  * the number shouldn't be a commonly-used one. */
  43 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  44 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  45 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  46 #define SI_GS_PER_ES 128
  47 /* Alignment for optimal CP DMA performance. */
  48 #define SI_CPDMA_ALIGNMENT      32
  49
  50 /* Instruction cache. */
  51 #define SI_CONTEXT_INV_ICACHE           (R600_CONTEXT_PRIVATE_FLAG << 0)
  52 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  53 #define SI_CONTEXT_INV_SMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 1)
  54 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  55 #define SI_CONTEXT_INV_VMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 2)
  56 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  57 #define SI_CONTEXT_INV_GLOBAL_L2        (R600_CONTEXT_PRIVATE_FLAG << 3)
  58 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  59  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
  60 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2  (R600_CONTEXT_PRIVATE_FLAG << 4)
  61 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
  62  * a CB or DB flush. */
  63 #define SI_CONTEXT_INV_L2_METADATA      (R600_CONTEXT_PRIVATE_FLAG << 5)
  64 /* Framebuffer caches. */
  65 #define SI_CONTEXT_FLUSH_AND_INV_DB     (R600_CONTEXT_PRIVATE_FLAG << 6)
  66 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 7)
  67 #define SI_CONTEXT_FLUSH_AND_INV_CB     (R600_CONTEXT_PRIVATE_FLAG << 8)
  68 /* Engine synchronization. */
  69 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 9)
  70 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 10)
  71 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 11)
  72 #define SI_CONTEXT_VGT_FLUSH            (R600_CONTEXT_PRIVATE_FLAG << 12)
  73 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (R600_CONTEXT_PRIVATE_FLAG << 13)
  74
  75 #define SI_PREFETCH_VBO_DESCRIPTORS     (1 << 0)
  76 #define SI_PREFETCH_LS                  (1 << 1)
  77 #define SI_PREFETCH_HS                  (1 << 2)
  78 #define SI_PREFETCH_ES                  (1 << 3)
  79 #define SI_PREFETCH_GS                  (1 << 4)
  80 #define SI_PREFETCH_VS                  (1 << 5)
  81 #define SI_PREFETCH_PS                  (1 << 6)
  82
  83 #define SI_MAX_BORDER_COLORS    4096
  84 #define SIX_BITS                0x3F
  85
  86 struct si_compute;
  87 struct hash_table;
  88 struct u_suballocator;
  89
  90 struct si_screen {
  91         struct r600_common_screen       b;
  92         unsigned                        gs_table_depth;
  93         unsigned                        tess_offchip_block_dw_size;
  94         bool                            has_clear_state;
  95         bool                            has_distributed_tess;
  96         bool                            has_draw_indirect_multi;
  97         bool                            has_ds_bpermute;
  98         bool                            has_msaa_sample_loc_bug;
  99         bool                            dpbb_allowed;
 100         bool                            dfsm_allowed;
 101         bool                            llvm_has_working_vgpr_indexing;
 102
 103         /* Whether shaders are monolithic (1-part) or separate (3-part). */
 104         bool                            use_monolithic_shaders;
 105         bool                            record_llvm_ir;
 106
 107         mtx_t                   shader_parts_mutex;
 108         struct si_shader_part           *vs_prologs;
 109         struct si_shader_part           *tcs_epilogs;
 110         struct si_shader_part           *gs_prologs;
 111         struct si_shader_part           *ps_prologs;
 112         struct si_shader_part           *ps_epilogs;
 113
 114         /* Shader cache in memory.
 115          *
 116          * Design & limitations:
 117          * - The shader cache is per screen (= per process), never saved to
 118          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 119          * - It can only be used with one-variant-per-shader support, in which
 120          *   case only the main (typically middle) part of shaders is cached.
 121          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 122          *   variants of VS and TES are cached, so LS and ES aren't.
 123          * - GS and CS aren't cached, but it's certainly possible to cache
 124          *   those as well.
 125          */
 126         mtx_t                   shader_cache_mutex;
 127         struct hash_table               *shader_cache;
 128
 129         /* Shader compiler queue for multithreaded compilation. */
 130         struct util_queue               shader_compiler_queue;
 131         /* Use at most 3 normal compiler threads on quadcore and better.
 132          * Hyperthreaded CPUs report the number of threads, but we want
 133          * the number of cores. */
 134         LLVMTargetMachineRef            tm[3]; /* used by the queue only */
 135
 136         struct util_queue               shader_compiler_queue_low_priority;
 137         /* Use at most 2 low priority threads on quadcore and better.
 138          * We want to minimize the impact on multithreaded Mesa. */
 139         LLVMTargetMachineRef            tm_low_priority[2]; /* at most 2 threads */
 140 };
 141
 142 struct si_blend_color {
 143         struct r600_atom                atom;
 144         struct pipe_blend_color         state;
 145         bool                            any_nonzeros;
 146 };
 147
 148 struct si_sampler_view {
 149         struct pipe_sampler_view        base;
 150         /* [0..7] = image descriptor
 151          * [4..7] = buffer descriptor */
 152         uint32_t                        state[8];
 153         uint32_t                        fmask_state[8];
 154         const struct legacy_surf_level  *base_level_info;
 155         ubyte                           base_level;
 156         ubyte                           block_width;
 157         bool is_stencil_sampler;
 158         bool dcc_incompatible;
 159 };
 160
 161 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
 162
 163 struct si_sampler_state {
 164 #ifdef DEBUG
 165         unsigned                        magic;
 166 #endif
 167         uint32_t                        val[4];
 168 };
 169
 170 struct si_cs_shader_state {
 171         struct si_compute               *program;
 172         struct si_compute               *emitted_program;
 173         unsigned                        offset;
 174         bool                            initialized;
 175         bool                            uses_scratch;
 176 };
 177
 178 struct si_textures_info {
 179         struct si_sampler_views         views;
 180         uint32_t                        needs_depth_decompress_mask;
 181         uint32_t                        needs_color_decompress_mask;
 182 };
 183
 184 struct si_images_info {
 185         struct pipe_image_view          views[SI_NUM_IMAGES];
 186         uint32_t                        needs_color_decompress_mask;
 187         unsigned                        enabled_mask;
 188 };
 189
 190 struct si_framebuffer {
 191         struct r600_atom                atom;
 192         struct pipe_framebuffer_state   state;
 193         unsigned                        colorbuf_enabled_4bit;
 194         unsigned                        spi_shader_col_format;
 195         unsigned                        spi_shader_col_format_alpha;
 196         unsigned                        spi_shader_col_format_blend;
 197         unsigned                        spi_shader_col_format_blend_alpha;
 198         ubyte                           nr_samples:5; /* at most 16xAA */
 199         ubyte                           log_samples:3; /* at most 4 = 16xAA */
 200         ubyte                           compressed_cb_mask;
 201         ubyte                           color_is_int8;
 202         ubyte                           color_is_int10;
 203         ubyte                           dirty_cbufs;
 204         bool                            dirty_zsbuf;
 205         bool                            any_dst_linear;
 206         bool                            CB_has_shader_readable_metadata;
 207         bool                            DB_has_shader_readable_metadata;
 208 };
 209
 210 struct si_clip_state {
 211         struct r600_atom                atom;
 212         struct pipe_clip_state          state;
 213         bool                            any_nonzeros;
 214 };
 215
 216 struct si_sample_locs {
 217         struct r600_atom        atom;
 218         unsigned                nr_samples;
 219 };
 220
 221 struct si_sample_mask {
 222         struct r600_atom        atom;
 223         uint16_t                sample_mask;
 224 };
 225
 226 /* A shader state consists of the shader selector, which is a constant state
 227  * object shared by multiple contexts and shouldn't be modified, and
 228  * the current shader variant selected for this context.
 229  */
 230 struct si_shader_ctx_state {
 231         struct si_shader_selector       *cso;
 232         struct si_shader                *current;
 233 };
 234
 235 #define SI_NUM_VGT_PARAM_KEY_BITS 12
 236 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
 237
 238 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
 239  * Some fields are set by state-change calls, most are set by draw_vbo.
 240  */
 241 union si_vgt_param_key {
 242         struct {
 243                 unsigned prim:4;
 244                 unsigned uses_instancing:1;
 245                 unsigned multi_instances_smaller_than_primgroup:1;
 246                 unsigned primitive_restart:1;
 247                 unsigned count_from_stream_output:1;
 248                 unsigned line_stipple_enabled:1;
 249                 unsigned uses_tess:1;
 250                 unsigned tess_uses_prim_id:1;
 251                 unsigned uses_gs:1;
 252                 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
 253         } u;
 254         uint32_t index;
 255 };
 256
 257 struct si_texture_handle
 258 {
 259         unsigned                        desc_slot;
 260         bool                            desc_dirty;
 261         struct pipe_sampler_view        *view;
 262         struct si_sampler_state         sstate;
 263 };
 264
 265 struct si_image_handle
 266 {
 267         unsigned                        desc_slot;
 268         bool                            desc_dirty;
 269         struct pipe_image_view          view;
 270 };
 271
 272 struct si_saved_cs {
 273         struct pipe_reference   reference;
 274         struct si_context       *ctx;
 275         struct radeon_saved_cs  gfx;
 276         struct r600_resource    *trace_buf;
 277         unsigned                trace_id;
 278
 279         unsigned                gfx_last_dw;
 280         bool                    flushed;
 281 };
 282
 283 struct si_context {
 284         struct r600_common_context      b;
 285         struct blitter_context          *blitter;
 286         void                            *custom_dsa_flush;
 287         void                            *custom_blend_resolve;
 288         void                            *custom_blend_fmask_decompress;
 289         void                            *custom_blend_eliminate_fastclear;
 290         void                            *custom_blend_dcc_decompress;
 291         struct si_screen                *screen;
 292         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 293         struct si_shader_ctx_state      fixed_func_tcs_shader;
 294         struct r600_resource            *wait_mem_scratch;
 295         unsigned                        wait_mem_number;
 296         uint16_t                        prefetch_L2_mask;
 297
 298         bool                            gfx_flush_in_progress:1;
 299         bool                            compute_is_busy:1;
 300
 301         /* Atoms (direct states). */
 302         union si_state_atoms            atoms;
 303         unsigned                        dirty_atoms; /* mask */
 304         /* PM4 states (precomputed immutable states) */
 305         unsigned                        dirty_states;
 306         union si_state                  queued;
 307         union si_state                  emitted;
 308
 309         /* Atom declarations. */
 310         struct si_framebuffer           framebuffer;
 311         struct si_sample_locs           msaa_sample_locs;
 312         struct r600_atom                db_render_state;
 313         struct r600_atom                dpbb_state;
 314         struct r600_atom                msaa_config;
 315         struct si_sample_mask           sample_mask;
 316         struct r600_atom                cb_render_state;
 317         unsigned                        last_cb_target_mask;
 318         struct si_blend_color           blend_color;
 319         struct r600_atom                clip_regs;
 320         struct si_clip_state            clip_state;
 321         struct si_shader_data           shader_pointers;
 322         struct si_stencil_ref           stencil_ref;
 323         struct r600_atom                spi_map;
 324
 325         /* Precomputed states. */
 326         struct si_pm4_state             *init_config;
 327         struct si_pm4_state             *init_config_gs_rings;
 328         bool                            init_config_has_vgt_flush;
 329         struct si_pm4_state             *vgt_shader_config[4];
 330
 331         /* shaders */
 332         struct si_shader_ctx_state      ps_shader;
 333         struct si_shader_ctx_state      gs_shader;
 334         struct si_shader_ctx_state      vs_shader;
 335         struct si_shader_ctx_state      tcs_shader;
 336         struct si_shader_ctx_state      tes_shader;
 337         struct si_cs_shader_state       cs_shader_state;
 338
 339         /* shader information */
 340         struct si_vertex_elements       *vertex_elements;
 341         unsigned                        sprite_coord_enable;
 342         bool                            flatshade;
 343         bool                            do_update_shaders;
 344
 345         /* shader descriptors */
 346         struct si_descriptors           vertex_buffers;
 347         struct si_descriptors           descriptors[SI_NUM_DESCS];
 348         unsigned                        descriptors_dirty;
 349         unsigned                        shader_pointers_dirty;
 350         unsigned                        shader_needs_decompress_mask;
 351         struct si_buffer_resources      rw_buffers;
 352         struct si_buffer_resources      const_and_shader_buffers[SI_NUM_SHADERS];
 353         struct si_textures_info         samplers[SI_NUM_SHADERS];
 354         struct si_images_info           images[SI_NUM_SHADERS];
 355
 356         /* other shader resources */
 357         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 358         struct pipe_resource            *esgs_ring;
 359         struct pipe_resource            *gsvs_ring;
 360         struct pipe_resource            *tf_ring;
 361         struct pipe_resource            *tess_offchip_ring;
 362         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 363         struct r600_resource            *border_color_buffer;
 364         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 365         unsigned                        border_color_count;
 366
 367         /* Vertex and index buffers. */
 368         bool                            vertex_buffers_dirty;
 369         bool                            vertex_buffer_pointer_dirty;
 370         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 371
 372         /* MSAA config state. */
 373         int                             ps_iter_samples;
 374         bool                            smoothing_enabled;
 375
 376         /* DB render state. */
 377         unsigned                ps_db_shader_control;
 378         unsigned                dbcb_copy_sample;
 379         bool                    dbcb_depth_copy_enabled:1;
 380         bool                    dbcb_stencil_copy_enabled:1;
 381         bool                    db_flush_depth_inplace:1;
 382         bool                    db_flush_stencil_inplace:1;
 383         bool                    db_depth_clear:1;
 384         bool                    db_depth_disable_expclear:1;
 385         bool                    db_stencil_clear:1;
 386         bool                    db_stencil_disable_expclear:1;
 387         bool                    occlusion_queries_disabled:1;
 388         bool                    generate_mipmap_for_depth:1;
 389
 390         /* Emitted draw state. */
 391         bool                    gs_tri_strip_adj_fix:1;
 392         int                     last_index_size;
 393         int                     last_base_vertex;
 394         int                     last_start_instance;
 395         int                     last_drawid;
 396         int                     last_sh_base_reg;
 397         int                     last_primitive_restart_en;
 398         int                     last_restart_index;
 399         int                     last_gs_out_prim;
 400         int                     last_prim;
 401         int                     last_multi_vgt_param;
 402         int                     last_rast_prim;
 403         unsigned                last_sc_line_stipple;
 404         unsigned                current_vs_state;
 405         unsigned                last_vs_state;
 406         enum pipe_prim_type     current_rast_prim; /* primitive type after TES, GS */
 407
 408         /* Scratch buffer */
 409         struct r600_atom        scratch_state;
 410         struct r600_resource    *scratch_buffer;
 411         unsigned                scratch_waves;
 412         unsigned                spi_tmpring_size;
 413
 414         struct r600_resource    *compute_scratch_buffer;
 415
 416         /* Emitted derived tessellation state. */
 417         /* Local shader (VS), or HS if LS-HS are merged. */
 418         struct si_shader        *last_ls;
 419         struct si_shader_selector *last_tcs;
 420         int                     last_num_tcs_input_cp;
 421         int                     last_tes_sh_base;
 422         bool                    last_tess_uses_primid;
 423         unsigned                last_num_patches;
 424
 425         /* Debug state. */
 426         bool                    is_debug;
 427         struct si_saved_cs      *current_saved_cs;
 428         uint64_t                dmesg_timestamp;
 429         unsigned                apitrace_call_number;
 430
 431         /* Other state */
 432         bool need_check_render_feedback;
 433         bool                    decompression_enabled;
 434
 435         /* Precomputed IA_MULTI_VGT_PARAM */
 436         union si_vgt_param_key  ia_multi_vgt_param_key;
 437         unsigned                ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
 438
 439         /* Bindless descriptors. */
 440         struct si_descriptors   bindless_descriptors;
 441         struct util_idalloc     bindless_used_slots;
 442         unsigned                num_bindless_descriptors;
 443         bool                    bindless_descriptors_dirty;
 444         bool                    graphics_bindless_pointer_dirty;
 445         bool                    compute_bindless_pointer_dirty;
 446
 447         /* Allocated bindless handles */
 448         struct hash_table       *tex_handles;
 449         struct hash_table       *img_handles;
 450
 451         /* Resident bindless handles */
 452         struct util_dynarray    resident_tex_handles;
 453         struct util_dynarray    resident_img_handles;
 454
 455         /* Resident bindless handles which need decompression */
 456         struct util_dynarray    resident_tex_needs_color_decompress;
 457         struct util_dynarray    resident_img_needs_color_decompress;
 458         struct util_dynarray    resident_tex_needs_depth_decompress;
 459
 460         /* Bindless state */
 461         bool                    uses_bindless_samplers;
 462         bool                    uses_bindless_images;
 463 };
 464
 465 /* cik_sdma.c */
 466 void cik_init_sdma_functions(struct si_context *sctx);
 467
 468 /* si_blit.c */
 469 void si_init_blit_functions(struct si_context *sctx);
 470 void si_decompress_graphics_textures(struct si_context *sctx);
 471 void si_decompress_compute_textures(struct si_context *sctx);
 472 void si_resource_copy_region(struct pipe_context *ctx,
 473                              struct pipe_resource *dst,
 474                              unsigned dst_level,
 475                              unsigned dstx, unsigned dsty, unsigned dstz,
 476                              struct pipe_resource *src,
 477                              unsigned src_level,
 478                              const struct pipe_box *src_box);
 479
 480 /* si_cp_dma.c */
 481 #define SI_CPDMA_SKIP_CHECK_CS_SPACE    (1 << 0) /* don't call need_cs_space */
 482 #define SI_CPDMA_SKIP_SYNC_AFTER        (1 << 1) /* don't wait for DMA after the copy */
 483 #define SI_CPDMA_SKIP_SYNC_BEFORE       (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
 484 #define SI_CPDMA_SKIP_GFX_SYNC          (1 << 3) /* don't flush caches and don't wait for PS/CS */
 485 #define SI_CPDMA_SKIP_BO_LIST_UPDATE    (1 << 4) /* don't update the BO list */
 486 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
 487                            SI_CPDMA_SKIP_SYNC_AFTER | \
 488                            SI_CPDMA_SKIP_SYNC_BEFORE | \
 489                            SI_CPDMA_SKIP_GFX_SYNC | \
 490                            SI_CPDMA_SKIP_BO_LIST_UPDATE)
 491
 492 void si_copy_buffer(struct si_context *sctx,
 493                     struct pipe_resource *dst, struct pipe_resource *src,
 494                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 495                     unsigned user_flags);
 496 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 497                               uint64_t offset, unsigned size);
 498 void cik_emit_prefetch_L2(struct si_context *sctx);
 499 void si_init_cp_dma_functions(struct si_context *sctx);
 500
 501 /* si_debug.c */
 502 void si_auto_log_cs(void *data, struct u_log_context *log);
 503 void si_log_hw_flush(struct si_context *sctx);
 504 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
 505 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
 506 void si_init_debug_functions(struct si_context *sctx);
 507 void si_check_vm_faults(struct r600_common_context *ctx,
 508                         struct radeon_saved_cs *saved, enum ring_type ring);
 509 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
 510
 511 /* si_dma.c */
 512 void si_init_dma_functions(struct si_context *sctx);
 513
 514 /* si_hw_context.c */
 515 void si_destroy_saved_cs(struct si_saved_cs *scs);
 516 void si_context_gfx_flush(void *context, unsigned flags,
 517                           struct pipe_fence_handle **fence);
 518 void si_begin_new_cs(struct si_context *ctx);
 519 void si_need_cs_space(struct si_context *ctx);
 520
 521 /* si_compute.c */
 522 void si_init_compute_functions(struct si_context *sctx);
 523
 524 /* si_perfcounters.c */
 525 void si_init_perfcounters(struct si_screen *screen);
 526
 527 /* si_uvd.c */
 528 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 529                                                const struct pipe_video_codec *templ);
 530
 531 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 532                                                  const struct pipe_video_buffer *tmpl);
 533
 534 /*
 535  * common helpers
 536  */
 537
 538 static inline void
 539 si_invalidate_draw_sh_constants(struct si_context *sctx)
 540 {
 541         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 542 }
 543
 544 static inline void
 545 si_set_atom_dirty(struct si_context *sctx,
 546                   struct r600_atom *atom, bool dirty)
 547 {
 548         unsigned bit = 1 << atom->id;
 549
 550         if (dirty)
 551                 sctx->dirty_atoms |= bit;
 552         else
 553                 sctx->dirty_atoms &= ~bit;
 554 }
 555
 556 static inline bool
 557 si_is_atom_dirty(struct si_context *sctx,
 558                   struct r600_atom *atom)
 559 {
 560         unsigned bit = 1 << atom->id;
 561
 562         return sctx->dirty_atoms & bit;
 563 }
 564
 565 static inline void
 566 si_mark_atom_dirty(struct si_context *sctx,
 567                    struct r600_atom *atom)
 568 {
 569         si_set_atom_dirty(sctx, atom, true);
 570 }
 571
 572 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
 573 {
 574         if (sctx->gs_shader.cso)
 575                 return &sctx->gs_shader;
 576         if (sctx->tes_shader.cso)
 577                 return &sctx->tes_shader;
 578
 579         return &sctx->vs_shader;
 580 }
 581
 582 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 583 {
 584         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 585
 586         return vs->cso ? &vs->cso->info : NULL;
 587 }
 588
 589 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 590 {
 591         if (sctx->gs_shader.cso)
 592                 return sctx->gs_shader.cso->gs_copy_shader;
 593
 594         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 595         return vs->current ? vs->current : NULL;
 596 }
 597
 598 static inline unsigned
 599 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
 600 {
 601         unsigned alignment, tcc_cache_line_size;
 602
 603         /* If the upload size is less than the cache line size (e.g. 16, 32),
 604          * the whole thing will fit into a cache line if we align it to its size.
 605          * The idea is that multiple small uploads can share a cache line.
 606          * If the upload size is greater, align it to the cache line size.
 607          */
 608         alignment = util_next_power_of_two(upload_size);
 609         tcc_cache_line_size = sctx->screen->b.info.tcc_cache_line_size;
 610         return MIN2(alignment, tcc_cache_line_size);
 611 }
 612
 613 static inline void
 614 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
 615 {
 616         if (pipe_reference(&(*dst)->reference, &src->reference))
 617                 si_destroy_saved_cs(*dst);
 618
 619         *dst = src;
 620 }
 621
 622 static inline void
 623 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 624                            bool shaders_read_metadata)
 625 {
 626         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
 627                          SI_CONTEXT_INV_VMEM_L1;
 628
 629         if (sctx->b.chip_class >= GFX9) {
 630                 /* Single-sample color is coherent with shaders on GFX9, but
 631                  * L2 metadata must be flushed if shaders read metadata.
 632                  * (DCC, CMASK).
 633                  */
 634                 if (num_samples >= 2)
 635                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 636                 else if (shaders_read_metadata)
 637                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 638         } else {
 639                 /* SI-CI-VI */
 640                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 641         }
 642 }
 643
 644 static inline void
 645 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 646                            bool include_stencil, bool shaders_read_metadata)
 647 {
 648         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
 649                          SI_CONTEXT_INV_VMEM_L1;
 650
 651         if (sctx->b.chip_class >= GFX9) {
 652                 /* Single-sample depth (not stencil) is coherent with shaders
 653                  * on GFX9, but L2 metadata must be flushed if shaders read
 654                  * metadata.
 655                  */
 656                 if (num_samples >= 2 || include_stencil)
 657                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 658                 else if (shaders_read_metadata)
 659                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 660         } else {
 661                 /* SI-CI-VI */
 662                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 663         }
 664 }
 665
 666 #endif