2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "si_shader.h"
31 #ifdef PIPE_ARCH_BIG_ENDIAN
32 #define SI_BIG_ENDIAN 1
34 #define SI_BIG_ENDIAN 0
37 /* The base vertex and primitive restart can be any number, but we must pick
38 * one which will mean "unknown" for the purpose of state tracking and
39 * the number shouldn't be a commonly-used one. */
40 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
41 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
42 #define SI_NUM_SMOOTH_AA_SAMPLES 8
43 #define SI_GS_PER_ES 128
45 /* Instruction cache. */
46 #define SI_CONTEXT_INV_ICACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
47 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
48 #define SI_CONTEXT_INV_SMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 1)
49 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
50 #define SI_CONTEXT_INV_VMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 2)
51 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
52 #define SI_CONTEXT_INV_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 3)
53 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
54 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
55 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 4)
57 /* Framebuffer caches. */
58 #define SI_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 7)
59 #define SI_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 8)
60 /* Engine synchronization. */
61 #define SI_CONTEXT_VS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 9)
62 #define SI_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 10)
63 #define SI_CONTEXT_CS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 11)
64 #define SI_CONTEXT_VGT_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 12)
65 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (R600_CONTEXT_PRIVATE_FLAG << 13)
67 #define SI_MAX_BORDER_COLORS 4096
71 struct u_suballocator
;
74 struct r600_common_screen b
;
75 unsigned gs_table_depth
;
76 unsigned tess_offchip_block_dw_size
;
77 bool has_distributed_tess
;
78 bool has_draw_indirect_multi
;
81 /* Whether shaders are monolithic (1-part) or separate (3-part). */
82 bool use_monolithic_shaders
;
85 pipe_mutex shader_parts_mutex
;
86 struct si_shader_part
*vs_prologs
;
87 struct si_shader_part
*vs_epilogs
;
88 struct si_shader_part
*tcs_epilogs
;
89 struct si_shader_part
*gs_prologs
;
90 struct si_shader_part
*ps_prologs
;
91 struct si_shader_part
*ps_epilogs
;
93 /* Shader cache in memory.
95 * Design & limitations:
96 * - The shader cache is per screen (= per process), never saved to
97 * disk, and skips redundant shader compilations from TGSI to bytecode.
98 * - It can only be used with one-variant-per-shader support, in which
99 * case only the main (typically middle) part of shaders is cached.
100 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
101 * variants of VS and TES are cached, so LS and ES aren't.
102 * - GS and CS aren't cached, but it's certainly possible to cache
105 pipe_mutex shader_cache_mutex
;
106 struct hash_table
*shader_cache
;
108 /* Shader compiler queue for multithreaded compilation. */
109 struct util_queue shader_compiler_queue
;
110 LLVMTargetMachineRef tm
[4]; /* used by the queue only */
113 struct si_blend_color
{
114 struct r600_atom atom
;
115 struct pipe_blend_color state
;
118 struct si_sampler_view
{
119 struct pipe_sampler_view base
;
120 /* [0..7] = image descriptor
121 * [4..7] = buffer descriptor */
123 uint32_t fmask_state
[8];
124 const struct radeon_surf_level
*base_level_info
;
126 unsigned block_width
;
127 bool is_stencil_sampler
;
130 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
132 struct si_sampler_state
{
139 struct si_cs_shader_state
{
140 struct si_compute
*program
;
141 struct si_compute
*emitted_program
;
147 struct si_textures_info
{
148 struct si_sampler_views views
;
149 uint32_t depth_texture_mask
; /* which textures are depth */
150 uint32_t compressed_colortex_mask
;
153 struct si_images_info
{
154 struct pipe_image_view views
[SI_NUM_IMAGES
];
155 uint32_t compressed_colortex_mask
;
156 unsigned enabled_mask
;
159 struct si_framebuffer
{
160 struct r600_atom atom
;
161 struct pipe_framebuffer_state state
;
163 unsigned log_samples
;
164 unsigned compressed_cb_mask
;
165 unsigned colorbuf_enabled_4bit
;
166 unsigned spi_shader_col_format
;
167 unsigned spi_shader_col_format_alpha
;
168 unsigned spi_shader_col_format_blend
;
169 unsigned spi_shader_col_format_blend_alpha
;
170 unsigned color_is_int8
; /* bitmask */
171 unsigned dirty_cbufs
;
174 bool do_update_surf_dirtiness
;
177 struct si_clip_state
{
178 struct r600_atom atom
;
179 struct pipe_clip_state state
;
182 struct si_sample_locs
{
183 struct r600_atom atom
;
187 struct si_sample_mask
{
188 struct r600_atom atom
;
189 uint16_t sample_mask
;
192 /* A shader state consists of the shader selector, which is a constant state
193 * object shared by multiple contexts and shouldn't be modified, and
194 * the current shader variant selected for this context.
196 struct si_shader_ctx_state
{
197 struct si_shader_selector
*cso
;
198 struct si_shader
*current
;
201 #define SI_NUM_VGT_PARAM_KEY_BITS 12
202 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
204 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
205 * Some fields are set by state-change calls, most are set by draw_vbo.
207 union si_vgt_param_key
{
210 unsigned uses_instancing
:1;
211 unsigned multi_instances_smaller_than_primgroup
:1;
212 unsigned primitive_restart
:1;
213 unsigned count_from_stream_output
:1;
214 unsigned line_stipple_enabled
:1;
215 unsigned uses_tess
:1;
216 unsigned tcs_tes_uses_prim_id
:1;
218 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
224 struct r600_common_context b
;
225 struct blitter_context
*blitter
;
226 void *custom_dsa_flush
;
227 void *custom_blend_resolve
;
228 void *custom_blend_decompress
;
229 void *custom_blend_fastclear
;
230 void *custom_blend_dcc_decompress
;
231 struct si_screen
*screen
;
233 struct radeon_winsys_cs
*ce_ib
;
234 struct radeon_winsys_cs
*ce_preamble_ib
;
235 bool ce_need_synchronization
;
236 struct u_suballocator
*ce_suballocator
;
238 struct si_shader_ctx_state fixed_func_tcs_shader
;
239 LLVMTargetMachineRef tm
; /* only non-threaded compilation */
240 bool gfx_flush_in_progress
;
241 bool compute_is_busy
;
243 /* Atoms (direct states). */
244 union si_state_atoms atoms
;
245 unsigned dirty_atoms
; /* mask */
246 /* PM4 states (precomputed immutable states) */
247 unsigned dirty_states
;
248 union si_state queued
;
249 union si_state emitted
;
251 /* Atom declarations. */
252 struct r600_atom prefetch_L2
;
253 struct si_framebuffer framebuffer
;
254 struct si_sample_locs msaa_sample_locs
;
255 struct r600_atom db_render_state
;
256 struct r600_atom msaa_config
;
257 struct si_sample_mask sample_mask
;
258 struct r600_atom cb_render_state
;
259 struct si_blend_color blend_color
;
260 struct r600_atom clip_regs
;
261 struct si_clip_state clip_state
;
262 struct si_shader_data shader_userdata
;
263 struct si_stencil_ref stencil_ref
;
264 struct r600_atom spi_map
;
266 /* Precomputed states. */
267 struct si_pm4_state
*init_config
;
268 struct si_pm4_state
*init_config_gs_rings
;
269 bool init_config_has_vgt_flush
;
270 struct si_pm4_state
*vgt_shader_config
[4];
273 struct si_shader_ctx_state ps_shader
;
274 struct si_shader_ctx_state gs_shader
;
275 struct si_shader_ctx_state vs_shader
;
276 struct si_shader_ctx_state tcs_shader
;
277 struct si_shader_ctx_state tes_shader
;
278 struct si_cs_shader_state cs_shader_state
;
280 /* shader information */
281 struct si_vertex_element
*vertex_elements
;
282 unsigned sprite_coord_enable
;
284 bool do_update_shaders
;
286 /* shader descriptors */
287 struct si_descriptors vertex_buffers
;
288 struct si_descriptors descriptors
[SI_NUM_DESCS
];
289 unsigned descriptors_dirty
;
290 unsigned shader_pointers_dirty
;
291 unsigned compressed_tex_shader_mask
;
292 struct si_buffer_resources rw_buffers
;
293 struct si_buffer_resources const_buffers
[SI_NUM_SHADERS
];
294 struct si_buffer_resources shader_buffers
[SI_NUM_SHADERS
];
295 struct si_textures_info samplers
[SI_NUM_SHADERS
];
296 struct si_images_info images
[SI_NUM_SHADERS
];
298 /* other shader resources */
299 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on CIK */
300 struct pipe_resource
*esgs_ring
;
301 struct pipe_resource
*gsvs_ring
;
302 struct pipe_resource
*tf_ring
;
303 struct pipe_resource
*tess_offchip_ring
;
304 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
305 struct r600_resource
*border_color_buffer
;
306 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
307 unsigned border_color_count
;
309 /* Vertex and index buffers. */
310 bool vertex_buffers_dirty
;
311 bool vertex_buffer_pointer_dirty
;
312 struct pipe_index_buffer index_buffer
;
313 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
315 /* MSAA config state. */
317 bool smoothing_enabled
;
319 /* DB render state. */
320 bool dbcb_depth_copy_enabled
;
321 bool dbcb_stencil_copy_enabled
;
322 unsigned dbcb_copy_sample
;
323 bool db_flush_depth_inplace
;
324 bool db_flush_stencil_inplace
;
326 bool db_depth_disable_expclear
;
327 bool db_stencil_clear
;
328 bool db_stencil_disable_expclear
;
329 unsigned ps_db_shader_control
;
330 bool occlusion_queries_disabled
;
332 /* Emitted draw state. */
334 int last_base_vertex
;
335 int last_start_instance
;
337 int last_sh_base_reg
;
338 int last_primitive_restart_en
;
339 int last_restart_index
;
340 int last_gs_out_prim
;
342 int last_multi_vgt_param
;
344 unsigned last_sc_line_stipple
;
345 int current_rast_prim
; /* primitive type after TES, GS */
346 bool gs_tri_strip_adj_fix
;
349 struct r600_atom scratch_state
;
350 struct r600_resource
*scratch_buffer
;
351 unsigned scratch_waves
;
352 unsigned spi_tmpring_size
;
354 struct r600_resource
*compute_scratch_buffer
;
356 /* Emitted derived tessellation state. */
357 struct si_shader
*last_ls
; /* local shader (VS) */
358 struct si_shader_selector
*last_tcs
;
359 int last_num_tcs_input_cp
;
360 int last_tes_sh_base
;
361 unsigned last_num_patches
;
365 struct radeon_saved_cs last_gfx
;
366 struct r600_resource
*last_trace_buf
;
367 struct r600_resource
*trace_buf
;
369 uint64_t dmesg_timestamp
;
370 unsigned apitrace_call_number
;
373 bool need_check_render_feedback
;
375 /* Precomputed IA_MULTI_VGT_PARAM */
376 union si_vgt_param_key ia_multi_vgt_param_key
;
377 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
381 void cik_init_sdma_functions(struct si_context
*sctx
);
384 void si_init_blit_functions(struct si_context
*sctx
);
385 void si_decompress_graphics_textures(struct si_context
*sctx
);
386 void si_decompress_compute_textures(struct si_context
*sctx
);
387 void si_resource_copy_region(struct pipe_context
*ctx
,
388 struct pipe_resource
*dst
,
390 unsigned dstx
, unsigned dsty
, unsigned dstz
,
391 struct pipe_resource
*src
,
393 const struct pipe_box
*src_box
);
396 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
397 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
398 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
399 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
400 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
401 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
402 SI_CPDMA_SKIP_SYNC_AFTER | \
403 SI_CPDMA_SKIP_SYNC_BEFORE | \
404 SI_CPDMA_SKIP_GFX_SYNC | \
405 SI_CPDMA_SKIP_BO_LIST_UPDATE)
407 void si_copy_buffer(struct si_context
*sctx
,
408 struct pipe_resource
*dst
, struct pipe_resource
*src
,
409 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
410 unsigned user_flags
);
411 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
412 uint64_t offset
, unsigned size
);
413 void si_init_cp_dma_functions(struct si_context
*sctx
);
416 void si_init_debug_functions(struct si_context
*sctx
);
417 void si_check_vm_faults(struct r600_common_context
*ctx
,
418 struct radeon_saved_cs
*saved
, enum ring_type ring
);
419 bool si_replace_shader(unsigned num
, struct radeon_shader_binary
*binary
);
422 void si_init_dma_functions(struct si_context
*sctx
);
424 /* si_hw_context.c */
425 void si_context_gfx_flush(void *context
, unsigned flags
,
426 struct pipe_fence_handle
**fence
);
427 void si_begin_new_cs(struct si_context
*ctx
);
428 void si_need_cs_space(struct si_context
*ctx
);
431 void si_init_compute_functions(struct si_context
*sctx
);
433 /* si_perfcounters.c */
434 void si_init_perfcounters(struct si_screen
*screen
);
437 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
438 const struct pipe_video_codec
*templ
);
440 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
441 const struct pipe_video_buffer
*tmpl
);
448 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
450 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
454 si_set_atom_dirty(struct si_context
*sctx
,
455 struct r600_atom
*atom
, bool dirty
)
457 unsigned bit
= 1 << atom
->id
;
460 sctx
->dirty_atoms
|= bit
;
462 sctx
->dirty_atoms
&= ~bit
;
466 si_is_atom_dirty(struct si_context
*sctx
,
467 struct r600_atom
*atom
)
469 unsigned bit
= 1 << atom
->id
;
471 return sctx
->dirty_atoms
& bit
;
475 si_mark_atom_dirty(struct si_context
*sctx
,
476 struct r600_atom
*atom
)
478 si_set_atom_dirty(sctx
, atom
, true);
481 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
483 if (sctx
->gs_shader
.cso
)
484 return &sctx
->gs_shader
.cso
->info
;
485 else if (sctx
->tes_shader
.cso
)
486 return &sctx
->tes_shader
.cso
->info
;
487 else if (sctx
->vs_shader
.cso
)
488 return &sctx
->vs_shader
.cso
->info
;
493 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
495 if (sctx
->gs_shader
.current
)
496 return sctx
->gs_shader
.cso
->gs_copy_shader
;
497 else if (sctx
->tes_shader
.current
)
498 return sctx
->tes_shader
.current
;
500 return sctx
->vs_shader
.current
;
503 static inline bool si_vs_exports_prim_id(struct si_shader
*shader
)
505 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
)
506 return shader
->key
.part
.vs
.epilog
.export_prim_id
;
507 else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
508 return shader
->key
.part
.tes
.epilog
.export_prim_id
;