src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef SI_PIPE_H
  27 #define SI_PIPE_H
  28
  29 #include "si_shader.h"
  30
  31 #include "util/u_dynarray.h"
  32 #include "util/u_idalloc.h"
  33
  34 #ifdef PIPE_ARCH_BIG_ENDIAN
  35 #define SI_BIG_ENDIAN 1
  36 #else
  37 #define SI_BIG_ENDIAN 0
  38 #endif
  39
  40 /* The base vertex and primitive restart can be any number, but we must pick
  41  * one which will mean "unknown" for the purpose of state tracking and
  42  * the number shouldn't be a commonly-used one. */
  43 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  44 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  45 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  46 #define SI_GS_PER_ES 128
  47 /* Alignment for optimal CP DMA performance. */
  48 #define SI_CPDMA_ALIGNMENT      32
  49
  50 /* Instruction cache. */
  51 #define SI_CONTEXT_INV_ICACHE           (R600_CONTEXT_PRIVATE_FLAG << 0)
  52 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  53 #define SI_CONTEXT_INV_SMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 1)
  54 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  55 #define SI_CONTEXT_INV_VMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 2)
  56 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  57 #define SI_CONTEXT_INV_GLOBAL_L2        (R600_CONTEXT_PRIVATE_FLAG << 3)
  58 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  59  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
  60 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2  (R600_CONTEXT_PRIVATE_FLAG << 4)
  61 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
  62  * a CB or DB flush. */
  63 #define SI_CONTEXT_INV_L2_METADATA      (R600_CONTEXT_PRIVATE_FLAG << 5)
  64 /* Framebuffer caches. */
  65 #define SI_CONTEXT_FLUSH_AND_INV_DB     (R600_CONTEXT_PRIVATE_FLAG << 6)
  66 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 7)
  67 #define SI_CONTEXT_FLUSH_AND_INV_CB     (R600_CONTEXT_PRIVATE_FLAG << 8)
  68 /* Engine synchronization. */
  69 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 9)
  70 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 10)
  71 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 11)
  72 #define SI_CONTEXT_VGT_FLUSH            (R600_CONTEXT_PRIVATE_FLAG << 12)
  73 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (R600_CONTEXT_PRIVATE_FLAG << 13)
  74
  75 #define SI_PREFETCH_VBO_DESCRIPTORS     (1 << 0)
  76 #define SI_PREFETCH_LS                  (1 << 1)
  77 #define SI_PREFETCH_HS                  (1 << 2)
  78 #define SI_PREFETCH_ES                  (1 << 3)
  79 #define SI_PREFETCH_GS                  (1 << 4)
  80 #define SI_PREFETCH_VS                  (1 << 5)
  81 #define SI_PREFETCH_PS                  (1 << 6)
  82
  83 #define SI_MAX_BORDER_COLORS    4096
  84 #define SI_MAX_VIEWPORTS        16
  85 #define SIX_BITS                0x3F
  86
  87 struct si_compute;
  88 struct hash_table;
  89 struct u_suballocator;
  90
  91 struct si_screen {
  92         struct r600_common_screen       b;
  93         unsigned                        gs_table_depth;
  94         unsigned                        tess_offchip_block_dw_size;
  95         bool                            has_clear_state;
  96         bool                            has_distributed_tess;
  97         bool                            has_draw_indirect_multi;
  98         bool                            has_out_of_order_rast;
  99         bool                            assume_no_z_fights;
 100         bool                            commutative_blend_add;
 101         bool                            has_msaa_sample_loc_bug;
 102         bool                            dpbb_allowed;
 103         bool                            dfsm_allowed;
 104         bool                            llvm_has_working_vgpr_indexing;
 105
 106         /* Whether shaders are monolithic (1-part) or separate (3-part). */
 107         bool                            use_monolithic_shaders;
 108         bool                            record_llvm_ir;
 109
 110         mtx_t                   shader_parts_mutex;
 111         struct si_shader_part           *vs_prologs;
 112         struct si_shader_part           *tcs_epilogs;
 113         struct si_shader_part           *gs_prologs;
 114         struct si_shader_part           *ps_prologs;
 115         struct si_shader_part           *ps_epilogs;
 116
 117         /* Shader cache in memory.
 118          *
 119          * Design & limitations:
 120          * - The shader cache is per screen (= per process), never saved to
 121          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 122          * - It can only be used with one-variant-per-shader support, in which
 123          *   case only the main (typically middle) part of shaders is cached.
 124          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 125          *   variants of VS and TES are cached, so LS and ES aren't.
 126          * - GS and CS aren't cached, but it's certainly possible to cache
 127          *   those as well.
 128          */
 129         mtx_t                   shader_cache_mutex;
 130         struct hash_table               *shader_cache;
 131
 132         /* Shader compiler queue for multithreaded compilation. */
 133         struct util_queue               shader_compiler_queue;
 134         /* Use at most 3 normal compiler threads on quadcore and better.
 135          * Hyperthreaded CPUs report the number of threads, but we want
 136          * the number of cores. */
 137         LLVMTargetMachineRef            tm[3]; /* used by the queue only */
 138
 139         struct util_queue               shader_compiler_queue_low_priority;
 140         /* Use at most 2 low priority threads on quadcore and better.
 141          * We want to minimize the impact on multithreaded Mesa. */
 142         LLVMTargetMachineRef            tm_low_priority[2]; /* at most 2 threads */
 143 };
 144
 145 struct si_blend_color {
 146         struct r600_atom                atom;
 147         struct pipe_blend_color         state;
 148         bool                            any_nonzeros;
 149 };
 150
 151 struct si_sampler_view {
 152         struct pipe_sampler_view        base;
 153         /* [0..7] = image descriptor
 154          * [4..7] = buffer descriptor */
 155         uint32_t                        state[8];
 156         uint32_t                        fmask_state[8];
 157         const struct legacy_surf_level  *base_level_info;
 158         ubyte                           base_level;
 159         ubyte                           block_width;
 160         bool is_stencil_sampler;
 161         bool is_integer;
 162         bool dcc_incompatible;
 163 };
 164
 165 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
 166
 167 struct si_sampler_state {
 168 #ifdef DEBUG
 169         unsigned                        magic;
 170 #endif
 171         uint32_t                        val[4];
 172         uint32_t                        integer_val[4];
 173         uint32_t                        upgraded_depth_val[4];
 174 };
 175
 176 struct si_cs_shader_state {
 177         struct si_compute               *program;
 178         struct si_compute               *emitted_program;
 179         unsigned                        offset;
 180         bool                            initialized;
 181         bool                            uses_scratch;
 182 };
 183
 184 struct si_textures_info {
 185         struct si_sampler_views         views;
 186         uint32_t                        needs_depth_decompress_mask;
 187         uint32_t                        needs_color_decompress_mask;
 188 };
 189
 190 struct si_images_info {
 191         struct pipe_image_view          views[SI_NUM_IMAGES];
 192         uint32_t                        needs_color_decompress_mask;
 193         unsigned                        enabled_mask;
 194 };
 195
 196 struct si_framebuffer {
 197         struct r600_atom                atom;
 198         struct pipe_framebuffer_state   state;
 199         unsigned                        colorbuf_enabled_4bit;
 200         unsigned                        spi_shader_col_format;
 201         unsigned                        spi_shader_col_format_alpha;
 202         unsigned                        spi_shader_col_format_blend;
 203         unsigned                        spi_shader_col_format_blend_alpha;
 204         ubyte                           nr_samples:5; /* at most 16xAA */
 205         ubyte                           log_samples:3; /* at most 4 = 16xAA */
 206         ubyte                           compressed_cb_mask;
 207         ubyte                           color_is_int8;
 208         ubyte                           color_is_int10;
 209         ubyte                           dirty_cbufs;
 210         bool                            dirty_zsbuf;
 211         bool                            any_dst_linear;
 212         bool                            CB_has_shader_readable_metadata;
 213         bool                            DB_has_shader_readable_metadata;
 214 };
 215
 216 struct si_signed_scissor {
 217         int minx;
 218         int miny;
 219         int maxx;
 220         int maxy;
 221 };
 222
 223 struct si_scissors {
 224         struct r600_atom                atom;
 225         unsigned                        dirty_mask;
 226         struct pipe_scissor_state       states[SI_MAX_VIEWPORTS];
 227 };
 228
 229 struct si_viewports {
 230         struct r600_atom                atom;
 231         unsigned                        dirty_mask;
 232         unsigned                        depth_range_dirty_mask;
 233         struct pipe_viewport_state      states[SI_MAX_VIEWPORTS];
 234         struct si_signed_scissor        as_scissor[SI_MAX_VIEWPORTS];
 235 };
 236
 237 struct si_clip_state {
 238         struct r600_atom                atom;
 239         struct pipe_clip_state          state;
 240         bool                            any_nonzeros;
 241 };
 242
 243 struct si_sample_locs {
 244         struct r600_atom        atom;
 245         unsigned                nr_samples;
 246 };
 247
 248 struct si_sample_mask {
 249         struct r600_atom        atom;
 250         uint16_t                sample_mask;
 251 };
 252
 253 /* A shader state consists of the shader selector, which is a constant state
 254  * object shared by multiple contexts and shouldn't be modified, and
 255  * the current shader variant selected for this context.
 256  */
 257 struct si_shader_ctx_state {
 258         struct si_shader_selector       *cso;
 259         struct si_shader                *current;
 260 };
 261
 262 #define SI_NUM_VGT_PARAM_KEY_BITS 12
 263 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
 264
 265 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
 266  * Some fields are set by state-change calls, most are set by draw_vbo.
 267  */
 268 union si_vgt_param_key {
 269         struct {
 270                 unsigned prim:4;
 271                 unsigned uses_instancing:1;
 272                 unsigned multi_instances_smaller_than_primgroup:1;
 273                 unsigned primitive_restart:1;
 274                 unsigned count_from_stream_output:1;
 275                 unsigned line_stipple_enabled:1;
 276                 unsigned uses_tess:1;
 277                 unsigned tess_uses_prim_id:1;
 278                 unsigned uses_gs:1;
 279                 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
 280         } u;
 281         uint32_t index;
 282 };
 283
 284 struct si_texture_handle
 285 {
 286         unsigned                        desc_slot;
 287         bool                            desc_dirty;
 288         struct pipe_sampler_view        *view;
 289         struct si_sampler_state         sstate;
 290 };
 291
 292 struct si_image_handle
 293 {
 294         unsigned                        desc_slot;
 295         bool                            desc_dirty;
 296         struct pipe_image_view          view;
 297 };
 298
 299 struct si_saved_cs {
 300         struct pipe_reference   reference;
 301         struct si_context       *ctx;
 302         struct radeon_saved_cs  gfx;
 303         struct r600_resource    *trace_buf;
 304         unsigned                trace_id;
 305
 306         unsigned                gfx_last_dw;
 307         bool                    flushed;
 308 };
 309
 310 struct si_context {
 311         struct r600_common_context      b;
 312         struct blitter_context          *blitter;
 313         void                            *custom_dsa_flush;
 314         void                            *custom_blend_resolve;
 315         void                            *custom_blend_fmask_decompress;
 316         void                            *custom_blend_eliminate_fastclear;
 317         void                            *custom_blend_dcc_decompress;
 318         struct si_screen                *screen;
 319         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 320         struct si_shader_ctx_state      fixed_func_tcs_shader;
 321         struct r600_resource            *wait_mem_scratch;
 322         unsigned                        wait_mem_number;
 323         uint16_t                        prefetch_L2_mask;
 324
 325         bool                            gfx_flush_in_progress:1;
 326         bool                            compute_is_busy:1;
 327
 328         /* Atoms (direct states). */
 329         union si_state_atoms            atoms;
 330         unsigned                        dirty_atoms; /* mask */
 331         /* PM4 states (precomputed immutable states) */
 332         unsigned                        dirty_states;
 333         union si_state                  queued;
 334         union si_state                  emitted;
 335
 336         /* Atom declarations. */
 337         struct si_framebuffer           framebuffer;
 338         struct si_sample_locs           msaa_sample_locs;
 339         struct r600_atom                db_render_state;
 340         struct r600_atom                dpbb_state;
 341         struct r600_atom                msaa_config;
 342         struct si_sample_mask           sample_mask;
 343         struct r600_atom                cb_render_state;
 344         unsigned                        last_cb_target_mask;
 345         struct si_blend_color           blend_color;
 346         struct r600_atom                clip_regs;
 347         struct si_clip_state            clip_state;
 348         struct si_shader_data           shader_pointers;
 349         struct si_stencil_ref           stencil_ref;
 350         struct r600_atom                spi_map;
 351         struct si_scissors              scissors;
 352         struct si_viewports             viewports;
 353
 354         /* Precomputed states. */
 355         struct si_pm4_state             *init_config;
 356         struct si_pm4_state             *init_config_gs_rings;
 357         bool                            init_config_has_vgt_flush;
 358         struct si_pm4_state             *vgt_shader_config[4];
 359
 360         /* shaders */
 361         struct si_shader_ctx_state      ps_shader;
 362         struct si_shader_ctx_state      gs_shader;
 363         struct si_shader_ctx_state      vs_shader;
 364         struct si_shader_ctx_state      tcs_shader;
 365         struct si_shader_ctx_state      tes_shader;
 366         struct si_cs_shader_state       cs_shader_state;
 367
 368         /* shader information */
 369         struct si_vertex_elements       *vertex_elements;
 370         unsigned                        sprite_coord_enable;
 371         bool                            flatshade;
 372         bool                            do_update_shaders;
 373
 374         /* shader descriptors */
 375         struct si_descriptors           vertex_buffers;
 376         struct si_descriptors           descriptors[SI_NUM_DESCS];
 377         unsigned                        descriptors_dirty;
 378         unsigned                        shader_pointers_dirty;
 379         unsigned                        shader_needs_decompress_mask;
 380         struct si_buffer_resources      rw_buffers;
 381         struct si_buffer_resources      const_and_shader_buffers[SI_NUM_SHADERS];
 382         struct si_textures_info         samplers[SI_NUM_SHADERS];
 383         struct si_images_info           images[SI_NUM_SHADERS];
 384
 385         /* other shader resources */
 386         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 387         struct pipe_resource            *esgs_ring;
 388         struct pipe_resource            *gsvs_ring;
 389         struct pipe_resource            *tf_ring;
 390         struct pipe_resource            *tess_offchip_ring;
 391         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 392         struct r600_resource            *border_color_buffer;
 393         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 394         unsigned                        border_color_count;
 395
 396         /* Vertex and index buffers. */
 397         bool                            vertex_buffers_dirty;
 398         bool                            vertex_buffer_pointer_dirty;
 399         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 400
 401         /* MSAA config state. */
 402         int                             ps_iter_samples;
 403         bool                            smoothing_enabled;
 404
 405         /* DB render state. */
 406         unsigned                ps_db_shader_control;
 407         unsigned                dbcb_copy_sample;
 408         bool                    dbcb_depth_copy_enabled:1;
 409         bool                    dbcb_stencil_copy_enabled:1;
 410         bool                    db_flush_depth_inplace:1;
 411         bool                    db_flush_stencil_inplace:1;
 412         bool                    db_depth_clear:1;
 413         bool                    db_depth_disable_expclear:1;
 414         bool                    db_stencil_clear:1;
 415         bool                    db_stencil_disable_expclear:1;
 416         bool                    occlusion_queries_disabled:1;
 417         bool                    generate_mipmap_for_depth:1;
 418
 419         /* Emitted draw state. */
 420         bool                    gs_tri_strip_adj_fix:1;
 421         bool                    ls_vgpr_fix:1;
 422         int                     last_index_size;
 423         int                     last_base_vertex;
 424         int                     last_start_instance;
 425         int                     last_drawid;
 426         int                     last_sh_base_reg;
 427         int                     last_primitive_restart_en;
 428         int                     last_restart_index;
 429         int                     last_gs_out_prim;
 430         int                     last_prim;
 431         int                     last_multi_vgt_param;
 432         int                     last_rast_prim;
 433         unsigned                last_sc_line_stipple;
 434         unsigned                current_vs_state;
 435         unsigned                last_vs_state;
 436         enum pipe_prim_type     current_rast_prim; /* primitive type after TES, GS */
 437
 438         /* Scratch buffer */
 439         struct r600_atom        scratch_state;
 440         struct r600_resource    *scratch_buffer;
 441         unsigned                scratch_waves;
 442         unsigned                spi_tmpring_size;
 443
 444         struct r600_resource    *compute_scratch_buffer;
 445
 446         /* Emitted derived tessellation state. */
 447         /* Local shader (VS), or HS if LS-HS are merged. */
 448         struct si_shader        *last_ls;
 449         struct si_shader_selector *last_tcs;
 450         int                     last_num_tcs_input_cp;
 451         int                     last_tes_sh_base;
 452         bool                    last_tess_uses_primid;
 453         unsigned                last_num_patches;
 454
 455         /* Debug state. */
 456         bool                    is_debug;
 457         struct si_saved_cs      *current_saved_cs;
 458         uint64_t                dmesg_timestamp;
 459         unsigned                apitrace_call_number;
 460
 461         /* Other state */
 462         bool need_check_render_feedback;
 463         bool                    decompression_enabled;
 464
 465         bool                    vs_writes_viewport_index;
 466         bool                    vs_disables_clipping_viewport;
 467
 468         /* Precomputed IA_MULTI_VGT_PARAM */
 469         union si_vgt_param_key  ia_multi_vgt_param_key;
 470         unsigned                ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
 471
 472         /* Bindless descriptors. */
 473         struct si_descriptors   bindless_descriptors;
 474         struct util_idalloc     bindless_used_slots;
 475         unsigned                num_bindless_descriptors;
 476         bool                    bindless_descriptors_dirty;
 477         bool                    graphics_bindless_pointer_dirty;
 478         bool                    compute_bindless_pointer_dirty;
 479
 480         /* Allocated bindless handles */
 481         struct hash_table       *tex_handles;
 482         struct hash_table       *img_handles;
 483
 484         /* Resident bindless handles */
 485         struct util_dynarray    resident_tex_handles;
 486         struct util_dynarray    resident_img_handles;
 487
 488         /* Resident bindless handles which need decompression */
 489         struct util_dynarray    resident_tex_needs_color_decompress;
 490         struct util_dynarray    resident_img_needs_color_decompress;
 491         struct util_dynarray    resident_tex_needs_depth_decompress;
 492
 493         /* Bindless state */
 494         bool                    uses_bindless_samplers;
 495         bool                    uses_bindless_images;
 496 };
 497
 498 /* cik_sdma.c */
 499 void cik_init_sdma_functions(struct si_context *sctx);
 500
 501 /* si_blit.c */
 502 void si_init_blit_functions(struct si_context *sctx);
 503 void si_decompress_graphics_textures(struct si_context *sctx);
 504 void si_decompress_compute_textures(struct si_context *sctx);
 505 void si_resource_copy_region(struct pipe_context *ctx,
 506                              struct pipe_resource *dst,
 507                              unsigned dst_level,
 508                              unsigned dstx, unsigned dsty, unsigned dstz,
 509                              struct pipe_resource *src,
 510                              unsigned src_level,
 511                              const struct pipe_box *src_box);
 512
 513 /* si_cp_dma.c */
 514 #define SI_CPDMA_SKIP_CHECK_CS_SPACE    (1 << 0) /* don't call need_cs_space */
 515 #define SI_CPDMA_SKIP_SYNC_AFTER        (1 << 1) /* don't wait for DMA after the copy */
 516 #define SI_CPDMA_SKIP_SYNC_BEFORE       (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
 517 #define SI_CPDMA_SKIP_GFX_SYNC          (1 << 3) /* don't flush caches and don't wait for PS/CS */
 518 #define SI_CPDMA_SKIP_BO_LIST_UPDATE    (1 << 4) /* don't update the BO list */
 519 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
 520                            SI_CPDMA_SKIP_SYNC_AFTER | \
 521                            SI_CPDMA_SKIP_SYNC_BEFORE | \
 522                            SI_CPDMA_SKIP_GFX_SYNC | \
 523                            SI_CPDMA_SKIP_BO_LIST_UPDATE)
 524
 525 void si_copy_buffer(struct si_context *sctx,
 526                     struct pipe_resource *dst, struct pipe_resource *src,
 527                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 528                     unsigned user_flags);
 529 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 530                               uint64_t offset, unsigned size);
 531 void cik_emit_prefetch_L2(struct si_context *sctx);
 532 void si_init_cp_dma_functions(struct si_context *sctx);
 533
 534 /* si_debug.c */
 535 void si_auto_log_cs(void *data, struct u_log_context *log);
 536 void si_log_hw_flush(struct si_context *sctx);
 537 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
 538 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
 539 void si_init_debug_functions(struct si_context *sctx);
 540 void si_check_vm_faults(struct r600_common_context *ctx,
 541                         struct radeon_saved_cs *saved, enum ring_type ring);
 542 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
 543
 544 /* si_dma.c */
 545 void si_init_dma_functions(struct si_context *sctx);
 546
 547 /* si_hw_context.c */
 548 void si_destroy_saved_cs(struct si_saved_cs *scs);
 549 void si_context_gfx_flush(void *context, unsigned flags,
 550                           struct pipe_fence_handle **fence);
 551 void si_begin_new_cs(struct si_context *ctx);
 552 void si_need_cs_space(struct si_context *ctx);
 553
 554 /* si_compute.c */
 555 void si_init_compute_functions(struct si_context *sctx);
 556
 557 /* si_perfcounters.c */
 558 void si_init_perfcounters(struct si_screen *screen);
 559
 560 /* si_uvd.c */
 561 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 562                                                const struct pipe_video_codec *templ);
 563
 564 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 565                                                  const struct pipe_video_buffer *tmpl);
 566
 567 /* si_viewport.c */
 568 void si_update_vs_writes_viewport_index(struct si_context *ctx);
 569 void si_init_viewport_functions(struct si_context *ctx);
 570
 571
 572 /*
 573  * common helpers
 574  */
 575
 576 static inline void
 577 si_invalidate_draw_sh_constants(struct si_context *sctx)
 578 {
 579         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 580 }
 581
 582 static inline void
 583 si_set_atom_dirty(struct si_context *sctx,
 584                   struct r600_atom *atom, bool dirty)
 585 {
 586         unsigned bit = 1 << atom->id;
 587
 588         if (dirty)
 589                 sctx->dirty_atoms |= bit;
 590         else
 591                 sctx->dirty_atoms &= ~bit;
 592 }
 593
 594 static inline bool
 595 si_is_atom_dirty(struct si_context *sctx,
 596                   struct r600_atom *atom)
 597 {
 598         unsigned bit = 1 << atom->id;
 599
 600         return sctx->dirty_atoms & bit;
 601 }
 602
 603 static inline void
 604 si_mark_atom_dirty(struct si_context *sctx,
 605                    struct r600_atom *atom)
 606 {
 607         si_set_atom_dirty(sctx, atom, true);
 608 }
 609
 610 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
 611 {
 612         if (sctx->gs_shader.cso)
 613                 return &sctx->gs_shader;
 614         if (sctx->tes_shader.cso)
 615                 return &sctx->tes_shader;
 616
 617         return &sctx->vs_shader;
 618 }
 619
 620 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 621 {
 622         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 623
 624         return vs->cso ? &vs->cso->info : NULL;
 625 }
 626
 627 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 628 {
 629         if (sctx->gs_shader.cso)
 630                 return sctx->gs_shader.cso->gs_copy_shader;
 631
 632         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 633         return vs->current ? vs->current : NULL;
 634 }
 635
 636 static inline unsigned
 637 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
 638 {
 639         unsigned alignment, tcc_cache_line_size;
 640
 641         /* If the upload size is less than the cache line size (e.g. 16, 32),
 642          * the whole thing will fit into a cache line if we align it to its size.
 643          * The idea is that multiple small uploads can share a cache line.
 644          * If the upload size is greater, align it to the cache line size.
 645          */
 646         alignment = util_next_power_of_two(upload_size);
 647         tcc_cache_line_size = sctx->screen->b.info.tcc_cache_line_size;
 648         return MIN2(alignment, tcc_cache_line_size);
 649 }
 650
 651 static inline void
 652 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
 653 {
 654         if (pipe_reference(&(*dst)->reference, &src->reference))
 655                 si_destroy_saved_cs(*dst);
 656
 657         *dst = src;
 658 }
 659
 660 static inline void
 661 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 662                            bool shaders_read_metadata)
 663 {
 664         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
 665                          SI_CONTEXT_INV_VMEM_L1;
 666
 667         if (sctx->b.chip_class >= GFX9) {
 668                 /* Single-sample color is coherent with shaders on GFX9, but
 669                  * L2 metadata must be flushed if shaders read metadata.
 670                  * (DCC, CMASK).
 671                  */
 672                 if (num_samples >= 2)
 673                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 674                 else if (shaders_read_metadata)
 675                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 676         } else {
 677                 /* SI-CI-VI */
 678                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 679         }
 680 }
 681
 682 static inline void
 683 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 684                            bool include_stencil, bool shaders_read_metadata)
 685 {
 686         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
 687                          SI_CONTEXT_INV_VMEM_L1;
 688
 689         if (sctx->b.chip_class >= GFX9) {
 690                 /* Single-sample depth (not stencil) is coherent with shaders
 691                  * on GFX9, but L2 metadata must be flushed if shaders read
 692                  * metadata.
 693                  */
 694                 if (num_samples >= 2 || include_stencil)
 695                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 696                 else if (shaders_read_metadata)
 697                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 698         } else {
 699                 /* SI-CI-VI */
 700                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 701         }
 702 }
 703
 704 #endif