src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef SI_PIPE_H
  27 #define SI_PIPE_H
  28
  29 #include "si_shader.h"
  30
  31 #include "util/u_dynarray.h"
  32 #include "util/u_idalloc.h"
  33
  34 #ifdef PIPE_ARCH_BIG_ENDIAN
  35 #define SI_BIG_ENDIAN 1
  36 #else
  37 #define SI_BIG_ENDIAN 0
  38 #endif
  39
  40 /* The base vertex and primitive restart can be any number, but we must pick
  41  * one which will mean "unknown" for the purpose of state tracking and
  42  * the number shouldn't be a commonly-used one. */
  43 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  44 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  45 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  46 #define SI_GS_PER_ES 128
  47 /* Alignment for optimal CP DMA performance. */
  48 #define SI_CPDMA_ALIGNMENT      32
  49
  50 /* Instruction cache. */
  51 #define SI_CONTEXT_INV_ICACHE           (R600_CONTEXT_PRIVATE_FLAG << 0)
  52 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  53 #define SI_CONTEXT_INV_SMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 1)
  54 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  55 #define SI_CONTEXT_INV_VMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 2)
  56 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  57 #define SI_CONTEXT_INV_GLOBAL_L2        (R600_CONTEXT_PRIVATE_FLAG << 3)
  58 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  59  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
  60 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2  (R600_CONTEXT_PRIVATE_FLAG << 4)
  61 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
  62  * a CB or DB flush. */
  63 #define SI_CONTEXT_INV_L2_METADATA      (R600_CONTEXT_PRIVATE_FLAG << 5)
  64 /* Framebuffer caches. */
  65 #define SI_CONTEXT_FLUSH_AND_INV_DB     (R600_CONTEXT_PRIVATE_FLAG << 6)
  66 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 7)
  67 #define SI_CONTEXT_FLUSH_AND_INV_CB     (R600_CONTEXT_PRIVATE_FLAG << 8)
  68 /* Engine synchronization. */
  69 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 9)
  70 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 10)
  71 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 11)
  72 #define SI_CONTEXT_VGT_FLUSH            (R600_CONTEXT_PRIVATE_FLAG << 12)
  73 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (R600_CONTEXT_PRIVATE_FLAG << 13)
  74
  75 #define SI_PREFETCH_VBO_DESCRIPTORS     (1 << 0)
  76 #define SI_PREFETCH_LS                  (1 << 1)
  77 #define SI_PREFETCH_HS                  (1 << 2)
  78 #define SI_PREFETCH_ES                  (1 << 3)
  79 #define SI_PREFETCH_GS                  (1 << 4)
  80 #define SI_PREFETCH_VS                  (1 << 5)
  81 #define SI_PREFETCH_PS                  (1 << 6)
  82
  83 #define SI_MAX_BORDER_COLORS    4096
  84 #define SI_MAX_VIEWPORTS        16
  85 #define SIX_BITS                0x3F
  86
  87 struct si_compute;
  88 struct hash_table;
  89 struct u_suballocator;
  90
  91 struct si_screen {
  92         struct r600_common_screen       b;
  93         unsigned                        gs_table_depth;
  94         unsigned                        tess_offchip_block_dw_size;
  95         bool                            has_clear_state;
  96         bool                            has_distributed_tess;
  97         bool                            has_draw_indirect_multi;
  98         bool                            has_out_of_order_rast;
  99         bool                            assume_no_z_fights;
 100         bool                            commutative_blend_add;
 101         bool                            clear_db_meta_before_clear;
 102         bool                            has_msaa_sample_loc_bug;
 103         bool                            dpbb_allowed;
 104         bool                            dfsm_allowed;
 105         bool                            llvm_has_working_vgpr_indexing;
 106
 107         /* Whether shaders are monolithic (1-part) or separate (3-part). */
 108         bool                            use_monolithic_shaders;
 109         bool                            record_llvm_ir;
 110
 111         mtx_t                   shader_parts_mutex;
 112         struct si_shader_part           *vs_prologs;
 113         struct si_shader_part           *tcs_epilogs;
 114         struct si_shader_part           *gs_prologs;
 115         struct si_shader_part           *ps_prologs;
 116         struct si_shader_part           *ps_epilogs;
 117
 118         /* Shader cache in memory.
 119          *
 120          * Design & limitations:
 121          * - The shader cache is per screen (= per process), never saved to
 122          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 123          * - It can only be used with one-variant-per-shader support, in which
 124          *   case only the main (typically middle) part of shaders is cached.
 125          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 126          *   variants of VS and TES are cached, so LS and ES aren't.
 127          * - GS and CS aren't cached, but it's certainly possible to cache
 128          *   those as well.
 129          */
 130         mtx_t                   shader_cache_mutex;
 131         struct hash_table               *shader_cache;
 132
 133         /* Shader compiler queue for multithreaded compilation. */
 134         struct util_queue               shader_compiler_queue;
 135         /* Use at most 3 normal compiler threads on quadcore and better.
 136          * Hyperthreaded CPUs report the number of threads, but we want
 137          * the number of cores. */
 138         LLVMTargetMachineRef            tm[3]; /* used by the queue only */
 139
 140         struct util_queue               shader_compiler_queue_low_priority;
 141         /* Use at most 2 low priority threads on quadcore and better.
 142          * We want to minimize the impact on multithreaded Mesa. */
 143         LLVMTargetMachineRef            tm_low_priority[2]; /* at most 2 threads */
 144 };
 145
 146 struct si_blend_color {
 147         struct r600_atom                atom;
 148         struct pipe_blend_color         state;
 149         bool                            any_nonzeros;
 150 };
 151
 152 struct si_sampler_view {
 153         struct pipe_sampler_view        base;
 154         /* [0..7] = image descriptor
 155          * [4..7] = buffer descriptor */
 156         uint32_t                        state[8];
 157         uint32_t                        fmask_state[8];
 158         const struct legacy_surf_level  *base_level_info;
 159         ubyte                           base_level;
 160         ubyte                           block_width;
 161         bool is_stencil_sampler;
 162         bool is_integer;
 163         bool dcc_incompatible;
 164 };
 165
 166 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
 167
 168 struct si_sampler_state {
 169 #ifdef DEBUG
 170         unsigned                        magic;
 171 #endif
 172         uint32_t                        val[4];
 173         uint32_t                        integer_val[4];
 174         uint32_t                        upgraded_depth_val[4];
 175 };
 176
 177 struct si_cs_shader_state {
 178         struct si_compute               *program;
 179         struct si_compute               *emitted_program;
 180         unsigned                        offset;
 181         bool                            initialized;
 182         bool                            uses_scratch;
 183 };
 184
 185 struct si_samplers {
 186         struct pipe_sampler_view        *views[SI_NUM_SAMPLERS];
 187         struct si_sampler_state         *sampler_states[SI_NUM_SAMPLERS];
 188
 189         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 190         unsigned                        enabled_mask;
 191         uint32_t                        needs_depth_decompress_mask;
 192         uint32_t                        needs_color_decompress_mask;
 193 };
 194
 195 struct si_images {
 196         struct pipe_image_view          views[SI_NUM_IMAGES];
 197         uint32_t                        needs_color_decompress_mask;
 198         unsigned                        enabled_mask;
 199 };
 200
 201 struct si_framebuffer {
 202         struct r600_atom                atom;
 203         struct pipe_framebuffer_state   state;
 204         unsigned                        colorbuf_enabled_4bit;
 205         unsigned                        spi_shader_col_format;
 206         unsigned                        spi_shader_col_format_alpha;
 207         unsigned                        spi_shader_col_format_blend;
 208         unsigned                        spi_shader_col_format_blend_alpha;
 209         ubyte                           nr_samples:5; /* at most 16xAA */
 210         ubyte                           log_samples:3; /* at most 4 = 16xAA */
 211         ubyte                           compressed_cb_mask;
 212         ubyte                           color_is_int8;
 213         ubyte                           color_is_int10;
 214         ubyte                           dirty_cbufs;
 215         bool                            dirty_zsbuf;
 216         bool                            any_dst_linear;
 217         bool                            CB_has_shader_readable_metadata;
 218         bool                            DB_has_shader_readable_metadata;
 219 };
 220
 221 struct si_signed_scissor {
 222         int minx;
 223         int miny;
 224         int maxx;
 225         int maxy;
 226 };
 227
 228 struct si_scissors {
 229         struct r600_atom                atom;
 230         unsigned                        dirty_mask;
 231         struct pipe_scissor_state       states[SI_MAX_VIEWPORTS];
 232 };
 233
 234 struct si_viewports {
 235         struct r600_atom                atom;
 236         unsigned                        dirty_mask;
 237         unsigned                        depth_range_dirty_mask;
 238         struct pipe_viewport_state      states[SI_MAX_VIEWPORTS];
 239         struct si_signed_scissor        as_scissor[SI_MAX_VIEWPORTS];
 240 };
 241
 242 struct si_clip_state {
 243         struct r600_atom                atom;
 244         struct pipe_clip_state          state;
 245         bool                            any_nonzeros;
 246 };
 247
 248 struct si_sample_locs {
 249         struct r600_atom        atom;
 250         unsigned                nr_samples;
 251 };
 252
 253 struct si_sample_mask {
 254         struct r600_atom        atom;
 255         uint16_t                sample_mask;
 256 };
 257
 258 /* A shader state consists of the shader selector, which is a constant state
 259  * object shared by multiple contexts and shouldn't be modified, and
 260  * the current shader variant selected for this context.
 261  */
 262 struct si_shader_ctx_state {
 263         struct si_shader_selector       *cso;
 264         struct si_shader                *current;
 265 };
 266
 267 #define SI_NUM_VGT_PARAM_KEY_BITS 12
 268 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
 269
 270 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
 271  * Some fields are set by state-change calls, most are set by draw_vbo.
 272  */
 273 union si_vgt_param_key {
 274         struct {
 275                 unsigned prim:4;
 276                 unsigned uses_instancing:1;
 277                 unsigned multi_instances_smaller_than_primgroup:1;
 278                 unsigned primitive_restart:1;
 279                 unsigned count_from_stream_output:1;
 280                 unsigned line_stipple_enabled:1;
 281                 unsigned uses_tess:1;
 282                 unsigned tess_uses_prim_id:1;
 283                 unsigned uses_gs:1;
 284                 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
 285         } u;
 286         uint32_t index;
 287 };
 288
 289 struct si_texture_handle
 290 {
 291         unsigned                        desc_slot;
 292         bool                            desc_dirty;
 293         struct pipe_sampler_view        *view;
 294         struct si_sampler_state         sstate;
 295 };
 296
 297 struct si_image_handle
 298 {
 299         unsigned                        desc_slot;
 300         bool                            desc_dirty;
 301         struct pipe_image_view          view;
 302 };
 303
 304 struct si_saved_cs {
 305         struct pipe_reference   reference;
 306         struct si_context       *ctx;
 307         struct radeon_saved_cs  gfx;
 308         struct r600_resource    *trace_buf;
 309         unsigned                trace_id;
 310
 311         unsigned                gfx_last_dw;
 312         bool                    flushed;
 313 };
 314
 315 struct si_context {
 316         struct r600_common_context      b;
 317         struct blitter_context          *blitter;
 318         void                            *custom_dsa_flush;
 319         void                            *custom_blend_resolve;
 320         void                            *custom_blend_fmask_decompress;
 321         void                            *custom_blend_eliminate_fastclear;
 322         void                            *custom_blend_dcc_decompress;
 323         void                            *vs_blit_pos;
 324         void                            *vs_blit_pos_layered;
 325         void                            *vs_blit_color;
 326         void                            *vs_blit_color_layered;
 327         void                            *vs_blit_texcoord;
 328         struct si_screen                *screen;
 329         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 330         struct si_shader_ctx_state      fixed_func_tcs_shader;
 331         struct r600_resource            *wait_mem_scratch;
 332         unsigned                        wait_mem_number;
 333         uint16_t                        prefetch_L2_mask;
 334
 335         bool                            gfx_flush_in_progress:1;
 336         bool                            compute_is_busy:1;
 337
 338         /* Atoms (direct states). */
 339         union si_state_atoms            atoms;
 340         unsigned                        dirty_atoms; /* mask */
 341         /* PM4 states (precomputed immutable states) */
 342         unsigned                        dirty_states;
 343         union si_state                  queued;
 344         union si_state                  emitted;
 345
 346         /* Atom declarations. */
 347         struct si_framebuffer           framebuffer;
 348         struct si_sample_locs           msaa_sample_locs;
 349         struct r600_atom                db_render_state;
 350         struct r600_atom                dpbb_state;
 351         struct r600_atom                msaa_config;
 352         struct si_sample_mask           sample_mask;
 353         struct r600_atom                cb_render_state;
 354         unsigned                        last_cb_target_mask;
 355         struct si_blend_color           blend_color;
 356         struct r600_atom                clip_regs;
 357         struct si_clip_state            clip_state;
 358         struct si_shader_data           shader_pointers;
 359         struct si_stencil_ref           stencil_ref;
 360         struct r600_atom                spi_map;
 361         struct si_scissors              scissors;
 362         struct si_viewports             viewports;
 363
 364         /* Precomputed states. */
 365         struct si_pm4_state             *init_config;
 366         struct si_pm4_state             *init_config_gs_rings;
 367         bool                            init_config_has_vgt_flush;
 368         struct si_pm4_state             *vgt_shader_config[4];
 369
 370         /* shaders */
 371         struct si_shader_ctx_state      ps_shader;
 372         struct si_shader_ctx_state      gs_shader;
 373         struct si_shader_ctx_state      vs_shader;
 374         struct si_shader_ctx_state      tcs_shader;
 375         struct si_shader_ctx_state      tes_shader;
 376         struct si_cs_shader_state       cs_shader_state;
 377
 378         /* shader information */
 379         struct si_vertex_elements       *vertex_elements;
 380         unsigned                        sprite_coord_enable;
 381         bool                            flatshade;
 382         bool                            do_update_shaders;
 383
 384         /* shader descriptors */
 385         struct si_descriptors           vertex_buffers;
 386         struct si_descriptors           descriptors[SI_NUM_DESCS];
 387         unsigned                        descriptors_dirty;
 388         unsigned                        shader_pointers_dirty;
 389         unsigned                        shader_needs_decompress_mask;
 390         struct si_buffer_resources      rw_buffers;
 391         struct si_buffer_resources      const_and_shader_buffers[SI_NUM_SHADERS];
 392         struct si_samplers              samplers[SI_NUM_SHADERS];
 393         struct si_images                images[SI_NUM_SHADERS];
 394
 395         /* other shader resources */
 396         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 397         struct pipe_resource            *esgs_ring;
 398         struct pipe_resource            *gsvs_ring;
 399         struct pipe_resource            *tf_ring;
 400         struct pipe_resource            *tess_offchip_ring;
 401         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 402         struct r600_resource            *border_color_buffer;
 403         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 404         unsigned                        border_color_count;
 405         unsigned                        num_vs_blit_sgprs;
 406         uint32_t                        vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
 407
 408         /* Vertex and index buffers. */
 409         bool                            vertex_buffers_dirty;
 410         bool                            vertex_buffer_pointer_dirty;
 411         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 412
 413         /* MSAA config state. */
 414         int                             ps_iter_samples;
 415         bool                            smoothing_enabled;
 416
 417         /* DB render state. */
 418         unsigned                ps_db_shader_control;
 419         unsigned                dbcb_copy_sample;
 420         bool                    dbcb_depth_copy_enabled:1;
 421         bool                    dbcb_stencil_copy_enabled:1;
 422         bool                    db_flush_depth_inplace:1;
 423         bool                    db_flush_stencil_inplace:1;
 424         bool                    db_depth_clear:1;
 425         bool                    db_depth_disable_expclear:1;
 426         bool                    db_stencil_clear:1;
 427         bool                    db_stencil_disable_expclear:1;
 428         bool                    occlusion_queries_disabled:1;
 429         bool                    generate_mipmap_for_depth:1;
 430
 431         /* Emitted draw state. */
 432         bool                    gs_tri_strip_adj_fix:1;
 433         bool                    ls_vgpr_fix:1;
 434         int                     last_index_size;
 435         int                     last_base_vertex;
 436         int                     last_start_instance;
 437         int                     last_drawid;
 438         int                     last_sh_base_reg;
 439         int                     last_primitive_restart_en;
 440         int                     last_restart_index;
 441         int                     last_gs_out_prim;
 442         int                     last_prim;
 443         int                     last_multi_vgt_param;
 444         int                     last_rast_prim;
 445         unsigned                last_sc_line_stipple;
 446         unsigned                current_vs_state;
 447         unsigned                last_vs_state;
 448         enum pipe_prim_type     current_rast_prim; /* primitive type after TES, GS */
 449
 450         /* Scratch buffer */
 451         struct r600_atom        scratch_state;
 452         struct r600_resource    *scratch_buffer;
 453         unsigned                scratch_waves;
 454         unsigned                spi_tmpring_size;
 455
 456         struct r600_resource    *compute_scratch_buffer;
 457
 458         /* Emitted derived tessellation state. */
 459         /* Local shader (VS), or HS if LS-HS are merged. */
 460         struct si_shader        *last_ls;
 461         struct si_shader_selector *last_tcs;
 462         int                     last_num_tcs_input_cp;
 463         int                     last_tes_sh_base;
 464         bool                    last_tess_uses_primid;
 465         unsigned                last_num_patches;
 466
 467         /* Debug state. */
 468         bool                    is_debug;
 469         struct si_saved_cs      *current_saved_cs;
 470         uint64_t                dmesg_timestamp;
 471         unsigned                apitrace_call_number;
 472
 473         /* Other state */
 474         bool need_check_render_feedback;
 475         bool                    decompression_enabled;
 476
 477         bool                    vs_writes_viewport_index;
 478         bool                    vs_disables_clipping_viewport;
 479
 480         /* Precomputed IA_MULTI_VGT_PARAM */
 481         union si_vgt_param_key  ia_multi_vgt_param_key;
 482         unsigned                ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
 483
 484         /* Bindless descriptors. */
 485         struct si_descriptors   bindless_descriptors;
 486         struct util_idalloc     bindless_used_slots;
 487         unsigned                num_bindless_descriptors;
 488         bool                    bindless_descriptors_dirty;
 489         bool                    graphics_bindless_pointer_dirty;
 490         bool                    compute_bindless_pointer_dirty;
 491
 492         /* Allocated bindless handles */
 493         struct hash_table       *tex_handles;
 494         struct hash_table       *img_handles;
 495
 496         /* Resident bindless handles */
 497         struct util_dynarray    resident_tex_handles;
 498         struct util_dynarray    resident_img_handles;
 499
 500         /* Resident bindless handles which need decompression */
 501         struct util_dynarray    resident_tex_needs_color_decompress;
 502         struct util_dynarray    resident_img_needs_color_decompress;
 503         struct util_dynarray    resident_tex_needs_depth_decompress;
 504
 505         /* Bindless state */
 506         bool                    uses_bindless_samplers;
 507         bool                    uses_bindless_images;
 508 };
 509
 510 /* cik_sdma.c */
 511 void cik_init_sdma_functions(struct si_context *sctx);
 512
 513 /* si_blit.c */
 514 void si_init_blit_functions(struct si_context *sctx);
 515 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
 516 void si_resource_copy_region(struct pipe_context *ctx,
 517                              struct pipe_resource *dst,
 518                              unsigned dst_level,
 519                              unsigned dstx, unsigned dsty, unsigned dstz,
 520                              struct pipe_resource *src,
 521                              unsigned src_level,
 522                              const struct pipe_box *src_box);
 523
 524 /* si_cp_dma.c */
 525 #define SI_CPDMA_SKIP_CHECK_CS_SPACE    (1 << 0) /* don't call need_cs_space */
 526 #define SI_CPDMA_SKIP_SYNC_AFTER        (1 << 1) /* don't wait for DMA after the copy */
 527 #define SI_CPDMA_SKIP_SYNC_BEFORE       (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
 528 #define SI_CPDMA_SKIP_GFX_SYNC          (1 << 3) /* don't flush caches and don't wait for PS/CS */
 529 #define SI_CPDMA_SKIP_BO_LIST_UPDATE    (1 << 4) /* don't update the BO list */
 530 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
 531                            SI_CPDMA_SKIP_SYNC_AFTER | \
 532                            SI_CPDMA_SKIP_SYNC_BEFORE | \
 533                            SI_CPDMA_SKIP_GFX_SYNC | \
 534                            SI_CPDMA_SKIP_BO_LIST_UPDATE)
 535
 536 void si_copy_buffer(struct si_context *sctx,
 537                     struct pipe_resource *dst, struct pipe_resource *src,
 538                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 539                     unsigned user_flags);
 540 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 541                               uint64_t offset, unsigned size);
 542 void cik_emit_prefetch_L2(struct si_context *sctx);
 543 void si_init_cp_dma_functions(struct si_context *sctx);
 544
 545 /* si_debug.c */
 546 void si_auto_log_cs(void *data, struct u_log_context *log);
 547 void si_log_hw_flush(struct si_context *sctx);
 548 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
 549 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
 550 void si_init_debug_functions(struct si_context *sctx);
 551 void si_check_vm_faults(struct r600_common_context *ctx,
 552                         struct radeon_saved_cs *saved, enum ring_type ring);
 553 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
 554
 555 /* si_dma.c */
 556 void si_init_dma_functions(struct si_context *sctx);
 557
 558 /* si_hw_context.c */
 559 void si_destroy_saved_cs(struct si_saved_cs *scs);
 560 void si_context_gfx_flush(void *context, unsigned flags,
 561                           struct pipe_fence_handle **fence);
 562 void si_begin_new_cs(struct si_context *ctx);
 563 void si_need_cs_space(struct si_context *ctx);
 564
 565 /* si_compute.c */
 566 void si_init_compute_functions(struct si_context *sctx);
 567
 568 /* si_perfcounters.c */
 569 void si_init_perfcounters(struct si_screen *screen);
 570
 571 /* si_uvd.c */
 572 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 573                                                const struct pipe_video_codec *templ);
 574
 575 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 576                                                  const struct pipe_video_buffer *tmpl);
 577
 578 /* si_viewport.c */
 579 void si_update_vs_writes_viewport_index(struct si_context *ctx);
 580 void si_init_viewport_functions(struct si_context *ctx);
 581
 582
 583 /*
 584  * common helpers
 585  */
 586
 587 static inline void
 588 si_invalidate_draw_sh_constants(struct si_context *sctx)
 589 {
 590         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 591 }
 592
 593 static inline void
 594 si_set_atom_dirty(struct si_context *sctx,
 595                   struct r600_atom *atom, bool dirty)
 596 {
 597         unsigned bit = 1 << atom->id;
 598
 599         if (dirty)
 600                 sctx->dirty_atoms |= bit;
 601         else
 602                 sctx->dirty_atoms &= ~bit;
 603 }
 604
 605 static inline bool
 606 si_is_atom_dirty(struct si_context *sctx,
 607                   struct r600_atom *atom)
 608 {
 609         unsigned bit = 1 << atom->id;
 610
 611         return sctx->dirty_atoms & bit;
 612 }
 613
 614 static inline void
 615 si_mark_atom_dirty(struct si_context *sctx,
 616                    struct r600_atom *atom)
 617 {
 618         si_set_atom_dirty(sctx, atom, true);
 619 }
 620
 621 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
 622 {
 623         if (sctx->gs_shader.cso)
 624                 return &sctx->gs_shader;
 625         if (sctx->tes_shader.cso)
 626                 return &sctx->tes_shader;
 627
 628         return &sctx->vs_shader;
 629 }
 630
 631 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 632 {
 633         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 634
 635         return vs->cso ? &vs->cso->info : NULL;
 636 }
 637
 638 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 639 {
 640         if (sctx->gs_shader.cso)
 641                 return sctx->gs_shader.cso->gs_copy_shader;
 642
 643         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 644         return vs->current ? vs->current : NULL;
 645 }
 646
 647 static inline unsigned
 648 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
 649 {
 650         unsigned alignment, tcc_cache_line_size;
 651
 652         /* If the upload size is less than the cache line size (e.g. 16, 32),
 653          * the whole thing will fit into a cache line if we align it to its size.
 654          * The idea is that multiple small uploads can share a cache line.
 655          * If the upload size is greater, align it to the cache line size.
 656          */
 657         alignment = util_next_power_of_two(upload_size);
 658         tcc_cache_line_size = sctx->screen->b.info.tcc_cache_line_size;
 659         return MIN2(alignment, tcc_cache_line_size);
 660 }
 661
 662 static inline void
 663 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
 664 {
 665         if (pipe_reference(&(*dst)->reference, &src->reference))
 666                 si_destroy_saved_cs(*dst);
 667
 668         *dst = src;
 669 }
 670
 671 static inline void
 672 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 673                            bool shaders_read_metadata)
 674 {
 675         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
 676                          SI_CONTEXT_INV_VMEM_L1;
 677
 678         if (sctx->b.chip_class >= GFX9) {
 679                 /* Single-sample color is coherent with shaders on GFX9, but
 680                  * L2 metadata must be flushed if shaders read metadata.
 681                  * (DCC, CMASK).
 682                  */
 683                 if (num_samples >= 2)
 684                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 685                 else if (shaders_read_metadata)
 686                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 687         } else {
 688                 /* SI-CI-VI */
 689                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 690         }
 691 }
 692
 693 static inline void
 694 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 695                            bool include_stencil, bool shaders_read_metadata)
 696 {
 697         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
 698                          SI_CONTEXT_INV_VMEM_L1;
 699
 700         if (sctx->b.chip_class >= GFX9) {
 701                 /* Single-sample depth (not stencil) is coherent with shaders
 702                  * on GFX9, but L2 metadata must be flushed if shaders read
 703                  * metadata.
 704                  */
 705                 if (num_samples >= 2 || include_stencil)
 706                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 707                 else if (shaders_read_metadata)
 708                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 709         } else {
 710                 /* SI-CI-VI */
 711                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 712         }
 713 }
 714
 715 #endif