src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef SI_PIPE_H
  27 #define SI_PIPE_H
  28
  29 #include "si_shader.h"
  30
  31 #ifdef PIPE_ARCH_BIG_ENDIAN
  32 #define SI_BIG_ENDIAN 1
  33 #else
  34 #define SI_BIG_ENDIAN 0
  35 #endif
  36
  37 /* The base vertex and primitive restart can be any number, but we must pick
  38  * one which will mean "unknown" for the purpose of state tracking and
  39  * the number shouldn't be a commonly-used one. */
  40 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  41 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  42 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  43 #define SI_GS_PER_ES 128
  44 /* Alignment for optimal CP DMA performance. */
  45 #define SI_CPDMA_ALIGNMENT      32
  46
  47 /* Instruction cache. */
  48 #define SI_CONTEXT_INV_ICACHE           (R600_CONTEXT_PRIVATE_FLAG << 0)
  49 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  50 #define SI_CONTEXT_INV_SMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 1)
  51 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  52 #define SI_CONTEXT_INV_VMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 2)
  53 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  54 #define SI_CONTEXT_INV_GLOBAL_L2        (R600_CONTEXT_PRIVATE_FLAG << 3)
  55 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  56  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
  57 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2  (R600_CONTEXT_PRIVATE_FLAG << 4)
  58 /* gaps */
  59 /* Framebuffer caches. */
  60 #define SI_CONTEXT_FLUSH_AND_INV_DB     (R600_CONTEXT_PRIVATE_FLAG << 7)
  61 #define SI_CONTEXT_FLUSH_AND_INV_CB     (R600_CONTEXT_PRIVATE_FLAG << 8)
  62 /* Engine synchronization. */
  63 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 9)
  64 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 10)
  65 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 11)
  66 #define SI_CONTEXT_VGT_FLUSH            (R600_CONTEXT_PRIVATE_FLAG << 12)
  67 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (R600_CONTEXT_PRIVATE_FLAG << 13)
  68
  69 #define SI_MAX_BORDER_COLORS    4096
  70
  71 struct si_compute;
  72 struct hash_table;
  73 struct u_suballocator;
  74
  75 struct si_screen {
  76         struct r600_common_screen       b;
  77         unsigned                        gs_table_depth;
  78         unsigned                        tess_offchip_block_dw_size;
  79         bool                            has_distributed_tess;
  80         bool                            has_draw_indirect_multi;
  81         bool                            has_ds_bpermute;
  82         bool                            has_msaa_sample_loc_bug;
  83
  84         /* Whether shaders are monolithic (1-part) or separate (3-part). */
  85         bool                            use_monolithic_shaders;
  86         bool                            record_llvm_ir;
  87
  88         mtx_t                   shader_parts_mutex;
  89         struct si_shader_part           *vs_prologs;
  90         struct si_shader_part           *vs_epilogs;
  91         struct si_shader_part           *tcs_epilogs;
  92         struct si_shader_part           *gs_prologs;
  93         struct si_shader_part           *ps_prologs;
  94         struct si_shader_part           *ps_epilogs;
  95
  96         /* Shader cache in memory.
  97          *
  98          * Design & limitations:
  99          * - The shader cache is per screen (= per process), never saved to
 100          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 101          * - It can only be used with one-variant-per-shader support, in which
 102          *   case only the main (typically middle) part of shaders is cached.
 103          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 104          *   variants of VS and TES are cached, so LS and ES aren't.
 105          * - GS and CS aren't cached, but it's certainly possible to cache
 106          *   those as well.
 107          */
 108         mtx_t                   shader_cache_mutex;
 109         struct hash_table               *shader_cache;
 110
 111         /* Shader compiler queue for multithreaded compilation. */
 112         struct util_queue               shader_compiler_queue;
 113         LLVMTargetMachineRef            tm[4]; /* used by the queue only */
 114 };
 115
 116 struct si_blend_color {
 117         struct r600_atom                atom;
 118         struct pipe_blend_color         state;
 119 };
 120
 121 struct si_sampler_view {
 122         struct pipe_sampler_view        base;
 123         /* [0..7] = image descriptor
 124          * [4..7] = buffer descriptor */
 125         uint32_t                        state[8];
 126         uint32_t                        fmask_state[8];
 127         const struct legacy_surf_level  *base_level_info;
 128         unsigned                        base_level;
 129         unsigned                        block_width;
 130         bool is_stencil_sampler;
 131         bool dcc_incompatible;
 132 };
 133
 134 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
 135
 136 struct si_sampler_state {
 137 #ifdef DEBUG
 138         unsigned                        magic;
 139 #endif
 140         uint32_t                        val[4];
 141 };
 142
 143 struct si_cs_shader_state {
 144         struct si_compute               *program;
 145         struct si_compute               *emitted_program;
 146         unsigned                        offset;
 147         bool                            initialized;
 148         bool                            uses_scratch;
 149 };
 150
 151 struct si_textures_info {
 152         struct si_sampler_views         views;
 153         uint32_t                        depth_texture_mask; /* which textures are depth */
 154         uint32_t                        compressed_colortex_mask;
 155 };
 156
 157 struct si_images_info {
 158         struct pipe_image_view          views[SI_NUM_IMAGES];
 159         uint32_t                        compressed_colortex_mask;
 160         unsigned                        enabled_mask;
 161 };
 162
 163 struct si_framebuffer {
 164         struct r600_atom                atom;
 165         struct pipe_framebuffer_state   state;
 166         unsigned                        nr_samples;
 167         unsigned                        log_samples;
 168         unsigned                        compressed_cb_mask;
 169         unsigned                        colorbuf_enabled_4bit;
 170         unsigned                        spi_shader_col_format;
 171         unsigned                        spi_shader_col_format_alpha;
 172         unsigned                        spi_shader_col_format_blend;
 173         unsigned                        spi_shader_col_format_blend_alpha;
 174         unsigned                        color_is_int8;
 175         unsigned                        color_is_int10;
 176         unsigned                        dirty_cbufs;
 177         bool                            dirty_zsbuf;
 178         bool                            any_dst_linear;
 179         bool                            do_update_surf_dirtiness;
 180 };
 181
 182 struct si_clip_state {
 183         struct r600_atom                atom;
 184         struct pipe_clip_state          state;
 185 };
 186
 187 struct si_sample_locs {
 188         struct r600_atom        atom;
 189         unsigned                nr_samples;
 190 };
 191
 192 struct si_sample_mask {
 193         struct r600_atom        atom;
 194         uint16_t                sample_mask;
 195 };
 196
 197 /* A shader state consists of the shader selector, which is a constant state
 198  * object shared by multiple contexts and shouldn't be modified, and
 199  * the current shader variant selected for this context.
 200  */
 201 struct si_shader_ctx_state {
 202         struct si_shader_selector       *cso;
 203         struct si_shader                *current;
 204 };
 205
 206 #define SI_NUM_VGT_PARAM_KEY_BITS 12
 207 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
 208
 209 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
 210  * Some fields are set by state-change calls, most are set by draw_vbo.
 211  */
 212 union si_vgt_param_key {
 213         struct {
 214                 unsigned prim:4;
 215                 unsigned uses_instancing:1;
 216                 unsigned multi_instances_smaller_than_primgroup:1;
 217                 unsigned primitive_restart:1;
 218                 unsigned count_from_stream_output:1;
 219                 unsigned line_stipple_enabled:1;
 220                 unsigned uses_tess:1;
 221                 unsigned tcs_tes_uses_prim_id:1;
 222                 unsigned uses_gs:1;
 223                 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
 224         } u;
 225         uint32_t index;
 226 };
 227
 228 struct si_context {
 229         struct r600_common_context      b;
 230         struct blitter_context          *blitter;
 231         void                            *custom_dsa_flush;
 232         void                            *custom_blend_resolve;
 233         void                            *custom_blend_decompress;
 234         void                            *custom_blend_fastclear;
 235         void                            *custom_blend_dcc_decompress;
 236         struct si_screen                *screen;
 237
 238         struct radeon_winsys_cs         *ce_ib;
 239         struct radeon_winsys_cs         *ce_preamble_ib;
 240         bool                            ce_need_synchronization;
 241         struct u_suballocator           *ce_suballocator;
 242
 243         struct si_shader_ctx_state      fixed_func_tcs_shader;
 244         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 245         bool                            gfx_flush_in_progress;
 246         bool                            compute_is_busy;
 247
 248         /* Atoms (direct states). */
 249         union si_state_atoms            atoms;
 250         unsigned                        dirty_atoms; /* mask */
 251         /* PM4 states (precomputed immutable states) */
 252         unsigned                        dirty_states;
 253         union si_state                  queued;
 254         union si_state                  emitted;
 255
 256         /* Atom declarations. */
 257         struct r600_atom                prefetch_L2;
 258         struct si_framebuffer           framebuffer;
 259         struct si_sample_locs           msaa_sample_locs;
 260         struct r600_atom                db_render_state;
 261         struct r600_atom                msaa_config;
 262         struct si_sample_mask           sample_mask;
 263         struct r600_atom                cb_render_state;
 264         unsigned                        last_cb_target_mask;
 265         struct si_blend_color           blend_color;
 266         struct r600_atom                clip_regs;
 267         struct si_clip_state            clip_state;
 268         struct si_shader_data           shader_userdata;
 269         struct si_stencil_ref           stencil_ref;
 270         struct r600_atom                spi_map;
 271
 272         /* Precomputed states. */
 273         struct si_pm4_state             *init_config;
 274         struct si_pm4_state             *init_config_gs_rings;
 275         bool                            init_config_has_vgt_flush;
 276         struct si_pm4_state             *vgt_shader_config[4];
 277
 278         /* shaders */
 279         struct si_shader_ctx_state      ps_shader;
 280         struct si_shader_ctx_state      gs_shader;
 281         struct si_shader_ctx_state      vs_shader;
 282         struct si_shader_ctx_state      tcs_shader;
 283         struct si_shader_ctx_state      tes_shader;
 284         struct si_cs_shader_state       cs_shader_state;
 285
 286         /* shader information */
 287         struct si_vertex_element        *vertex_elements;
 288         unsigned                        sprite_coord_enable;
 289         bool                            flatshade;
 290         bool                            do_update_shaders;
 291
 292         /* shader descriptors */
 293         struct si_descriptors           vertex_buffers;
 294         struct si_descriptors           descriptors[SI_NUM_DESCS];
 295         unsigned                        descriptors_dirty;
 296         unsigned                        shader_pointers_dirty;
 297         unsigned                        compressed_tex_shader_mask;
 298         struct si_buffer_resources      rw_buffers;
 299         struct si_buffer_resources      const_buffers[SI_NUM_SHADERS];
 300         struct si_buffer_resources      shader_buffers[SI_NUM_SHADERS];
 301         struct si_textures_info         samplers[SI_NUM_SHADERS];
 302         struct si_images_info           images[SI_NUM_SHADERS];
 303
 304         /* other shader resources */
 305         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 306         struct pipe_resource            *esgs_ring;
 307         struct pipe_resource            *gsvs_ring;
 308         struct pipe_resource            *tf_ring;
 309         struct pipe_resource            *tess_offchip_ring;
 310         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 311         struct r600_resource            *border_color_buffer;
 312         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 313         unsigned                        border_color_count;
 314
 315         /* Vertex and index buffers. */
 316         bool                            vertex_buffers_dirty;
 317         bool                            vertex_buffer_pointer_dirty;
 318         struct pipe_index_buffer        index_buffer;
 319         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 320
 321         /* MSAA config state. */
 322         int                             ps_iter_samples;
 323         bool                            smoothing_enabled;
 324
 325         /* DB render state. */
 326         bool                    dbcb_depth_copy_enabled;
 327         bool                    dbcb_stencil_copy_enabled;
 328         unsigned                dbcb_copy_sample;
 329         bool                    db_flush_depth_inplace;
 330         bool                    db_flush_stencil_inplace;
 331         bool                    db_depth_clear;
 332         bool                    db_depth_disable_expclear;
 333         bool                    db_stencil_clear;
 334         bool                    db_stencil_disable_expclear;
 335         unsigned                ps_db_shader_control;
 336         bool                    occlusion_queries_disabled;
 337
 338         /* Emitted draw state. */
 339         int                     last_index_size;
 340         int                     last_base_vertex;
 341         int                     last_start_instance;
 342         int                     last_drawid;
 343         int                     last_sh_base_reg;
 344         int                     last_primitive_restart_en;
 345         int                     last_restart_index;
 346         int                     last_gs_out_prim;
 347         int                     last_prim;
 348         int                     last_multi_vgt_param;
 349         int                     last_rast_prim;
 350         unsigned                last_sc_line_stipple;
 351         int                     current_rast_prim; /* primitive type after TES, GS */
 352         bool                    gs_tri_strip_adj_fix;
 353
 354         /* Scratch buffer */
 355         struct r600_atom        scratch_state;
 356         struct r600_resource    *scratch_buffer;
 357         unsigned                scratch_waves;
 358         unsigned                spi_tmpring_size;
 359
 360         struct r600_resource    *compute_scratch_buffer;
 361
 362         /* Emitted derived tessellation state. */
 363         struct si_shader        *last_ls; /* local shader (VS) */
 364         struct si_shader_selector *last_tcs;
 365         int                     last_num_tcs_input_cp;
 366         int                     last_tes_sh_base;
 367         unsigned                last_num_patches;
 368
 369         /* Debug state. */
 370         bool                    is_debug;
 371         struct radeon_saved_cs  last_gfx;
 372         struct r600_resource    *last_trace_buf;
 373         struct r600_resource    *trace_buf;
 374         unsigned                trace_id;
 375         uint64_t                dmesg_timestamp;
 376         unsigned                apitrace_call_number;
 377
 378         /* Other state */
 379         bool need_check_render_feedback;
 380
 381         /* Precomputed IA_MULTI_VGT_PARAM */
 382         union si_vgt_param_key  ia_multi_vgt_param_key;
 383         unsigned                ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
 384 };
 385
 386 /* cik_sdma.c */
 387 void cik_init_sdma_functions(struct si_context *sctx);
 388
 389 /* si_blit.c */
 390 void si_init_blit_functions(struct si_context *sctx);
 391 void si_decompress_graphics_textures(struct si_context *sctx);
 392 void si_decompress_compute_textures(struct si_context *sctx);
 393 void si_resource_copy_region(struct pipe_context *ctx,
 394                              struct pipe_resource *dst,
 395                              unsigned dst_level,
 396                              unsigned dstx, unsigned dsty, unsigned dstz,
 397                              struct pipe_resource *src,
 398                              unsigned src_level,
 399                              const struct pipe_box *src_box);
 400
 401 /* si_cp_dma.c */
 402 #define SI_CPDMA_SKIP_CHECK_CS_SPACE    (1 << 0) /* don't call need_cs_space */
 403 #define SI_CPDMA_SKIP_SYNC_AFTER        (1 << 1) /* don't wait for DMA after the copy */
 404 #define SI_CPDMA_SKIP_SYNC_BEFORE       (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
 405 #define SI_CPDMA_SKIP_GFX_SYNC          (1 << 3) /* don't flush caches and don't wait for PS/CS */
 406 #define SI_CPDMA_SKIP_BO_LIST_UPDATE    (1 << 4) /* don't update the BO list */
 407 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
 408                            SI_CPDMA_SKIP_SYNC_AFTER | \
 409                            SI_CPDMA_SKIP_SYNC_BEFORE | \
 410                            SI_CPDMA_SKIP_GFX_SYNC | \
 411                            SI_CPDMA_SKIP_BO_LIST_UPDATE)
 412
 413 void si_copy_buffer(struct si_context *sctx,
 414                     struct pipe_resource *dst, struct pipe_resource *src,
 415                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 416                     unsigned user_flags);
 417 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 418                               uint64_t offset, unsigned size);
 419 void si_init_cp_dma_functions(struct si_context *sctx);
 420
 421 /* si_debug.c */
 422 void si_init_debug_functions(struct si_context *sctx);
 423 void si_check_vm_faults(struct r600_common_context *ctx,
 424                         struct radeon_saved_cs *saved, enum ring_type ring);
 425 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
 426
 427 /* si_dma.c */
 428 void si_init_dma_functions(struct si_context *sctx);
 429
 430 /* si_hw_context.c */
 431 void si_context_gfx_flush(void *context, unsigned flags,
 432                           struct pipe_fence_handle **fence);
 433 void si_begin_new_cs(struct si_context *ctx);
 434 void si_need_cs_space(struct si_context *ctx);
 435
 436 /* si_compute.c */
 437 void si_init_compute_functions(struct si_context *sctx);
 438
 439 /* si_perfcounters.c */
 440 void si_init_perfcounters(struct si_screen *screen);
 441
 442 /* si_uvd.c */
 443 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 444                                                const struct pipe_video_codec *templ);
 445
 446 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 447                                                  const struct pipe_video_buffer *tmpl);
 448
 449 /*
 450  * common helpers
 451  */
 452
 453 static inline void
 454 si_invalidate_draw_sh_constants(struct si_context *sctx)
 455 {
 456         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 457 }
 458
 459 static inline void
 460 si_set_atom_dirty(struct si_context *sctx,
 461                   struct r600_atom *atom, bool dirty)
 462 {
 463         unsigned bit = 1 << atom->id;
 464
 465         if (dirty)
 466                 sctx->dirty_atoms |= bit;
 467         else
 468                 sctx->dirty_atoms &= ~bit;
 469 }
 470
 471 static inline bool
 472 si_is_atom_dirty(struct si_context *sctx,
 473                   struct r600_atom *atom)
 474 {
 475         unsigned bit = 1 << atom->id;
 476
 477         return sctx->dirty_atoms & bit;
 478 }
 479
 480 static inline void
 481 si_mark_atom_dirty(struct si_context *sctx,
 482                    struct r600_atom *atom)
 483 {
 484         si_set_atom_dirty(sctx, atom, true);
 485 }
 486
 487 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 488 {
 489         if (sctx->gs_shader.cso)
 490                 return &sctx->gs_shader.cso->info;
 491         else if (sctx->tes_shader.cso)
 492                 return &sctx->tes_shader.cso->info;
 493         else if (sctx->vs_shader.cso)
 494                 return &sctx->vs_shader.cso->info;
 495         else
 496                 return NULL;
 497 }
 498
 499 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 500 {
 501         if (sctx->gs_shader.current)
 502                 return sctx->gs_shader.cso->gs_copy_shader;
 503         else if (sctx->tes_shader.current)
 504                 return sctx->tes_shader.current;
 505         else
 506                 return sctx->vs_shader.current;
 507 }
 508
 509 static inline bool si_vs_exports_prim_id(struct si_shader *shader)
 510 {
 511         if (shader->selector->type == PIPE_SHADER_VERTEX)
 512                 return shader->key.part.vs.epilog.export_prim_id;
 513         else if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
 514                 return shader->key.part.tes.epilog.export_prim_id;
 515         else
 516                 return false;
 517 }
 518
 519 static inline unsigned
 520 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
 521 {
 522         unsigned alignment, tcc_cache_line_size;
 523
 524         /* If the upload size is less than the cache line size (e.g. 16, 32),
 525          * the whole thing will fit into a cache line if we align it to its size.
 526          * The idea is that multiple small uploads can share a cache line.
 527          * If the upload size is greater, align it to the cache line size.
 528          */
 529         alignment = util_next_power_of_two(upload_size);
 530         tcc_cache_line_size = sctx->screen->b.info.tcc_cache_line_size;
 531         return MIN2(alignment, tcc_cache_line_size);
 532 }
 533
 534 #endif