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radeonsi: add si_debug_options for convenient adding/removing of options
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
34
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
37 #else
38 #define SI_BIG_ENDIAN 0
39 #endif
40
41 #define ATI_VENDOR_ID 0x1002
42
43 #define SI_NOT_QUERY 0xffffffff
44
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
56
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
61
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
69 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
70 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
71 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
72 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
73 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
74 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
75 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
76 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
77 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
78 * a CB or DB flush. */
79 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
80 /* Framebuffer caches. */
81 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
82 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
83 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
84 /* Engine synchronization. */
85 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
86 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
87 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
88 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
89 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
90
91 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
92 #define SI_PREFETCH_LS (1 << 1)
93 #define SI_PREFETCH_HS (1 << 2)
94 #define SI_PREFETCH_ES (1 << 3)
95 #define SI_PREFETCH_GS (1 << 4)
96 #define SI_PREFETCH_VS (1 << 5)
97 #define SI_PREFETCH_PS (1 << 6)
98
99 #define SI_MAX_BORDER_COLORS 4096
100 #define SI_MAX_VIEWPORTS 16
101 #define SIX_BITS 0x3F
102 #define SI_MAP_BUFFER_ALIGNMENT 64
103 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
104
105 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
106 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
107 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
108 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
109 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
110 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
111 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
112 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
113 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
114 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
115
116 enum si_clear_code
117 {
118 DCC_CLEAR_COLOR_0000 = 0x00000000,
119 DCC_CLEAR_COLOR_0001 = 0x40404040,
120 DCC_CLEAR_COLOR_1110 = 0x80808080,
121 DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
122 DCC_CLEAR_COLOR_REG = 0x20202020,
123 DCC_UNCOMPRESSED = 0xFFFFFFFF,
124 };
125
126 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
127
128 /* Debug flags. */
129 enum {
130 /* Shader logging options: */
131 DBG_VS = PIPE_SHADER_VERTEX,
132 DBG_PS = PIPE_SHADER_FRAGMENT,
133 DBG_GS = PIPE_SHADER_GEOMETRY,
134 DBG_TCS = PIPE_SHADER_TESS_CTRL,
135 DBG_TES = PIPE_SHADER_TESS_EVAL,
136 DBG_CS = PIPE_SHADER_COMPUTE,
137 DBG_NO_IR,
138 DBG_NO_TGSI,
139 DBG_NO_ASM,
140 DBG_PREOPT_IR,
141
142 /* Shader compiler options the shader cache should be aware of: */
143 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
144 DBG_UNSAFE_MATH,
145 DBG_SI_SCHED,
146 DBG_GISEL,
147
148 /* Shader compiler options (with no effect on the shader cache): */
149 DBG_CHECK_IR,
150 DBG_MONOLITHIC_SHADERS,
151 DBG_NO_OPT_VARIANT,
152
153 /* Information logging options: */
154 DBG_INFO,
155 DBG_TEX,
156 DBG_COMPUTE,
157 DBG_VM,
158
159 /* Driver options: */
160 DBG_FORCE_DMA,
161 DBG_NO_ASYNC_DMA,
162 DBG_NO_WC,
163 DBG_CHECK_VM,
164 DBG_RESERVE_VMID,
165 DBG_ZERO_VRAM,
166
167 /* 3D engine options: */
168 DBG_SWITCH_ON_EOP,
169 DBG_NO_OUT_OF_ORDER,
170 DBG_NO_DPBB,
171 DBG_NO_DFSM,
172 DBG_DPBB,
173 DBG_DFSM,
174 DBG_NO_HYPERZ,
175 DBG_NO_RB_PLUS,
176 DBG_NO_2D_TILING,
177 DBG_NO_TILING,
178 DBG_NO_DCC,
179 DBG_NO_DCC_CLEAR,
180 DBG_NO_DCC_FB,
181 DBG_NO_DCC_MSAA,
182 DBG_NO_FMASK,
183
184 /* Tests: */
185 DBG_TEST_DMA,
186 DBG_TEST_VMFAULT_CP,
187 DBG_TEST_VMFAULT_SDMA,
188 DBG_TEST_VMFAULT_SHADER,
189 DBG_TEST_DMA_PERF,
190 DBG_TEST_GDS,
191 DBG_TEST_GDS_MM,
192 DBG_TEST_GDS_OA_MM,
193 };
194
195 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
196 #define DBG(name) (1ull << DBG_##name)
197
198 enum si_cache_policy {
199 L2_BYPASS,
200 L2_STREAM, /* same as SLC=1 */
201 L2_LRU, /* same as SLC=0 */
202 };
203
204 enum si_coherency {
205 SI_COHERENCY_NONE, /* no cache flushes needed */
206 SI_COHERENCY_SHADER,
207 SI_COHERENCY_CB_META,
208 SI_COHERENCY_CP,
209 };
210
211 struct si_compute;
212 struct hash_table;
213 struct u_suballocator;
214
215 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
216 * at the moment.
217 */
218 struct si_resource {
219 struct threaded_resource b;
220
221 /* Winsys objects. */
222 struct pb_buffer *buf;
223 uint64_t gpu_address;
224 /* Memory usage if the buffer placement is optimal. */
225 uint64_t vram_usage;
226 uint64_t gart_usage;
227
228 /* Resource properties. */
229 uint64_t bo_size;
230 unsigned bo_alignment;
231 enum radeon_bo_domain domains;
232 enum radeon_bo_flag flags;
233 unsigned bind_history;
234 int max_forced_staging_uploads;
235
236 /* The buffer range which is initialized (with a write transfer,
237 * streamout, DMA, or as a random access target). The rest of
238 * the buffer is considered invalid and can be mapped unsynchronized.
239 *
240 * This allows unsychronized mapping of a buffer range which hasn't
241 * been used yet. It's for applications which forget to use
242 * the unsynchronized map flag and expect the driver to figure it out.
243 */
244 struct util_range valid_buffer_range;
245
246 /* For buffers only. This indicates that a write operation has been
247 * performed by TC L2, but the cache hasn't been flushed.
248 * Any hw block which doesn't use or bypasses TC L2 should check this
249 * flag and flush the cache before using the buffer.
250 *
251 * For example, TC L2 must be flushed if a buffer which has been
252 * modified by a shader store instruction is about to be used as
253 * an index buffer. The reason is that VGT DMA index fetching doesn't
254 * use TC L2.
255 */
256 bool TC_L2_dirty;
257
258 /* Whether this resource is referenced by bindless handles. */
259 bool texture_handle_allocated;
260 bool image_handle_allocated;
261
262 /* Whether the resource has been exported via resource_get_handle. */
263 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
264 };
265
266 struct si_transfer {
267 struct threaded_transfer b;
268 struct si_resource *staging;
269 unsigned offset;
270 };
271
272 struct si_texture {
273 struct si_resource buffer;
274
275 struct radeon_surf surface;
276 uint64_t size;
277 struct si_texture *flushed_depth_texture;
278
279 /* One texture allocation can contain these buffers:
280 * - image (pixel data)
281 * - FMASK buffer (MSAA compression)
282 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
283 * - HTILE buffer (Z/S compression and fast Z/S clear)
284 * - DCC buffer (color compression and new fast color clear)
285 * - displayable DCC buffer (if the DCC buffer is not displayable)
286 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
287 */
288 uint64_t fmask_offset;
289 uint64_t cmask_offset;
290 uint64_t cmask_base_address_reg;
291 struct si_resource *cmask_buffer;
292 uint64_t dcc_offset; /* 0 = disabled */
293 uint64_t display_dcc_offset;
294 uint64_t dcc_retile_map_offset;
295 unsigned cb_color_info; /* fast clear enable bit */
296 unsigned color_clear_value[2];
297 unsigned last_msaa_resolve_target_micro_mode;
298 unsigned num_level0_transfers;
299
300 /* Depth buffer compression and fast clear. */
301 uint64_t htile_offset;
302 float depth_clear_value;
303 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
304 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
305 enum pipe_format db_render_format:16;
306 uint8_t stencil_clear_value;
307 bool tc_compatible_htile:1;
308 bool depth_cleared:1; /* if it was cleared at least once */
309 bool stencil_cleared:1; /* if it was cleared at least once */
310 bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
311 bool is_depth:1;
312 bool db_compatible:1;
313 bool can_sample_z:1;
314 bool can_sample_s:1;
315
316 /* We need to track DCC dirtiness, because st/dri usually calls
317 * flush_resource twice per frame (not a bug) and we don't wanna
318 * decompress DCC twice. Also, the dirty tracking must be done even
319 * if DCC isn't used, because it's required by the DCC usage analysis
320 * for a possible future enablement.
321 */
322 bool separate_dcc_dirty:1;
323 /* Statistics gathering for the DCC enablement heuristic. */
324 bool dcc_gather_statistics:1;
325 /* Counter that should be non-zero if the texture is bound to a
326 * framebuffer.
327 */
328 unsigned framebuffers_bound;
329 /* Whether the texture is a displayable back buffer and needs DCC
330 * decompression, which is expensive. Therefore, it's enabled only
331 * if statistics suggest that it will pay off and it's allocated
332 * separately. It can't be bound as a sampler by apps. Limited to
333 * target == 2D and last_level == 0. If enabled, dcc_offset contains
334 * the absolute GPUVM address, not the relative one.
335 */
336 struct si_resource *dcc_separate_buffer;
337 /* When DCC is temporarily disabled, the separate buffer is here. */
338 struct si_resource *last_dcc_separate_buffer;
339 /* Estimate of how much this color buffer is written to in units of
340 * full-screen draws: ps_invocations / (width * height)
341 * Shader kills, late Z, and blending with trivial discards make it
342 * inaccurate (we need to count CB updates, not PS invocations).
343 */
344 unsigned ps_draw_ratio;
345 /* The number of clears since the last DCC usage analysis. */
346 unsigned num_slow_clears;
347 };
348
349 struct si_surface {
350 struct pipe_surface base;
351
352 /* These can vary with block-compressed textures. */
353 uint16_t width0;
354 uint16_t height0;
355
356 bool color_initialized:1;
357 bool depth_initialized:1;
358
359 /* Misc. color flags. */
360 bool color_is_int8:1;
361 bool color_is_int10:1;
362 bool dcc_incompatible:1;
363
364 /* Color registers. */
365 unsigned cb_color_info;
366 unsigned cb_color_view;
367 unsigned cb_color_attrib;
368 unsigned cb_color_attrib2; /* GFX9 and later */
369 unsigned cb_dcc_control; /* VI and later */
370 unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */
371 unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
372 unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
373 unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
374
375 /* DB registers. */
376 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
377 uint64_t db_stencil_base;
378 uint64_t db_htile_data_base;
379 unsigned db_depth_info;
380 unsigned db_z_info;
381 unsigned db_z_info2; /* GFX9+ */
382 unsigned db_depth_view;
383 unsigned db_depth_size;
384 unsigned db_depth_slice;
385 unsigned db_stencil_info;
386 unsigned db_stencil_info2; /* GFX9+ */
387 unsigned db_htile_surface;
388 };
389
390 struct si_mmio_counter {
391 unsigned busy;
392 unsigned idle;
393 };
394
395 union si_mmio_counters {
396 struct {
397 /* For global GPU load including SDMA. */
398 struct si_mmio_counter gpu;
399
400 /* GRBM_STATUS */
401 struct si_mmio_counter spi;
402 struct si_mmio_counter gui;
403 struct si_mmio_counter ta;
404 struct si_mmio_counter gds;
405 struct si_mmio_counter vgt;
406 struct si_mmio_counter ia;
407 struct si_mmio_counter sx;
408 struct si_mmio_counter wd;
409 struct si_mmio_counter bci;
410 struct si_mmio_counter sc;
411 struct si_mmio_counter pa;
412 struct si_mmio_counter db;
413 struct si_mmio_counter cp;
414 struct si_mmio_counter cb;
415
416 /* SRBM_STATUS2 */
417 struct si_mmio_counter sdma;
418
419 /* CP_STAT */
420 struct si_mmio_counter pfp;
421 struct si_mmio_counter meq;
422 struct si_mmio_counter me;
423 struct si_mmio_counter surf_sync;
424 struct si_mmio_counter cp_dma;
425 struct si_mmio_counter scratch_ram;
426 } named;
427 unsigned array[0];
428 };
429
430 struct si_memory_object {
431 struct pipe_memory_object b;
432 struct pb_buffer *buf;
433 uint32_t stride;
434 };
435
436 /* Saved CS data for debugging features. */
437 struct radeon_saved_cs {
438 uint32_t *ib;
439 unsigned num_dw;
440
441 struct radeon_bo_list_item *bo_list;
442 unsigned bo_count;
443 };
444
445 struct si_screen {
446 struct pipe_screen b;
447 struct radeon_winsys *ws;
448 struct disk_cache *disk_shader_cache;
449
450 struct radeon_info info;
451 uint64_t debug_flags;
452 char renderer_string[183];
453
454 unsigned pa_sc_raster_config;
455 unsigned pa_sc_raster_config_1;
456 unsigned se_tile_repeat;
457 unsigned gs_table_depth;
458 unsigned tess_offchip_block_dw_size;
459 unsigned tess_offchip_ring_size;
460 unsigned tess_factor_ring_size;
461 unsigned vgt_hs_offchip_param;
462 unsigned eqaa_force_coverage_samples;
463 unsigned eqaa_force_z_samples;
464 unsigned eqaa_force_color_samples;
465 bool has_clear_state;
466 bool has_distributed_tess;
467 bool has_draw_indirect_multi;
468 bool has_out_of_order_rast;
469 bool assume_no_z_fights;
470 bool commutative_blend_add;
471 bool has_msaa_sample_loc_bug;
472 bool has_ls_vgpr_init_bug;
473 bool has_dcc_constant_encode;
474 bool dpbb_allowed;
475 bool dfsm_allowed;
476 bool llvm_has_working_vgpr_indexing;
477
478 struct {
479 #define OPT_BOOL(name, dflt, description) bool name:1;
480 #include "si_debug_options.h"
481 } options;
482
483 /* Whether shaders are monolithic (1-part) or separate (3-part). */
484 bool use_monolithic_shaders;
485 bool record_llvm_ir;
486 bool has_rbplus; /* if RB+ registers exist */
487 bool rbplus_allowed; /* if RB+ is allowed */
488 bool dcc_msaa_allowed;
489 bool cpdma_prefetch_writes_memory;
490
491 struct slab_parent_pool pool_transfers;
492
493 /* Texture filter settings. */
494 int force_aniso; /* -1 = disabled */
495
496 /* Auxiliary context. Mainly used to initialize resources.
497 * It must be locked prior to using and flushed before unlocking. */
498 struct pipe_context *aux_context;
499 mtx_t aux_context_lock;
500
501 /* This must be in the screen, because UE4 uses one context for
502 * compilation and another one for rendering.
503 */
504 unsigned num_compilations;
505 /* Along with ST_DEBUG=precompile, this should show if applications
506 * are loading shaders on demand. This is a monotonic counter.
507 */
508 unsigned num_shaders_created;
509 unsigned num_shader_cache_hits;
510
511 /* GPU load thread. */
512 mtx_t gpu_load_mutex;
513 thrd_t gpu_load_thread;
514 union si_mmio_counters mmio_counters;
515 volatile unsigned gpu_load_stop_thread; /* bool */
516
517 /* Performance counters. */
518 struct si_perfcounters *perfcounters;
519
520 /* If pipe_screen wants to recompute and re-emit the framebuffer,
521 * sampler, and image states of all contexts, it should atomically
522 * increment this.
523 *
524 * Each context will compare this with its own last known value of
525 * the counter before drawing and re-emit the states accordingly.
526 */
527 unsigned dirty_tex_counter;
528
529 /* Atomically increment this counter when an existing texture's
530 * metadata is enabled or disabled in a way that requires changing
531 * contexts' compressed texture binding masks.
532 */
533 unsigned compressed_colortex_counter;
534
535 struct {
536 /* Context flags to set so that all writes from earlier jobs
537 * in the CP are seen by L2 clients.
538 */
539 unsigned cp_to_L2;
540
541 /* Context flags to set so that all writes from earlier jobs
542 * that end in L2 are seen by CP.
543 */
544 unsigned L2_to_cp;
545 } barrier_flags;
546
547 mtx_t shader_parts_mutex;
548 struct si_shader_part *vs_prologs;
549 struct si_shader_part *tcs_epilogs;
550 struct si_shader_part *gs_prologs;
551 struct si_shader_part *ps_prologs;
552 struct si_shader_part *ps_epilogs;
553
554 /* Shader cache in memory.
555 *
556 * Design & limitations:
557 * - The shader cache is per screen (= per process), never saved to
558 * disk, and skips redundant shader compilations from TGSI to bytecode.
559 * - It can only be used with one-variant-per-shader support, in which
560 * case only the main (typically middle) part of shaders is cached.
561 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
562 * variants of VS and TES are cached, so LS and ES aren't.
563 * - GS and CS aren't cached, but it's certainly possible to cache
564 * those as well.
565 */
566 mtx_t shader_cache_mutex;
567 struct hash_table *shader_cache;
568
569 /* Shader compiler queue for multithreaded compilation. */
570 struct util_queue shader_compiler_queue;
571 /* Use at most 3 normal compiler threads on quadcore and better.
572 * Hyperthreaded CPUs report the number of threads, but we want
573 * the number of cores. We only need this many threads for shader-db. */
574 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
575
576 struct util_queue shader_compiler_queue_low_priority;
577 /* Use at most 2 low priority threads on quadcore and better.
578 * We want to minimize the impact on multithreaded Mesa. */
579 struct ac_llvm_compiler compiler_lowp[10];
580 };
581
582 struct si_blend_color {
583 struct pipe_blend_color state;
584 bool any_nonzeros;
585 };
586
587 struct si_sampler_view {
588 struct pipe_sampler_view base;
589 /* [0..7] = image descriptor
590 * [4..7] = buffer descriptor */
591 uint32_t state[8];
592 uint32_t fmask_state[8];
593 const struct legacy_surf_level *base_level_info;
594 ubyte base_level;
595 ubyte block_width;
596 bool is_stencil_sampler;
597 bool is_integer;
598 bool dcc_incompatible;
599 };
600
601 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
602
603 struct si_sampler_state {
604 #ifdef DEBUG
605 unsigned magic;
606 #endif
607 uint32_t val[4];
608 uint32_t integer_val[4];
609 uint32_t upgraded_depth_val[4];
610 };
611
612 struct si_cs_shader_state {
613 struct si_compute *program;
614 struct si_compute *emitted_program;
615 unsigned offset;
616 bool initialized;
617 bool uses_scratch;
618 };
619
620 struct si_samplers {
621 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
622 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
623
624 /* The i-th bit is set if that element is enabled (non-NULL resource). */
625 unsigned enabled_mask;
626 uint32_t needs_depth_decompress_mask;
627 uint32_t needs_color_decompress_mask;
628 };
629
630 struct si_images {
631 struct pipe_image_view views[SI_NUM_IMAGES];
632 uint32_t needs_color_decompress_mask;
633 unsigned enabled_mask;
634 };
635
636 struct si_framebuffer {
637 struct pipe_framebuffer_state state;
638 unsigned colorbuf_enabled_4bit;
639 unsigned spi_shader_col_format;
640 unsigned spi_shader_col_format_alpha;
641 unsigned spi_shader_col_format_blend;
642 unsigned spi_shader_col_format_blend_alpha;
643 ubyte nr_samples:5; /* at most 16xAA */
644 ubyte log_samples:3; /* at most 4 = 16xAA */
645 ubyte nr_color_samples; /* at most 8xAA */
646 ubyte compressed_cb_mask;
647 ubyte uncompressed_cb_mask;
648 ubyte color_is_int8;
649 ubyte color_is_int10;
650 ubyte dirty_cbufs;
651 ubyte dcc_overwrite_combiner_watermark;
652 bool dirty_zsbuf;
653 bool any_dst_linear;
654 bool CB_has_shader_readable_metadata;
655 bool DB_has_shader_readable_metadata;
656 bool all_DCC_pipe_aligned;
657 };
658
659 enum si_quant_mode {
660 /* This is the list we want to support. */
661 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
662 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
663 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
664 };
665
666 struct si_signed_scissor {
667 int minx;
668 int miny;
669 int maxx;
670 int maxy;
671 enum si_quant_mode quant_mode;
672 };
673
674 struct si_scissors {
675 unsigned dirty_mask;
676 struct pipe_scissor_state states[SI_MAX_VIEWPORTS];
677 };
678
679 struct si_viewports {
680 unsigned dirty_mask;
681 unsigned depth_range_dirty_mask;
682 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
683 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
684 };
685
686 struct si_clip_state {
687 struct pipe_clip_state state;
688 bool any_nonzeros;
689 };
690
691 struct si_streamout_target {
692 struct pipe_stream_output_target b;
693
694 /* The buffer where BUFFER_FILLED_SIZE is stored. */
695 struct si_resource *buf_filled_size;
696 unsigned buf_filled_size_offset;
697 bool buf_filled_size_valid;
698
699 unsigned stride_in_dw;
700 };
701
702 struct si_streamout {
703 bool begin_emitted;
704
705 unsigned enabled_mask;
706 unsigned num_targets;
707 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
708
709 unsigned append_bitmask;
710 bool suspended;
711
712 /* External state which comes from the vertex shader,
713 * it must be set explicitly when binding a shader. */
714 uint16_t *stride_in_dw;
715 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
716
717 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
718 unsigned hw_enabled_mask;
719
720 /* The state of VGT_STRMOUT_(CONFIG|EN). */
721 bool streamout_enabled;
722 bool prims_gen_query_enabled;
723 int num_prims_gen_queries;
724 };
725
726 /* A shader state consists of the shader selector, which is a constant state
727 * object shared by multiple contexts and shouldn't be modified, and
728 * the current shader variant selected for this context.
729 */
730 struct si_shader_ctx_state {
731 struct si_shader_selector *cso;
732 struct si_shader *current;
733 };
734
735 #define SI_NUM_VGT_PARAM_KEY_BITS 12
736 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
737
738 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
739 * Some fields are set by state-change calls, most are set by draw_vbo.
740 */
741 union si_vgt_param_key {
742 struct {
743 #ifdef PIPE_ARCH_LITTLE_ENDIAN
744 unsigned prim:4;
745 unsigned uses_instancing:1;
746 unsigned multi_instances_smaller_than_primgroup:1;
747 unsigned primitive_restart:1;
748 unsigned count_from_stream_output:1;
749 unsigned line_stipple_enabled:1;
750 unsigned uses_tess:1;
751 unsigned tess_uses_prim_id:1;
752 unsigned uses_gs:1;
753 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
754 #else /* PIPE_ARCH_BIG_ENDIAN */
755 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
756 unsigned uses_gs:1;
757 unsigned tess_uses_prim_id:1;
758 unsigned uses_tess:1;
759 unsigned line_stipple_enabled:1;
760 unsigned count_from_stream_output:1;
761 unsigned primitive_restart:1;
762 unsigned multi_instances_smaller_than_primgroup:1;
763 unsigned uses_instancing:1;
764 unsigned prim:4;
765 #endif
766 } u;
767 uint32_t index;
768 };
769
770 struct si_texture_handle
771 {
772 unsigned desc_slot;
773 bool desc_dirty;
774 struct pipe_sampler_view *view;
775 struct si_sampler_state sstate;
776 };
777
778 struct si_image_handle
779 {
780 unsigned desc_slot;
781 bool desc_dirty;
782 struct pipe_image_view view;
783 };
784
785 struct si_saved_cs {
786 struct pipe_reference reference;
787 struct si_context *ctx;
788 struct radeon_saved_cs gfx;
789 struct si_resource *trace_buf;
790 unsigned trace_id;
791
792 unsigned gfx_last_dw;
793 bool flushed;
794 int64_t time_flush;
795 };
796
797 struct si_sdma_upload {
798 struct si_resource *dst;
799 struct si_resource *src;
800 unsigned src_offset;
801 unsigned dst_offset;
802 unsigned size;
803 };
804
805 struct si_context {
806 struct pipe_context b; /* base class */
807
808 enum radeon_family family;
809 enum chip_class chip_class;
810
811 struct radeon_winsys *ws;
812 struct radeon_winsys_ctx *ctx;
813 struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
814 struct radeon_cmdbuf *dma_cs;
815 struct pipe_fence_handle *last_gfx_fence;
816 struct pipe_fence_handle *last_sdma_fence;
817 struct si_resource *eop_bug_scratch;
818 struct u_upload_mgr *cached_gtt_allocator;
819 struct threaded_context *tc;
820 struct u_suballocator *allocator_zeroed_memory;
821 struct slab_child_pool pool_transfers;
822 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
823 struct pipe_device_reset_callback device_reset_callback;
824 struct u_log_context *log;
825 void *query_result_shader;
826 struct blitter_context *blitter;
827 void *custom_dsa_flush;
828 void *custom_blend_resolve;
829 void *custom_blend_fmask_decompress;
830 void *custom_blend_eliminate_fastclear;
831 void *custom_blend_dcc_decompress;
832 void *vs_blit_pos;
833 void *vs_blit_pos_layered;
834 void *vs_blit_color;
835 void *vs_blit_color_layered;
836 void *vs_blit_texcoord;
837 void *cs_clear_buffer;
838 void *cs_copy_buffer;
839 void *cs_copy_image;
840 void *cs_copy_image_1d_array;
841 void *cs_clear_render_target;
842 void *cs_clear_render_target_1d_array;
843 void *cs_dcc_retile;
844 struct si_screen *screen;
845 struct pipe_debug_callback debug;
846 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
847 struct si_shader_ctx_state fixed_func_tcs_shader;
848 struct si_resource *wait_mem_scratch;
849 unsigned wait_mem_number;
850 uint16_t prefetch_L2_mask;
851
852 bool has_graphics;
853 bool gfx_flush_in_progress:1;
854 bool gfx_last_ib_is_busy:1;
855 bool compute_is_busy:1;
856
857 unsigned num_gfx_cs_flushes;
858 unsigned initial_gfx_cs_size;
859 unsigned gpu_reset_counter;
860 unsigned last_dirty_tex_counter;
861 unsigned last_compressed_colortex_counter;
862 unsigned last_num_draw_calls;
863 unsigned flags; /* flush flags */
864 /* Current unaccounted memory usage. */
865 uint64_t vram;
866 uint64_t gtt;
867
868 /* Atoms (direct states). */
869 union si_state_atoms atoms;
870 unsigned dirty_atoms; /* mask */
871 /* PM4 states (precomputed immutable states) */
872 unsigned dirty_states;
873 union si_state queued;
874 union si_state emitted;
875
876 /* Atom declarations. */
877 struct si_framebuffer framebuffer;
878 unsigned sample_locs_num_samples;
879 uint16_t sample_mask;
880 unsigned last_cb_target_mask;
881 struct si_blend_color blend_color;
882 struct si_clip_state clip_state;
883 struct si_shader_data shader_pointers;
884 struct si_stencil_ref stencil_ref;
885 struct si_scissors scissors;
886 struct si_streamout streamout;
887 struct si_viewports viewports;
888 unsigned num_window_rectangles;
889 bool window_rectangles_include;
890 struct pipe_scissor_state window_rectangles[4];
891
892 /* Precomputed states. */
893 struct si_pm4_state *init_config;
894 struct si_pm4_state *init_config_gs_rings;
895 bool init_config_has_vgt_flush;
896 struct si_pm4_state *vgt_shader_config[4];
897
898 /* shaders */
899 struct si_shader_ctx_state ps_shader;
900 struct si_shader_ctx_state gs_shader;
901 struct si_shader_ctx_state vs_shader;
902 struct si_shader_ctx_state tcs_shader;
903 struct si_shader_ctx_state tes_shader;
904 struct si_cs_shader_state cs_shader_state;
905
906 /* shader information */
907 struct si_vertex_elements *vertex_elements;
908 unsigned sprite_coord_enable;
909 unsigned cs_max_waves_per_sh;
910 bool flatshade;
911 bool do_update_shaders;
912
913 /* vertex buffer descriptors */
914 uint32_t *vb_descriptors_gpu_list;
915 struct si_resource *vb_descriptors_buffer;
916 unsigned vb_descriptors_offset;
917
918 /* shader descriptors */
919 struct si_descriptors descriptors[SI_NUM_DESCS];
920 unsigned descriptors_dirty;
921 unsigned shader_pointers_dirty;
922 unsigned shader_needs_decompress_mask;
923 struct si_buffer_resources rw_buffers;
924 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
925 struct si_samplers samplers[SI_NUM_SHADERS];
926 struct si_images images[SI_NUM_SHADERS];
927 bool bo_list_add_all_resident_resources;
928 bool bo_list_add_all_gfx_resources;
929 bool bo_list_add_all_compute_resources;
930
931 /* other shader resources */
932 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
933 struct pipe_resource *esgs_ring;
934 struct pipe_resource *gsvs_ring;
935 struct pipe_resource *tess_rings;
936 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
937 struct si_resource *border_color_buffer;
938 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
939 unsigned border_color_count;
940 unsigned num_vs_blit_sgprs;
941 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
942 uint32_t cs_user_data[4];
943
944 /* Vertex and index buffers. */
945 bool vertex_buffers_dirty;
946 bool vertex_buffer_pointer_dirty;
947 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
948
949 /* MSAA config state. */
950 int ps_iter_samples;
951 bool ps_uses_fbfetch;
952 bool smoothing_enabled;
953
954 /* DB render state. */
955 unsigned ps_db_shader_control;
956 unsigned dbcb_copy_sample;
957 bool dbcb_depth_copy_enabled:1;
958 bool dbcb_stencil_copy_enabled:1;
959 bool db_flush_depth_inplace:1;
960 bool db_flush_stencil_inplace:1;
961 bool db_depth_clear:1;
962 bool db_depth_disable_expclear:1;
963 bool db_stencil_clear:1;
964 bool db_stencil_disable_expclear:1;
965 bool occlusion_queries_disabled:1;
966 bool generate_mipmap_for_depth:1;
967
968 /* Emitted draw state. */
969 bool gs_tri_strip_adj_fix:1;
970 bool ls_vgpr_fix:1;
971 int last_index_size;
972 int last_base_vertex;
973 int last_start_instance;
974 int last_instance_count;
975 int last_drawid;
976 int last_sh_base_reg;
977 int last_primitive_restart_en;
978 int last_restart_index;
979 int last_prim;
980 int last_multi_vgt_param;
981 int last_rast_prim;
982 unsigned last_sc_line_stipple;
983 unsigned current_vs_state;
984 unsigned last_vs_state;
985 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
986
987 /* Scratch buffer */
988 struct si_resource *scratch_buffer;
989 unsigned scratch_waves;
990 unsigned spi_tmpring_size;
991
992 struct si_resource *compute_scratch_buffer;
993
994 /* Emitted derived tessellation state. */
995 /* Local shader (VS), or HS if LS-HS are merged. */
996 struct si_shader *last_ls;
997 struct si_shader_selector *last_tcs;
998 int last_num_tcs_input_cp;
999 int last_tes_sh_base;
1000 bool last_tess_uses_primid;
1001 unsigned last_num_patches;
1002 int last_ls_hs_config;
1003
1004 /* Debug state. */
1005 bool is_debug;
1006 struct si_saved_cs *current_saved_cs;
1007 uint64_t dmesg_timestamp;
1008 unsigned apitrace_call_number;
1009
1010 /* Other state */
1011 bool need_check_render_feedback;
1012 bool decompression_enabled;
1013 bool dpbb_force_off;
1014 bool vs_writes_viewport_index;
1015 bool vs_disables_clipping_viewport;
1016
1017 /* Precomputed IA_MULTI_VGT_PARAM */
1018 union si_vgt_param_key ia_multi_vgt_param_key;
1019 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1020
1021 /* Bindless descriptors. */
1022 struct si_descriptors bindless_descriptors;
1023 struct util_idalloc bindless_used_slots;
1024 unsigned num_bindless_descriptors;
1025 bool bindless_descriptors_dirty;
1026 bool graphics_bindless_pointer_dirty;
1027 bool compute_bindless_pointer_dirty;
1028
1029 /* Allocated bindless handles */
1030 struct hash_table *tex_handles;
1031 struct hash_table *img_handles;
1032
1033 /* Resident bindless handles */
1034 struct util_dynarray resident_tex_handles;
1035 struct util_dynarray resident_img_handles;
1036
1037 /* Resident bindless handles which need decompression */
1038 struct util_dynarray resident_tex_needs_color_decompress;
1039 struct util_dynarray resident_img_needs_color_decompress;
1040 struct util_dynarray resident_tex_needs_depth_decompress;
1041
1042 /* Bindless state */
1043 bool uses_bindless_samplers;
1044 bool uses_bindless_images;
1045
1046 /* MSAA sample locations.
1047 * The first index is the sample index.
1048 * The second index is the coordinate: X, Y. */
1049 struct {
1050 float x1[1][2];
1051 float x2[2][2];
1052 float x4[4][2];
1053 float x8[8][2];
1054 float x16[16][2];
1055 } sample_positions;
1056 struct pipe_resource *sample_pos_buffer;
1057
1058 /* Misc stats. */
1059 unsigned num_draw_calls;
1060 unsigned num_decompress_calls;
1061 unsigned num_mrt_draw_calls;
1062 unsigned num_prim_restart_calls;
1063 unsigned num_spill_draw_calls;
1064 unsigned num_compute_calls;
1065 unsigned num_spill_compute_calls;
1066 unsigned num_dma_calls;
1067 unsigned num_cp_dma_calls;
1068 unsigned num_vs_flushes;
1069 unsigned num_ps_flushes;
1070 unsigned num_cs_flushes;
1071 unsigned num_cb_cache_flushes;
1072 unsigned num_db_cache_flushes;
1073 unsigned num_L2_invalidates;
1074 unsigned num_L2_writebacks;
1075 unsigned num_resident_handles;
1076 uint64_t num_alloc_tex_transfer_bytes;
1077 unsigned last_tex_ps_draw_ratio; /* for query */
1078 unsigned context_roll_counter;
1079
1080 /* Queries. */
1081 /* Maintain the list of active queries for pausing between IBs. */
1082 int num_occlusion_queries;
1083 int num_perfect_occlusion_queries;
1084 struct list_head active_queries;
1085 unsigned num_cs_dw_queries_suspend;
1086
1087 /* Render condition. */
1088 struct pipe_query *render_cond;
1089 unsigned render_cond_mode;
1090 bool render_cond_invert;
1091 bool render_cond_force_off; /* for u_blitter */
1092
1093 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1094 bool sdma_uploads_in_progress;
1095 struct si_sdma_upload *sdma_uploads;
1096 unsigned num_sdma_uploads;
1097 unsigned max_sdma_uploads;
1098
1099 /* Statistics gathering for the DCC enablement heuristic. It can't be
1100 * in si_texture because si_texture can be shared by multiple
1101 * contexts. This is for back buffers only. We shouldn't get too many
1102 * of those.
1103 *
1104 * X11 DRI3 rotates among a finite set of back buffers. They should
1105 * all fit in this array. If they don't, separate DCC might never be
1106 * enabled by DCC stat gathering.
1107 */
1108 struct {
1109 struct si_texture *tex;
1110 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1111 struct pipe_query *ps_stats[3];
1112 /* If all slots are used and another slot is needed,
1113 * the least recently used slot is evicted based on this. */
1114 int64_t last_use_timestamp;
1115 bool query_active;
1116 } dcc_stats[5];
1117
1118 /* Copy one resource to another using async DMA. */
1119 void (*dma_copy)(struct pipe_context *ctx,
1120 struct pipe_resource *dst,
1121 unsigned dst_level,
1122 unsigned dst_x, unsigned dst_y, unsigned dst_z,
1123 struct pipe_resource *src,
1124 unsigned src_level,
1125 const struct pipe_box *src_box);
1126
1127 struct si_tracked_regs tracked_regs;
1128 };
1129
1130 /* cik_sdma.c */
1131 void cik_init_sdma_functions(struct si_context *sctx);
1132
1133 /* si_blit.c */
1134 enum si_blitter_op /* bitmask */
1135 {
1136 SI_SAVE_TEXTURES = 1,
1137 SI_SAVE_FRAMEBUFFER = 2,
1138 SI_SAVE_FRAGMENT_STATE = 4,
1139 SI_DISABLE_RENDER_COND = 8,
1140 };
1141
1142 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1143 void si_blitter_end(struct si_context *sctx);
1144 void si_init_blit_functions(struct si_context *sctx);
1145 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1146 void si_resource_copy_region(struct pipe_context *ctx,
1147 struct pipe_resource *dst,
1148 unsigned dst_level,
1149 unsigned dstx, unsigned dsty, unsigned dstz,
1150 struct pipe_resource *src,
1151 unsigned src_level,
1152 const struct pipe_box *src_box);
1153 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1154 void si_blit_decompress_depth(struct pipe_context *ctx,
1155 struct si_texture *texture,
1156 struct si_texture *staging,
1157 unsigned first_level, unsigned last_level,
1158 unsigned first_layer, unsigned last_layer,
1159 unsigned first_sample, unsigned last_sample);
1160
1161 /* si_buffer.c */
1162 bool si_rings_is_buffer_referenced(struct si_context *sctx,
1163 struct pb_buffer *buf,
1164 enum radeon_bo_usage usage);
1165 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
1166 struct si_resource *resource,
1167 unsigned usage);
1168 void si_init_resource_fields(struct si_screen *sscreen,
1169 struct si_resource *res,
1170 uint64_t size, unsigned alignment);
1171 bool si_alloc_resource(struct si_screen *sscreen,
1172 struct si_resource *res);
1173 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
1174 unsigned flags, unsigned usage,
1175 unsigned size, unsigned alignment);
1176 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen,
1177 unsigned flags, unsigned usage,
1178 unsigned size, unsigned alignment);
1179 void si_replace_buffer_storage(struct pipe_context *ctx,
1180 struct pipe_resource *dst,
1181 struct pipe_resource *src);
1182 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1183 void si_init_buffer_functions(struct si_context *sctx);
1184
1185 /* si_clear.c */
1186 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1187 bool vi_alpha_is_on_msb(enum pipe_format format);
1188 void vi_dcc_clear_level(struct si_context *sctx,
1189 struct si_texture *tex,
1190 unsigned level, unsigned clear_value);
1191 void si_init_clear_functions(struct si_context *sctx);
1192
1193 /* si_compute_blit.c */
1194 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1195 enum si_cache_policy cache_policy);
1196 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1197 uint64_t offset, uint64_t size, uint32_t *clear_value,
1198 uint32_t clear_value_size, enum si_coherency coher,
1199 bool force_cpdma);
1200 void si_copy_buffer(struct si_context *sctx,
1201 struct pipe_resource *dst, struct pipe_resource *src,
1202 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1203 void si_compute_copy_image(struct si_context *sctx,
1204 struct pipe_resource *dst,
1205 unsigned dst_level,
1206 struct pipe_resource *src,
1207 unsigned src_level,
1208 unsigned dstx, unsigned dsty, unsigned dstz,
1209 const struct pipe_box *src_box);
1210 void si_compute_clear_render_target(struct pipe_context *ctx,
1211 struct pipe_surface *dstsurf,
1212 const union pipe_color_union *color,
1213 unsigned dstx, unsigned dsty,
1214 unsigned width, unsigned height,
1215 bool render_condition_enabled);
1216 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1217 void si_init_compute_blit_functions(struct si_context *sctx);
1218
1219 /* si_cp_dma.c */
1220 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1221 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1222 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1223 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1224 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1225 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1226 SI_CPDMA_SKIP_SYNC_AFTER | \
1227 SI_CPDMA_SKIP_SYNC_BEFORE | \
1228 SI_CPDMA_SKIP_GFX_SYNC | \
1229 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1230
1231 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1232 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1233 struct pipe_resource *dst, uint64_t offset,
1234 uint64_t size, unsigned value, unsigned user_flags,
1235 enum si_coherency coher, enum si_cache_policy cache_policy);
1236 void si_cp_dma_copy_buffer(struct si_context *sctx,
1237 struct pipe_resource *dst, struct pipe_resource *src,
1238 uint64_t dst_offset, uint64_t src_offset, unsigned size,
1239 unsigned user_flags, enum si_coherency coher,
1240 enum si_cache_policy cache_policy);
1241 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
1242 uint64_t offset, unsigned size);
1243 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1244 void si_test_gds(struct si_context *sctx);
1245 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf,
1246 unsigned offset, unsigned size, unsigned dst_sel,
1247 unsigned engine, const void *data);
1248 void si_cp_copy_data(struct si_context *sctx,
1249 unsigned dst_sel, struct si_resource *dst, unsigned dst_offset,
1250 unsigned src_sel, struct si_resource *src, unsigned src_offset);
1251
1252 /* si_debug.c */
1253 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
1254 struct radeon_saved_cs *saved, bool get_buffer_list);
1255 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1256 void si_destroy_saved_cs(struct si_saved_cs *scs);
1257 void si_auto_log_cs(void *data, struct u_log_context *log);
1258 void si_log_hw_flush(struct si_context *sctx);
1259 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1260 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1261 void si_init_debug_functions(struct si_context *sctx);
1262 void si_check_vm_faults(struct si_context *sctx,
1263 struct radeon_saved_cs *saved, enum ring_type ring);
1264 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
1265
1266 /* si_dma.c */
1267 void si_init_dma_functions(struct si_context *sctx);
1268
1269 /* si_dma_cs.c */
1270 void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst,
1271 uint64_t offset);
1272 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1273 uint64_t offset, uint64_t size, unsigned clear_value);
1274 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
1275 struct si_resource *dst, struct si_resource *src);
1276 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
1277 struct pipe_fence_handle **fence);
1278 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
1279 uint64_t offset, uint64_t size, unsigned value);
1280
1281 /* si_fence.c */
1282 void si_cp_release_mem(struct si_context *ctx,
1283 unsigned event, unsigned event_flags,
1284 unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1285 struct si_resource *buf, uint64_t va,
1286 uint32_t new_fence, unsigned query_type);
1287 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1288 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1289 uint64_t va, uint32_t ref, uint32_t mask, unsigned flags);
1290 void si_init_fence_functions(struct si_context *ctx);
1291 void si_init_screen_fence_functions(struct si_screen *screen);
1292 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1293 struct tc_unflushed_batch_token *tc_token);
1294
1295 /* si_get.c */
1296 void si_init_screen_get_functions(struct si_screen *sscreen);
1297
1298 /* si_gfx_cs.c */
1299 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
1300 struct pipe_fence_handle **fence);
1301 void si_begin_new_gfx_cs(struct si_context *ctx);
1302 void si_need_gfx_cs_space(struct si_context *ctx);
1303 void si_unref_sdma_uploads(struct si_context *sctx);
1304
1305 /* si_gpu_load.c */
1306 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1307 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1308 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
1309 uint64_t begin);
1310
1311 /* si_compute.c */
1312 void si_init_compute_functions(struct si_context *sctx);
1313
1314 /* si_perfcounters.c */
1315 void si_init_perfcounters(struct si_screen *screen);
1316 void si_destroy_perfcounters(struct si_screen *screen);
1317
1318 /* si_pipe.c */
1319 bool si_check_device_reset(struct si_context *sctx);
1320
1321 /* si_query.c */
1322 void si_init_screen_query_functions(struct si_screen *sscreen);
1323 void si_init_query_functions(struct si_context *sctx);
1324 void si_suspend_queries(struct si_context *sctx);
1325 void si_resume_queries(struct si_context *sctx);
1326
1327 /* si_shaderlib_tgsi.c */
1328 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1329 unsigned num_layers);
1330 void *si_create_fixed_func_tcs(struct si_context *sctx);
1331 void *si_create_dma_compute_shader(struct pipe_context *ctx,
1332 unsigned num_dwords_per_thread,
1333 bool dst_stream_cache_policy, bool is_copy);
1334 void *si_create_copy_image_compute_shader(struct pipe_context *ctx);
1335 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx);
1336 void *si_clear_render_target_shader(struct pipe_context *ctx);
1337 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
1338 void *si_create_dcc_retile_cs(struct pipe_context *ctx);
1339 void *si_create_query_result_cs(struct si_context *sctx);
1340
1341 /* si_test_dma.c */
1342 void si_test_dma(struct si_screen *sscreen);
1343
1344 /* si_test_clearbuffer.c */
1345 void si_test_dma_perf(struct si_screen *sscreen);
1346
1347 /* si_uvd.c */
1348 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1349 const struct pipe_video_codec *templ);
1350
1351 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1352 const struct pipe_video_buffer *tmpl);
1353
1354 /* si_viewport.c */
1355 void si_update_vs_viewport_state(struct si_context *ctx);
1356 void si_init_viewport_functions(struct si_context *ctx);
1357
1358 /* si_texture.c */
1359 bool si_prepare_for_dma_blit(struct si_context *sctx,
1360 struct si_texture *dst,
1361 unsigned dst_level, unsigned dstx,
1362 unsigned dsty, unsigned dstz,
1363 struct si_texture *src,
1364 unsigned src_level,
1365 const struct pipe_box *src_box);
1366 void si_eliminate_fast_color_clear(struct si_context *sctx,
1367 struct si_texture *tex);
1368 void si_texture_discard_cmask(struct si_screen *sscreen,
1369 struct si_texture *tex);
1370 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1371 struct pipe_resource *texture,
1372 struct si_texture **staging);
1373 void si_print_texture_info(struct si_screen *sscreen,
1374 struct si_texture *tex, struct u_log_context *log);
1375 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1376 const struct pipe_resource *templ);
1377 bool vi_dcc_formats_compatible(enum pipe_format format1,
1378 enum pipe_format format2);
1379 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1380 unsigned level,
1381 enum pipe_format view_format);
1382 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1383 struct pipe_resource *tex,
1384 unsigned level,
1385 enum pipe_format view_format);
1386 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1387 struct pipe_resource *texture,
1388 const struct pipe_surface *templ,
1389 unsigned width0, unsigned height0,
1390 unsigned width, unsigned height);
1391 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1392 void vi_separate_dcc_try_enable(struct si_context *sctx,
1393 struct si_texture *tex);
1394 void vi_separate_dcc_start_query(struct si_context *sctx,
1395 struct si_texture *tex);
1396 void vi_separate_dcc_stop_query(struct si_context *sctx,
1397 struct si_texture *tex);
1398 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1399 struct si_texture *tex);
1400 bool si_texture_disable_dcc(struct si_context *sctx,
1401 struct si_texture *tex);
1402 void si_init_screen_texture_functions(struct si_screen *sscreen);
1403 void si_init_context_texture_functions(struct si_context *sctx);
1404
1405
1406 /*
1407 * common helpers
1408 */
1409
1410 static inline struct si_resource *si_resource(struct pipe_resource *r)
1411 {
1412 return (struct si_resource*)r;
1413 }
1414
1415 static inline void
1416 si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1417 {
1418 pipe_resource_reference((struct pipe_resource **)ptr,
1419 (struct pipe_resource *)res);
1420 }
1421
1422 static inline void
1423 si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1424 {
1425 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1426 }
1427
1428 static inline bool
1429 vi_dcc_enabled(struct si_texture *tex, unsigned level)
1430 {
1431 return tex->dcc_offset && level < tex->surface.num_dcc_levels;
1432 }
1433
1434 static inline unsigned
1435 si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1436 {
1437 if (stencil)
1438 return tex->surface.u.legacy.stencil_tiling_index[level];
1439 else
1440 return tex->surface.u.legacy.tiling_index[level];
1441 }
1442
1443 static inline unsigned
1444 si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx)
1445 {
1446 /* Don't count the needed CS space exactly and just use an upper bound.
1447 *
1448 * Also reserve space for stopping queries at the end of IB, because
1449 * the number of active queries is unlimited in theory.
1450 */
1451 return 2048 + sctx->num_cs_dw_queries_suspend;
1452 }
1453
1454 static inline void
1455 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1456 {
1457 if (r) {
1458 /* Add memory usage for need_gfx_cs_space */
1459 sctx->vram += si_resource(r)->vram_usage;
1460 sctx->gtt += si_resource(r)->gart_usage;
1461 }
1462 }
1463
1464 static inline void
1465 si_invalidate_draw_sh_constants(struct si_context *sctx)
1466 {
1467 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1468 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1469 }
1470
1471 static inline unsigned
1472 si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1473 {
1474 return 1 << (atom - sctx->atoms.array);
1475 }
1476
1477 static inline void
1478 si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1479 {
1480 unsigned bit = si_get_atom_bit(sctx, atom);
1481
1482 if (dirty)
1483 sctx->dirty_atoms |= bit;
1484 else
1485 sctx->dirty_atoms &= ~bit;
1486 }
1487
1488 static inline bool
1489 si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1490 {
1491 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1492 }
1493
1494 static inline void
1495 si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1496 {
1497 si_set_atom_dirty(sctx, atom, true);
1498 }
1499
1500 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1501 {
1502 if (sctx->gs_shader.cso)
1503 return &sctx->gs_shader;
1504 if (sctx->tes_shader.cso)
1505 return &sctx->tes_shader;
1506
1507 return &sctx->vs_shader;
1508 }
1509
1510 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1511 {
1512 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1513
1514 return vs->cso ? &vs->cso->info : NULL;
1515 }
1516
1517 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1518 {
1519 if (sctx->gs_shader.cso)
1520 return sctx->gs_shader.cso->gs_copy_shader;
1521
1522 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1523 return vs->current ? vs->current : NULL;
1524 }
1525
1526 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1527 unsigned processor)
1528 {
1529 return sscreen->debug_flags & (1 << processor);
1530 }
1531
1532 static inline bool si_get_strmout_en(struct si_context *sctx)
1533 {
1534 return sctx->streamout.streamout_enabled ||
1535 sctx->streamout.prims_gen_query_enabled;
1536 }
1537
1538 static inline unsigned
1539 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1540 {
1541 unsigned alignment, tcc_cache_line_size;
1542
1543 /* If the upload size is less than the cache line size (e.g. 16, 32),
1544 * the whole thing will fit into a cache line if we align it to its size.
1545 * The idea is that multiple small uploads can share a cache line.
1546 * If the upload size is greater, align it to the cache line size.
1547 */
1548 alignment = util_next_power_of_two(upload_size);
1549 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1550 return MIN2(alignment, tcc_cache_line_size);
1551 }
1552
1553 static inline void
1554 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1555 {
1556 if (pipe_reference(&(*dst)->reference, &src->reference))
1557 si_destroy_saved_cs(*dst);
1558
1559 *dst = src;
1560 }
1561
1562 static inline void
1563 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1564 bool shaders_read_metadata, bool dcc_pipe_aligned)
1565 {
1566 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1567 SI_CONTEXT_INV_VMEM_L1;
1568
1569 if (sctx->chip_class >= GFX9) {
1570 /* Single-sample color is coherent with shaders on GFX9, but
1571 * L2 metadata must be flushed if shaders read metadata.
1572 * (DCC, CMASK).
1573 */
1574 if (num_samples >= 2 ||
1575 (shaders_read_metadata && !dcc_pipe_aligned))
1576 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1577 else if (shaders_read_metadata)
1578 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1579 } else {
1580 /* SI-CI-VI */
1581 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1582 }
1583 }
1584
1585 static inline void
1586 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1587 bool include_stencil, bool shaders_read_metadata)
1588 {
1589 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1590 SI_CONTEXT_INV_VMEM_L1;
1591
1592 if (sctx->chip_class >= GFX9) {
1593 /* Single-sample depth (not stencil) is coherent with shaders
1594 * on GFX9, but L2 metadata must be flushed if shaders read
1595 * metadata.
1596 */
1597 if (num_samples >= 2 || include_stencil)
1598 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1599 else if (shaders_read_metadata)
1600 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1601 } else {
1602 /* SI-CI-VI */
1603 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1604 }
1605 }
1606
1607 static inline bool
1608 si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1609 {
1610 return (stencil_sampler && tex->can_sample_s) ||
1611 (!stencil_sampler && tex->can_sample_z);
1612 }
1613
1614 static inline bool
1615 si_htile_enabled(struct si_texture *tex, unsigned level)
1616 {
1617 return tex->htile_offset && level == 0;
1618 }
1619
1620 static inline bool
1621 vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level)
1622 {
1623 assert(!tex->tc_compatible_htile || tex->htile_offset);
1624 return tex->tc_compatible_htile && level == 0;
1625 }
1626
1627 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1628 {
1629 if (sctx->ps_uses_fbfetch)
1630 return sctx->framebuffer.nr_color_samples;
1631
1632 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1633 }
1634
1635 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1636 {
1637 if (sctx->queued.named.rasterizer->rasterizer_discard)
1638 return 0;
1639
1640 struct si_shader_selector *ps = sctx->ps_shader.cso;
1641 if (!ps)
1642 return 0;
1643
1644 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1645 sctx->queued.named.blend->cb_target_mask;
1646
1647 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1648 colormask &= ps->colors_written_4bit;
1649 else if (!ps->colors_written_4bit)
1650 colormask = 0; /* color0 writes all cbufs, but it's not written */
1651
1652 return colormask;
1653 }
1654
1655 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1656 (1 << PIPE_PRIM_LINE_LOOP) | \
1657 (1 << PIPE_PRIM_LINE_STRIP) | \
1658 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1659 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1660
1661 static inline bool util_prim_is_lines(unsigned prim)
1662 {
1663 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1664 }
1665
1666 static inline bool util_prim_is_points_or_lines(unsigned prim)
1667 {
1668 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES |
1669 (1 << PIPE_PRIM_POINTS))) != 0;
1670 }
1671
1672 /**
1673 * Return true if there is enough memory in VRAM and GTT for the buffers
1674 * added so far.
1675 *
1676 * \param vram VRAM memory size not added to the buffer list yet
1677 * \param gtt GTT memory size not added to the buffer list yet
1678 */
1679 static inline bool
1680 radeon_cs_memory_below_limit(struct si_screen *screen,
1681 struct radeon_cmdbuf *cs,
1682 uint64_t vram, uint64_t gtt)
1683 {
1684 vram += cs->used_vram;
1685 gtt += cs->used_gart;
1686
1687 /* Anything that goes above the VRAM size should go to GTT. */
1688 if (vram > screen->info.vram_size)
1689 gtt += vram - screen->info.vram_size;
1690
1691 /* Now we just need to check if we have enough GTT. */
1692 return gtt < screen->info.gart_size * 0.7;
1693 }
1694
1695 /**
1696 * Add a buffer to the buffer list for the given command stream (CS).
1697 *
1698 * All buffers used by a CS must be added to the list. This tells the kernel
1699 * driver which buffers are used by GPU commands. Other buffers can
1700 * be swapped out (not accessible) during execution.
1701 *
1702 * The buffer list becomes empty after every context flush and must be
1703 * rebuilt.
1704 */
1705 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1706 struct radeon_cmdbuf *cs,
1707 struct si_resource *bo,
1708 enum radeon_bo_usage usage,
1709 enum radeon_bo_priority priority)
1710 {
1711 assert(usage);
1712 sctx->ws->cs_add_buffer(
1713 cs, bo->buf,
1714 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1715 bo->domains, priority);
1716 }
1717
1718 /**
1719 * Same as above, but also checks memory usage and flushes the context
1720 * accordingly.
1721 *
1722 * When this SHOULD NOT be used:
1723 *
1724 * - if si_context_add_resource_size has been called for the buffer
1725 * followed by *_need_cs_space for checking the memory usage
1726 *
1727 * - if si_need_dma_space has been called for the buffer
1728 *
1729 * - when emitting state packets and draw packets (because preceding packets
1730 * can't be re-emitted at that point)
1731 *
1732 * - if shader resource "enabled_mask" is not up-to-date or there is
1733 * a different constraint disallowing a context flush
1734 */
1735 static inline void
1736 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1737 struct si_resource *bo,
1738 enum radeon_bo_usage usage,
1739 enum radeon_bo_priority priority,
1740 bool check_mem)
1741 {
1742 if (check_mem &&
1743 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1744 sctx->vram + bo->vram_usage,
1745 sctx->gtt + bo->gart_usage))
1746 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1747
1748 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority);
1749 }
1750
1751 #define PRINT_ERR(fmt, args...) \
1752 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1753
1754 #endif