src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef SI_PIPE_H
  27 #define SI_PIPE_H
  28
  29 #include "si_shader.h"
  30
  31 #include "util/u_dynarray.h"
  32 #include "util/u_idalloc.h"
  33
  34 #ifdef PIPE_ARCH_BIG_ENDIAN
  35 #define SI_BIG_ENDIAN 1
  36 #else
  37 #define SI_BIG_ENDIAN 0
  38 #endif
  39
  40 /* The base vertex and primitive restart can be any number, but we must pick
  41  * one which will mean "unknown" for the purpose of state tracking and
  42  * the number shouldn't be a commonly-used one. */
  43 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  44 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  45 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  46 #define SI_GS_PER_ES 128
  47 /* Alignment for optimal CP DMA performance. */
  48 #define SI_CPDMA_ALIGNMENT      32
  49
  50 /* Instruction cache. */
  51 #define SI_CONTEXT_INV_ICACHE           (R600_CONTEXT_PRIVATE_FLAG << 0)
  52 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  53 #define SI_CONTEXT_INV_SMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 1)
  54 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  55 #define SI_CONTEXT_INV_VMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 2)
  56 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  57 #define SI_CONTEXT_INV_GLOBAL_L2        (R600_CONTEXT_PRIVATE_FLAG << 3)
  58 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  59  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
  60 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2  (R600_CONTEXT_PRIVATE_FLAG << 4)
  61 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
  62  * a CB or DB flush. */
  63 #define SI_CONTEXT_INV_L2_METADATA      (R600_CONTEXT_PRIVATE_FLAG << 5)
  64 /* Framebuffer caches. */
  65 #define SI_CONTEXT_FLUSH_AND_INV_DB     (R600_CONTEXT_PRIVATE_FLAG << 6)
  66 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 7)
  67 #define SI_CONTEXT_FLUSH_AND_INV_CB     (R600_CONTEXT_PRIVATE_FLAG << 8)
  68 /* Engine synchronization. */
  69 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 9)
  70 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 10)
  71 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 11)
  72 #define SI_CONTEXT_VGT_FLUSH            (R600_CONTEXT_PRIVATE_FLAG << 12)
  73 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (R600_CONTEXT_PRIVATE_FLAG << 13)
  74
  75 #define SI_PREFETCH_VBO_DESCRIPTORS     (1 << 0)
  76 #define SI_PREFETCH_LS                  (1 << 1)
  77 #define SI_PREFETCH_HS                  (1 << 2)
  78 #define SI_PREFETCH_ES                  (1 << 3)
  79 #define SI_PREFETCH_GS                  (1 << 4)
  80 #define SI_PREFETCH_VS                  (1 << 5)
  81 #define SI_PREFETCH_PS                  (1 << 6)
  82
  83 #define SI_MAX_BORDER_COLORS    4096
  84 #define SIX_BITS                0x3F
  85
  86 struct si_compute;
  87 struct hash_table;
  88 struct u_suballocator;
  89
  90 struct si_screen {
  91         struct r600_common_screen       b;
  92         unsigned                        gs_table_depth;
  93         unsigned                        tess_offchip_block_dw_size;
  94         bool                            has_clear_state;
  95         bool                            has_distributed_tess;
  96         bool                            has_draw_indirect_multi;
  97         bool                            has_out_of_order_rast;
  98         bool                            assume_no_z_fights;
  99         bool                            has_msaa_sample_loc_bug;
 100         bool                            dpbb_allowed;
 101         bool                            dfsm_allowed;
 102         bool                            llvm_has_working_vgpr_indexing;
 103
 104         /* Whether shaders are monolithic (1-part) or separate (3-part). */
 105         bool                            use_monolithic_shaders;
 106         bool                            record_llvm_ir;
 107
 108         mtx_t                   shader_parts_mutex;
 109         struct si_shader_part           *vs_prologs;
 110         struct si_shader_part           *tcs_epilogs;
 111         struct si_shader_part           *gs_prologs;
 112         struct si_shader_part           *ps_prologs;
 113         struct si_shader_part           *ps_epilogs;
 114
 115         /* Shader cache in memory.
 116          *
 117          * Design & limitations:
 118          * - The shader cache is per screen (= per process), never saved to
 119          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 120          * - It can only be used with one-variant-per-shader support, in which
 121          *   case only the main (typically middle) part of shaders is cached.
 122          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 123          *   variants of VS and TES are cached, so LS and ES aren't.
 124          * - GS and CS aren't cached, but it's certainly possible to cache
 125          *   those as well.
 126          */
 127         mtx_t                   shader_cache_mutex;
 128         struct hash_table               *shader_cache;
 129
 130         /* Shader compiler queue for multithreaded compilation. */
 131         struct util_queue               shader_compiler_queue;
 132         /* Use at most 3 normal compiler threads on quadcore and better.
 133          * Hyperthreaded CPUs report the number of threads, but we want
 134          * the number of cores. */
 135         LLVMTargetMachineRef            tm[3]; /* used by the queue only */
 136
 137         struct util_queue               shader_compiler_queue_low_priority;
 138         /* Use at most 2 low priority threads on quadcore and better.
 139          * We want to minimize the impact on multithreaded Mesa. */
 140         LLVMTargetMachineRef            tm_low_priority[2]; /* at most 2 threads */
 141 };
 142
 143 struct si_blend_color {
 144         struct r600_atom                atom;
 145         struct pipe_blend_color         state;
 146         bool                            any_nonzeros;
 147 };
 148
 149 struct si_sampler_view {
 150         struct pipe_sampler_view        base;
 151         /* [0..7] = image descriptor
 152          * [4..7] = buffer descriptor */
 153         uint32_t                        state[8];
 154         uint32_t                        fmask_state[8];
 155         const struct legacy_surf_level  *base_level_info;
 156         ubyte                           base_level;
 157         ubyte                           block_width;
 158         bool is_stencil_sampler;
 159         bool dcc_incompatible;
 160 };
 161
 162 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
 163
 164 struct si_sampler_state {
 165 #ifdef DEBUG
 166         unsigned                        magic;
 167 #endif
 168         uint32_t                        val[4];
 169 };
 170
 171 struct si_cs_shader_state {
 172         struct si_compute               *program;
 173         struct si_compute               *emitted_program;
 174         unsigned                        offset;
 175         bool                            initialized;
 176         bool                            uses_scratch;
 177 };
 178
 179 struct si_textures_info {
 180         struct si_sampler_views         views;
 181         uint32_t                        needs_depth_decompress_mask;
 182         uint32_t                        needs_color_decompress_mask;
 183 };
 184
 185 struct si_images_info {
 186         struct pipe_image_view          views[SI_NUM_IMAGES];
 187         uint32_t                        needs_color_decompress_mask;
 188         unsigned                        enabled_mask;
 189 };
 190
 191 struct si_framebuffer {
 192         struct r600_atom                atom;
 193         struct pipe_framebuffer_state   state;
 194         unsigned                        colorbuf_enabled_4bit;
 195         unsigned                        spi_shader_col_format;
 196         unsigned                        spi_shader_col_format_alpha;
 197         unsigned                        spi_shader_col_format_blend;
 198         unsigned                        spi_shader_col_format_blend_alpha;
 199         ubyte                           nr_samples:5; /* at most 16xAA */
 200         ubyte                           log_samples:3; /* at most 4 = 16xAA */
 201         ubyte                           compressed_cb_mask;
 202         ubyte                           color_is_int8;
 203         ubyte                           color_is_int10;
 204         ubyte                           dirty_cbufs;
 205         bool                            dirty_zsbuf;
 206         bool                            any_dst_linear;
 207         bool                            CB_has_shader_readable_metadata;
 208         bool                            DB_has_shader_readable_metadata;
 209 };
 210
 211 struct si_clip_state {
 212         struct r600_atom                atom;
 213         struct pipe_clip_state          state;
 214         bool                            any_nonzeros;
 215 };
 216
 217 struct si_sample_locs {
 218         struct r600_atom        atom;
 219         unsigned                nr_samples;
 220 };
 221
 222 struct si_sample_mask {
 223         struct r600_atom        atom;
 224         uint16_t                sample_mask;
 225 };
 226
 227 /* A shader state consists of the shader selector, which is a constant state
 228  * object shared by multiple contexts and shouldn't be modified, and
 229  * the current shader variant selected for this context.
 230  */
 231 struct si_shader_ctx_state {
 232         struct si_shader_selector       *cso;
 233         struct si_shader                *current;
 234 };
 235
 236 #define SI_NUM_VGT_PARAM_KEY_BITS 12
 237 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
 238
 239 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
 240  * Some fields are set by state-change calls, most are set by draw_vbo.
 241  */
 242 union si_vgt_param_key {
 243         struct {
 244                 unsigned prim:4;
 245                 unsigned uses_instancing:1;
 246                 unsigned multi_instances_smaller_than_primgroup:1;
 247                 unsigned primitive_restart:1;
 248                 unsigned count_from_stream_output:1;
 249                 unsigned line_stipple_enabled:1;
 250                 unsigned uses_tess:1;
 251                 unsigned tess_uses_prim_id:1;
 252                 unsigned uses_gs:1;
 253                 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
 254         } u;
 255         uint32_t index;
 256 };
 257
 258 struct si_texture_handle
 259 {
 260         unsigned                        desc_slot;
 261         bool                            desc_dirty;
 262         struct pipe_sampler_view        *view;
 263         struct si_sampler_state         sstate;
 264 };
 265
 266 struct si_image_handle
 267 {
 268         unsigned                        desc_slot;
 269         bool                            desc_dirty;
 270         struct pipe_image_view          view;
 271 };
 272
 273 struct si_saved_cs {
 274         struct pipe_reference   reference;
 275         struct si_context       *ctx;
 276         struct radeon_saved_cs  gfx;
 277         struct r600_resource    *trace_buf;
 278         unsigned                trace_id;
 279
 280         unsigned                gfx_last_dw;
 281         bool                    flushed;
 282 };
 283
 284 struct si_context {
 285         struct r600_common_context      b;
 286         struct blitter_context          *blitter;
 287         void                            *custom_dsa_flush;
 288         void                            *custom_blend_resolve;
 289         void                            *custom_blend_fmask_decompress;
 290         void                            *custom_blend_eliminate_fastclear;
 291         void                            *custom_blend_dcc_decompress;
 292         struct si_screen                *screen;
 293         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 294         struct si_shader_ctx_state      fixed_func_tcs_shader;
 295         struct r600_resource            *wait_mem_scratch;
 296         unsigned                        wait_mem_number;
 297         uint16_t                        prefetch_L2_mask;
 298
 299         bool                            gfx_flush_in_progress:1;
 300         bool                            compute_is_busy:1;
 301
 302         /* Atoms (direct states). */
 303         union si_state_atoms            atoms;
 304         unsigned                        dirty_atoms; /* mask */
 305         /* PM4 states (precomputed immutable states) */
 306         unsigned                        dirty_states;
 307         union si_state                  queued;
 308         union si_state                  emitted;
 309
 310         /* Atom declarations. */
 311         struct si_framebuffer           framebuffer;
 312         struct si_sample_locs           msaa_sample_locs;
 313         struct r600_atom                db_render_state;
 314         struct r600_atom                dpbb_state;
 315         struct r600_atom                msaa_config;
 316         struct si_sample_mask           sample_mask;
 317         struct r600_atom                cb_render_state;
 318         unsigned                        last_cb_target_mask;
 319         struct si_blend_color           blend_color;
 320         struct r600_atom                clip_regs;
 321         struct si_clip_state            clip_state;
 322         struct si_shader_data           shader_pointers;
 323         struct si_stencil_ref           stencil_ref;
 324         struct r600_atom                spi_map;
 325
 326         /* Precomputed states. */
 327         struct si_pm4_state             *init_config;
 328         struct si_pm4_state             *init_config_gs_rings;
 329         bool                            init_config_has_vgt_flush;
 330         struct si_pm4_state             *vgt_shader_config[4];
 331
 332         /* shaders */
 333         struct si_shader_ctx_state      ps_shader;
 334         struct si_shader_ctx_state      gs_shader;
 335         struct si_shader_ctx_state      vs_shader;
 336         struct si_shader_ctx_state      tcs_shader;
 337         struct si_shader_ctx_state      tes_shader;
 338         struct si_cs_shader_state       cs_shader_state;
 339
 340         /* shader information */
 341         struct si_vertex_elements       *vertex_elements;
 342         unsigned                        sprite_coord_enable;
 343         bool                            flatshade;
 344         bool                            do_update_shaders;
 345
 346         /* shader descriptors */
 347         struct si_descriptors           vertex_buffers;
 348         struct si_descriptors           descriptors[SI_NUM_DESCS];
 349         unsigned                        descriptors_dirty;
 350         unsigned                        shader_pointers_dirty;
 351         unsigned                        shader_needs_decompress_mask;
 352         struct si_buffer_resources      rw_buffers;
 353         struct si_buffer_resources      const_and_shader_buffers[SI_NUM_SHADERS];
 354         struct si_textures_info         samplers[SI_NUM_SHADERS];
 355         struct si_images_info           images[SI_NUM_SHADERS];
 356
 357         /* other shader resources */
 358         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 359         struct pipe_resource            *esgs_ring;
 360         struct pipe_resource            *gsvs_ring;
 361         struct pipe_resource            *tf_ring;
 362         struct pipe_resource            *tess_offchip_ring;
 363         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 364         struct r600_resource            *border_color_buffer;
 365         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 366         unsigned                        border_color_count;
 367
 368         /* Vertex and index buffers. */
 369         bool                            vertex_buffers_dirty;
 370         bool                            vertex_buffer_pointer_dirty;
 371         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 372
 373         /* MSAA config state. */
 374         int                             ps_iter_samples;
 375         bool                            smoothing_enabled;
 376
 377         /* DB render state. */
 378         unsigned                ps_db_shader_control;
 379         unsigned                dbcb_copy_sample;
 380         bool                    dbcb_depth_copy_enabled:1;
 381         bool                    dbcb_stencil_copy_enabled:1;
 382         bool                    db_flush_depth_inplace:1;
 383         bool                    db_flush_stencil_inplace:1;
 384         bool                    db_depth_clear:1;
 385         bool                    db_depth_disable_expclear:1;
 386         bool                    db_stencil_clear:1;
 387         bool                    db_stencil_disable_expclear:1;
 388         bool                    occlusion_queries_disabled:1;
 389         bool                    generate_mipmap_for_depth:1;
 390
 391         /* Emitted draw state. */
 392         bool                    gs_tri_strip_adj_fix:1;
 393         bool                    ls_vgpr_fix:1;
 394         int                     last_index_size;
 395         int                     last_base_vertex;
 396         int                     last_start_instance;
 397         int                     last_drawid;
 398         int                     last_sh_base_reg;
 399         int                     last_primitive_restart_en;
 400         int                     last_restart_index;
 401         int                     last_gs_out_prim;
 402         int                     last_prim;
 403         int                     last_multi_vgt_param;
 404         int                     last_rast_prim;
 405         unsigned                last_sc_line_stipple;
 406         unsigned                current_vs_state;
 407         unsigned                last_vs_state;
 408         enum pipe_prim_type     current_rast_prim; /* primitive type after TES, GS */
 409
 410         /* Scratch buffer */
 411         struct r600_atom        scratch_state;
 412         struct r600_resource    *scratch_buffer;
 413         unsigned                scratch_waves;
 414         unsigned                spi_tmpring_size;
 415
 416         struct r600_resource    *compute_scratch_buffer;
 417
 418         /* Emitted derived tessellation state. */
 419         /* Local shader (VS), or HS if LS-HS are merged. */
 420         struct si_shader        *last_ls;
 421         struct si_shader_selector *last_tcs;
 422         int                     last_num_tcs_input_cp;
 423         int                     last_tes_sh_base;
 424         bool                    last_tess_uses_primid;
 425         unsigned                last_num_patches;
 426
 427         /* Debug state. */
 428         bool                    is_debug;
 429         struct si_saved_cs      *current_saved_cs;
 430         uint64_t                dmesg_timestamp;
 431         unsigned                apitrace_call_number;
 432
 433         /* Other state */
 434         bool need_check_render_feedback;
 435         bool                    decompression_enabled;
 436
 437         /* Precomputed IA_MULTI_VGT_PARAM */
 438         union si_vgt_param_key  ia_multi_vgt_param_key;
 439         unsigned                ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
 440
 441         /* Bindless descriptors. */
 442         struct si_descriptors   bindless_descriptors;
 443         struct util_idalloc     bindless_used_slots;
 444         unsigned                num_bindless_descriptors;
 445         bool                    bindless_descriptors_dirty;
 446         bool                    graphics_bindless_pointer_dirty;
 447         bool                    compute_bindless_pointer_dirty;
 448
 449         /* Allocated bindless handles */
 450         struct hash_table       *tex_handles;
 451         struct hash_table       *img_handles;
 452
 453         /* Resident bindless handles */
 454         struct util_dynarray    resident_tex_handles;
 455         struct util_dynarray    resident_img_handles;
 456
 457         /* Resident bindless handles which need decompression */
 458         struct util_dynarray    resident_tex_needs_color_decompress;
 459         struct util_dynarray    resident_img_needs_color_decompress;
 460         struct util_dynarray    resident_tex_needs_depth_decompress;
 461
 462         /* Bindless state */
 463         bool                    uses_bindless_samplers;
 464         bool                    uses_bindless_images;
 465 };
 466
 467 /* cik_sdma.c */
 468 void cik_init_sdma_functions(struct si_context *sctx);
 469
 470 /* si_blit.c */
 471 void si_init_blit_functions(struct si_context *sctx);
 472 void si_decompress_graphics_textures(struct si_context *sctx);
 473 void si_decompress_compute_textures(struct si_context *sctx);
 474 void si_resource_copy_region(struct pipe_context *ctx,
 475                              struct pipe_resource *dst,
 476                              unsigned dst_level,
 477                              unsigned dstx, unsigned dsty, unsigned dstz,
 478                              struct pipe_resource *src,
 479                              unsigned src_level,
 480                              const struct pipe_box *src_box);
 481
 482 /* si_cp_dma.c */
 483 #define SI_CPDMA_SKIP_CHECK_CS_SPACE    (1 << 0) /* don't call need_cs_space */
 484 #define SI_CPDMA_SKIP_SYNC_AFTER        (1 << 1) /* don't wait for DMA after the copy */
 485 #define SI_CPDMA_SKIP_SYNC_BEFORE       (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
 486 #define SI_CPDMA_SKIP_GFX_SYNC          (1 << 3) /* don't flush caches and don't wait for PS/CS */
 487 #define SI_CPDMA_SKIP_BO_LIST_UPDATE    (1 << 4) /* don't update the BO list */
 488 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
 489                            SI_CPDMA_SKIP_SYNC_AFTER | \
 490                            SI_CPDMA_SKIP_SYNC_BEFORE | \
 491                            SI_CPDMA_SKIP_GFX_SYNC | \
 492                            SI_CPDMA_SKIP_BO_LIST_UPDATE)
 493
 494 void si_copy_buffer(struct si_context *sctx,
 495                     struct pipe_resource *dst, struct pipe_resource *src,
 496                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 497                     unsigned user_flags);
 498 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 499                               uint64_t offset, unsigned size);
 500 void cik_emit_prefetch_L2(struct si_context *sctx);
 501 void si_init_cp_dma_functions(struct si_context *sctx);
 502
 503 /* si_debug.c */
 504 void si_auto_log_cs(void *data, struct u_log_context *log);
 505 void si_log_hw_flush(struct si_context *sctx);
 506 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
 507 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
 508 void si_init_debug_functions(struct si_context *sctx);
 509 void si_check_vm_faults(struct r600_common_context *ctx,
 510                         struct radeon_saved_cs *saved, enum ring_type ring);
 511 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
 512
 513 /* si_dma.c */
 514 void si_init_dma_functions(struct si_context *sctx);
 515
 516 /* si_hw_context.c */
 517 void si_destroy_saved_cs(struct si_saved_cs *scs);
 518 void si_context_gfx_flush(void *context, unsigned flags,
 519                           struct pipe_fence_handle **fence);
 520 void si_begin_new_cs(struct si_context *ctx);
 521 void si_need_cs_space(struct si_context *ctx);
 522
 523 /* si_compute.c */
 524 void si_init_compute_functions(struct si_context *sctx);
 525
 526 /* si_perfcounters.c */
 527 void si_init_perfcounters(struct si_screen *screen);
 528
 529 /* si_uvd.c */
 530 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 531                                                const struct pipe_video_codec *templ);
 532
 533 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 534                                                  const struct pipe_video_buffer *tmpl);
 535
 536 /*
 537  * common helpers
 538  */
 539
 540 static inline void
 541 si_invalidate_draw_sh_constants(struct si_context *sctx)
 542 {
 543         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 544 }
 545
 546 static inline void
 547 si_set_atom_dirty(struct si_context *sctx,
 548                   struct r600_atom *atom, bool dirty)
 549 {
 550         unsigned bit = 1 << atom->id;
 551
 552         if (dirty)
 553                 sctx->dirty_atoms |= bit;
 554         else
 555                 sctx->dirty_atoms &= ~bit;
 556 }
 557
 558 static inline bool
 559 si_is_atom_dirty(struct si_context *sctx,
 560                   struct r600_atom *atom)
 561 {
 562         unsigned bit = 1 << atom->id;
 563
 564         return sctx->dirty_atoms & bit;
 565 }
 566
 567 static inline void
 568 si_mark_atom_dirty(struct si_context *sctx,
 569                    struct r600_atom *atom)
 570 {
 571         si_set_atom_dirty(sctx, atom, true);
 572 }
 573
 574 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
 575 {
 576         if (sctx->gs_shader.cso)
 577                 return &sctx->gs_shader;
 578         if (sctx->tes_shader.cso)
 579                 return &sctx->tes_shader;
 580
 581         return &sctx->vs_shader;
 582 }
 583
 584 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 585 {
 586         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 587
 588         return vs->cso ? &vs->cso->info : NULL;
 589 }
 590
 591 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 592 {
 593         if (sctx->gs_shader.cso)
 594                 return sctx->gs_shader.cso->gs_copy_shader;
 595
 596         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 597         return vs->current ? vs->current : NULL;
 598 }
 599
 600 static inline unsigned
 601 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
 602 {
 603         unsigned alignment, tcc_cache_line_size;
 604
 605         /* If the upload size is less than the cache line size (e.g. 16, 32),
 606          * the whole thing will fit into a cache line if we align it to its size.
 607          * The idea is that multiple small uploads can share a cache line.
 608          * If the upload size is greater, align it to the cache line size.
 609          */
 610         alignment = util_next_power_of_two(upload_size);
 611         tcc_cache_line_size = sctx->screen->b.info.tcc_cache_line_size;
 612         return MIN2(alignment, tcc_cache_line_size);
 613 }
 614
 615 static inline void
 616 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
 617 {
 618         if (pipe_reference(&(*dst)->reference, &src->reference))
 619                 si_destroy_saved_cs(*dst);
 620
 621         *dst = src;
 622 }
 623
 624 static inline void
 625 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 626                            bool shaders_read_metadata)
 627 {
 628         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
 629                          SI_CONTEXT_INV_VMEM_L1;
 630
 631         if (sctx->b.chip_class >= GFX9) {
 632                 /* Single-sample color is coherent with shaders on GFX9, but
 633                  * L2 metadata must be flushed if shaders read metadata.
 634                  * (DCC, CMASK).
 635                  */
 636                 if (num_samples >= 2)
 637                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 638                 else if (shaders_read_metadata)
 639                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 640         } else {
 641                 /* SI-CI-VI */
 642                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 643         }
 644 }
 645
 646 static inline void
 647 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 648                            bool include_stencil, bool shaders_read_metadata)
 649 {
 650         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
 651                          SI_CONTEXT_INV_VMEM_L1;
 652
 653         if (sctx->b.chip_class >= GFX9) {
 654                 /* Single-sample depth (not stencil) is coherent with shaders
 655                  * on GFX9, but L2 metadata must be flushed if shaders read
 656                  * metadata.
 657                  */
 658                 if (num_samples >= 2 || include_stencil)
 659                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 660                 else if (shaders_read_metadata)
 661                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 662         } else {
 663                 /* SI-CI-VI */
 664                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 665         }
 666 }
 667
 668 #endif