2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "si_shader.h"
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
38 #define SI_BIG_ENDIAN 0
41 #define ATI_VENDOR_ID 0x1002
43 #define SI_NOT_QUERY 0xffffffff
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
69 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
70 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
71 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
72 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
73 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
74 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
75 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
76 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
77 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
78 * a CB or DB flush. */
79 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
80 /* Framebuffer caches. */
81 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
82 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
83 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
84 /* Engine synchronization. */
85 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
86 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
87 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
88 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
89 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
91 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
92 #define SI_PREFETCH_LS (1 << 1)
93 #define SI_PREFETCH_HS (1 << 2)
94 #define SI_PREFETCH_ES (1 << 3)
95 #define SI_PREFETCH_GS (1 << 4)
96 #define SI_PREFETCH_VS (1 << 5)
97 #define SI_PREFETCH_PS (1 << 6)
99 #define SI_MAX_BORDER_COLORS 4096
100 #define SI_MAX_VIEWPORTS 16
101 #define SIX_BITS 0x3F
102 #define SI_MAP_BUFFER_ALIGNMENT 64
103 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
105 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
106 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
107 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
108 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
109 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
110 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
111 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
112 #define SI_RESOURCE_FLAG_SO_FILLED_SIZE (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
116 /* Shader logging options: */
117 DBG_VS
= PIPE_SHADER_VERTEX
,
118 DBG_PS
= PIPE_SHADER_FRAGMENT
,
119 DBG_GS
= PIPE_SHADER_GEOMETRY
,
120 DBG_TCS
= PIPE_SHADER_TESS_CTRL
,
121 DBG_TES
= PIPE_SHADER_TESS_EVAL
,
122 DBG_CS
= PIPE_SHADER_COMPUTE
,
128 /* Shader compiler options the shader cache should be aware of: */
129 DBG_FS_CORRECT_DERIVS_AFTER_KILL
,
134 /* Shader compiler options (with no effect on the shader cache): */
137 DBG_MONOLITHIC_SHADERS
,
140 /* Information logging options: */
146 /* Driver options: */
154 /* 3D engine options: */
174 DBG_TEST_VMFAULT_SDMA
,
175 DBG_TEST_VMFAULT_SHADER
,
182 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
183 #define DBG(name) (1ull << DBG_##name)
185 enum si_cache_policy
{
187 L2_STREAM
, /* same as SLC=1 */
188 L2_LRU
, /* same as SLC=0 */
192 SI_COHERENCY_NONE
, /* no cache flushes needed */
194 SI_COHERENCY_CB_META
,
200 struct u_suballocator
;
202 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
205 struct r600_resource
{
206 struct threaded_resource b
;
208 /* Winsys objects. */
209 struct pb_buffer
*buf
;
210 uint64_t gpu_address
;
211 /* Memory usage if the buffer placement is optimal. */
215 /* Resource properties. */
217 unsigned bo_alignment
;
218 enum radeon_bo_domain domains
;
219 enum radeon_bo_flag flags
;
220 unsigned bind_history
;
221 int max_forced_staging_uploads
;
223 /* The buffer range which is initialized (with a write transfer,
224 * streamout, DMA, or as a random access target). The rest of
225 * the buffer is considered invalid and can be mapped unsynchronized.
227 * This allows unsychronized mapping of a buffer range which hasn't
228 * been used yet. It's for applications which forget to use
229 * the unsynchronized map flag and expect the driver to figure it out.
231 struct util_range valid_buffer_range
;
233 /* For buffers only. This indicates that a write operation has been
234 * performed by TC L2, but the cache hasn't been flushed.
235 * Any hw block which doesn't use or bypasses TC L2 should check this
236 * flag and flush the cache before using the buffer.
238 * For example, TC L2 must be flushed if a buffer which has been
239 * modified by a shader store instruction is about to be used as
240 * an index buffer. The reason is that VGT DMA index fetching doesn't
245 /* Whether this resource is referenced by bindless handles. */
246 bool texture_handle_allocated
;
247 bool image_handle_allocated
;
249 /* Whether the resource has been exported via resource_get_handle. */
250 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
254 struct threaded_transfer b
;
255 struct r600_resource
*staging
;
260 struct r600_resource buffer
;
262 struct radeon_surf surface
;
264 struct si_texture
*flushed_depth_texture
;
266 /* Colorbuffer compression and fast clear. */
267 uint64_t fmask_offset
;
268 uint64_t cmask_offset
;
269 uint64_t cmask_base_address_reg
;
270 struct r600_resource
*cmask_buffer
;
271 uint64_t dcc_offset
; /* 0 = disabled */
272 unsigned cb_color_info
; /* fast clear enable bit */
273 unsigned color_clear_value
[2];
274 unsigned last_msaa_resolve_target_micro_mode
;
275 unsigned num_level0_transfers
;
277 /* Depth buffer compression and fast clear. */
278 uint64_t htile_offset
;
279 float depth_clear_value
;
280 uint16_t dirty_level_mask
; /* each bit says if that mipmap is compressed */
281 uint16_t stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
282 enum pipe_format db_render_format
:16;
283 uint8_t stencil_clear_value
;
284 bool tc_compatible_htile
:1;
285 bool depth_cleared
:1; /* if it was cleared at least once */
286 bool stencil_cleared
:1; /* if it was cleared at least once */
287 bool upgraded_depth
:1; /* upgraded from unorm to Z32_FLOAT */
289 bool db_compatible
:1;
293 /* We need to track DCC dirtiness, because st/dri usually calls
294 * flush_resource twice per frame (not a bug) and we don't wanna
295 * decompress DCC twice. Also, the dirty tracking must be done even
296 * if DCC isn't used, because it's required by the DCC usage analysis
297 * for a possible future enablement.
299 bool separate_dcc_dirty
:1;
300 /* Statistics gathering for the DCC enablement heuristic. */
301 bool dcc_gather_statistics
:1;
302 /* Counter that should be non-zero if the texture is bound to a
305 unsigned framebuffers_bound
;
306 /* Whether the texture is a displayable back buffer and needs DCC
307 * decompression, which is expensive. Therefore, it's enabled only
308 * if statistics suggest that it will pay off and it's allocated
309 * separately. It can't be bound as a sampler by apps. Limited to
310 * target == 2D and last_level == 0. If enabled, dcc_offset contains
311 * the absolute GPUVM address, not the relative one.
313 struct r600_resource
*dcc_separate_buffer
;
314 /* When DCC is temporarily disabled, the separate buffer is here. */
315 struct r600_resource
*last_dcc_separate_buffer
;
316 /* Estimate of how much this color buffer is written to in units of
317 * full-screen draws: ps_invocations / (width * height)
318 * Shader kills, late Z, and blending with trivial discards make it
319 * inaccurate (we need to count CB updates, not PS invocations).
321 unsigned ps_draw_ratio
;
322 /* The number of clears since the last DCC usage analysis. */
323 unsigned num_slow_clears
;
327 struct pipe_surface base
;
329 /* These can vary with block-compressed textures. */
333 bool color_initialized
:1;
334 bool depth_initialized
:1;
336 /* Misc. color flags. */
337 bool color_is_int8
:1;
338 bool color_is_int10
:1;
339 bool dcc_incompatible
:1;
341 /* Color registers. */
342 unsigned cb_color_info
;
343 unsigned cb_color_view
;
344 unsigned cb_color_attrib
;
345 unsigned cb_color_attrib2
; /* GFX9 and later */
346 unsigned cb_dcc_control
; /* VI and later */
347 unsigned spi_shader_col_format
:8; /* no blending, no alpha-to-coverage. */
348 unsigned spi_shader_col_format_alpha
:8; /* alpha-to-coverage */
349 unsigned spi_shader_col_format_blend
:8; /* blending without alpha. */
350 unsigned spi_shader_col_format_blend_alpha
:8; /* blending with alpha. */
353 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE */
354 uint64_t db_stencil_base
;
355 uint64_t db_htile_data_base
;
356 unsigned db_depth_info
;
358 unsigned db_z_info2
; /* GFX9+ */
359 unsigned db_depth_view
;
360 unsigned db_depth_size
;
361 unsigned db_depth_slice
;
362 unsigned db_stencil_info
;
363 unsigned db_stencil_info2
; /* GFX9+ */
364 unsigned db_htile_surface
;
367 struct si_mmio_counter
{
372 union si_mmio_counters
{
374 /* For global GPU load including SDMA. */
375 struct si_mmio_counter gpu
;
378 struct si_mmio_counter spi
;
379 struct si_mmio_counter gui
;
380 struct si_mmio_counter ta
;
381 struct si_mmio_counter gds
;
382 struct si_mmio_counter vgt
;
383 struct si_mmio_counter ia
;
384 struct si_mmio_counter sx
;
385 struct si_mmio_counter wd
;
386 struct si_mmio_counter bci
;
387 struct si_mmio_counter sc
;
388 struct si_mmio_counter pa
;
389 struct si_mmio_counter db
;
390 struct si_mmio_counter cp
;
391 struct si_mmio_counter cb
;
394 struct si_mmio_counter sdma
;
397 struct si_mmio_counter pfp
;
398 struct si_mmio_counter meq
;
399 struct si_mmio_counter me
;
400 struct si_mmio_counter surf_sync
;
401 struct si_mmio_counter cp_dma
;
402 struct si_mmio_counter scratch_ram
;
407 struct si_memory_object
{
408 struct pipe_memory_object b
;
409 struct pb_buffer
*buf
;
413 /* Saved CS data for debugging features. */
414 struct radeon_saved_cs
{
418 struct radeon_bo_list_item
*bo_list
;
423 struct pipe_screen b
;
424 struct radeon_winsys
*ws
;
425 struct disk_cache
*disk_shader_cache
;
427 struct radeon_info info
;
428 uint64_t debug_flags
;
429 char renderer_string
[183];
431 unsigned pa_sc_raster_config
;
432 unsigned pa_sc_raster_config_1
;
433 unsigned se_tile_repeat
;
434 unsigned gs_table_depth
;
435 unsigned tess_offchip_block_dw_size
;
436 unsigned tess_offchip_ring_size
;
437 unsigned tess_factor_ring_size
;
438 unsigned vgt_hs_offchip_param
;
439 unsigned eqaa_force_coverage_samples
;
440 unsigned eqaa_force_z_samples
;
441 unsigned eqaa_force_color_samples
;
442 bool has_clear_state
;
443 bool has_distributed_tess
;
444 bool has_draw_indirect_multi
;
445 bool has_out_of_order_rast
;
446 bool assume_no_z_fights
;
447 bool commutative_blend_add
;
448 bool clear_db_cache_before_clear
;
449 bool has_msaa_sample_loc_bug
;
450 bool has_ls_vgpr_init_bug
;
451 bool has_dcc_constant_encode
;
454 bool llvm_has_working_vgpr_indexing
;
456 /* Whether shaders are monolithic (1-part) or separate (3-part). */
457 bool use_monolithic_shaders
;
459 bool has_rbplus
; /* if RB+ registers exist */
460 bool rbplus_allowed
; /* if RB+ is allowed */
461 bool dcc_msaa_allowed
;
462 bool cpdma_prefetch_writes_memory
;
464 struct slab_parent_pool pool_transfers
;
466 /* Texture filter settings. */
467 int force_aniso
; /* -1 = disabled */
469 /* Auxiliary context. Mainly used to initialize resources.
470 * It must be locked prior to using and flushed before unlocking. */
471 struct pipe_context
*aux_context
;
472 mtx_t aux_context_lock
;
474 /* This must be in the screen, because UE4 uses one context for
475 * compilation and another one for rendering.
477 unsigned num_compilations
;
478 /* Along with ST_DEBUG=precompile, this should show if applications
479 * are loading shaders on demand. This is a monotonic counter.
481 unsigned num_shaders_created
;
482 unsigned num_shader_cache_hits
;
484 /* GPU load thread. */
485 mtx_t gpu_load_mutex
;
486 thrd_t gpu_load_thread
;
487 union si_mmio_counters mmio_counters
;
488 volatile unsigned gpu_load_stop_thread
; /* bool */
490 /* Performance counters. */
491 struct si_perfcounters
*perfcounters
;
493 /* If pipe_screen wants to recompute and re-emit the framebuffer,
494 * sampler, and image states of all contexts, it should atomically
497 * Each context will compare this with its own last known value of
498 * the counter before drawing and re-emit the states accordingly.
500 unsigned dirty_tex_counter
;
502 /* Atomically increment this counter when an existing texture's
503 * metadata is enabled or disabled in a way that requires changing
504 * contexts' compressed texture binding masks.
506 unsigned compressed_colortex_counter
;
509 /* Context flags to set so that all writes from earlier jobs
510 * in the CP are seen by L2 clients.
514 /* Context flags to set so that all writes from earlier jobs
515 * that end in L2 are seen by CP.
520 mtx_t shader_parts_mutex
;
521 struct si_shader_part
*vs_prologs
;
522 struct si_shader_part
*tcs_epilogs
;
523 struct si_shader_part
*gs_prologs
;
524 struct si_shader_part
*ps_prologs
;
525 struct si_shader_part
*ps_epilogs
;
527 /* Shader cache in memory.
529 * Design & limitations:
530 * - The shader cache is per screen (= per process), never saved to
531 * disk, and skips redundant shader compilations from TGSI to bytecode.
532 * - It can only be used with one-variant-per-shader support, in which
533 * case only the main (typically middle) part of shaders is cached.
534 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
535 * variants of VS and TES are cached, so LS and ES aren't.
536 * - GS and CS aren't cached, but it's certainly possible to cache
539 mtx_t shader_cache_mutex
;
540 struct hash_table
*shader_cache
;
542 /* Shader compiler queue for multithreaded compilation. */
543 struct util_queue shader_compiler_queue
;
544 /* Use at most 3 normal compiler threads on quadcore and better.
545 * Hyperthreaded CPUs report the number of threads, but we want
546 * the number of cores. We only need this many threads for shader-db. */
547 struct ac_llvm_compiler compiler
[24]; /* used by the queue only */
549 struct util_queue shader_compiler_queue_low_priority
;
550 /* Use at most 2 low priority threads on quadcore and better.
551 * We want to minimize the impact on multithreaded Mesa. */
552 struct ac_llvm_compiler compiler_lowp
[10];
555 struct si_blend_color
{
556 struct pipe_blend_color state
;
560 struct si_sampler_view
{
561 struct pipe_sampler_view base
;
562 /* [0..7] = image descriptor
563 * [4..7] = buffer descriptor */
565 uint32_t fmask_state
[8];
566 const struct legacy_surf_level
*base_level_info
;
569 bool is_stencil_sampler
;
571 bool dcc_incompatible
;
574 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
576 struct si_sampler_state
{
581 uint32_t integer_val
[4];
582 uint32_t upgraded_depth_val
[4];
585 struct si_cs_shader_state
{
586 struct si_compute
*program
;
587 struct si_compute
*emitted_program
;
594 struct pipe_sampler_view
*views
[SI_NUM_SAMPLERS
];
595 struct si_sampler_state
*sampler_states
[SI_NUM_SAMPLERS
];
597 /* The i-th bit is set if that element is enabled (non-NULL resource). */
598 unsigned enabled_mask
;
599 uint32_t needs_depth_decompress_mask
;
600 uint32_t needs_color_decompress_mask
;
604 struct pipe_image_view views
[SI_NUM_IMAGES
];
605 uint32_t needs_color_decompress_mask
;
606 unsigned enabled_mask
;
609 struct si_framebuffer
{
610 struct pipe_framebuffer_state state
;
611 unsigned colorbuf_enabled_4bit
;
612 unsigned spi_shader_col_format
;
613 unsigned spi_shader_col_format_alpha
;
614 unsigned spi_shader_col_format_blend
;
615 unsigned spi_shader_col_format_blend_alpha
;
616 ubyte nr_samples
:5; /* at most 16xAA */
617 ubyte log_samples
:3; /* at most 4 = 16xAA */
618 ubyte nr_color_samples
; /* at most 8xAA */
619 ubyte compressed_cb_mask
;
620 ubyte uncompressed_cb_mask
;
622 ubyte color_is_int10
;
624 ubyte dcc_overwrite_combiner_watermark
;
627 bool CB_has_shader_readable_metadata
;
628 bool DB_has_shader_readable_metadata
;
632 /* This is the list we want to support. */
633 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH
,
634 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH
,
635 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH
,
638 struct si_signed_scissor
{
643 enum si_quant_mode quant_mode
;
648 struct pipe_scissor_state states
[SI_MAX_VIEWPORTS
];
651 struct si_viewports
{
653 unsigned depth_range_dirty_mask
;
654 struct pipe_viewport_state states
[SI_MAX_VIEWPORTS
];
655 struct si_signed_scissor as_scissor
[SI_MAX_VIEWPORTS
];
658 struct si_clip_state
{
659 struct pipe_clip_state state
;
663 struct si_streamout_target
{
664 struct pipe_stream_output_target b
;
666 /* The buffer where BUFFER_FILLED_SIZE is stored. */
667 struct r600_resource
*buf_filled_size
;
668 unsigned buf_filled_size_offset
;
669 bool buf_filled_size_valid
;
671 unsigned stride_in_dw
;
674 struct si_streamout
{
677 unsigned enabled_mask
;
678 unsigned num_targets
;
679 struct si_streamout_target
*targets
[PIPE_MAX_SO_BUFFERS
];
681 unsigned append_bitmask
;
684 /* External state which comes from the vertex shader,
685 * it must be set explicitly when binding a shader. */
686 uint16_t *stride_in_dw
;
687 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
689 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
690 unsigned hw_enabled_mask
;
692 /* The state of VGT_STRMOUT_(CONFIG|EN). */
693 bool streamout_enabled
;
694 bool prims_gen_query_enabled
;
695 int num_prims_gen_queries
;
698 /* A shader state consists of the shader selector, which is a constant state
699 * object shared by multiple contexts and shouldn't be modified, and
700 * the current shader variant selected for this context.
702 struct si_shader_ctx_state
{
703 struct si_shader_selector
*cso
;
704 struct si_shader
*current
;
707 #define SI_NUM_VGT_PARAM_KEY_BITS 12
708 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
710 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
711 * Some fields are set by state-change calls, most are set by draw_vbo.
713 union si_vgt_param_key
{
715 #ifdef PIPE_ARCH_LITTLE_ENDIAN
717 unsigned uses_instancing
:1;
718 unsigned multi_instances_smaller_than_primgroup
:1;
719 unsigned primitive_restart
:1;
720 unsigned count_from_stream_output
:1;
721 unsigned line_stipple_enabled
:1;
722 unsigned uses_tess
:1;
723 unsigned tess_uses_prim_id
:1;
725 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
726 #else /* PIPE_ARCH_BIG_ENDIAN */
727 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
729 unsigned tess_uses_prim_id
:1;
730 unsigned uses_tess
:1;
731 unsigned line_stipple_enabled
:1;
732 unsigned count_from_stream_output
:1;
733 unsigned primitive_restart
:1;
734 unsigned multi_instances_smaller_than_primgroup
:1;
735 unsigned uses_instancing
:1;
742 struct si_texture_handle
746 struct pipe_sampler_view
*view
;
747 struct si_sampler_state sstate
;
750 struct si_image_handle
754 struct pipe_image_view view
;
758 struct pipe_reference reference
;
759 struct si_context
*ctx
;
760 struct radeon_saved_cs gfx
;
761 struct r600_resource
*trace_buf
;
764 unsigned gfx_last_dw
;
770 struct pipe_context b
; /* base class */
772 enum radeon_family family
;
773 enum chip_class chip_class
;
775 struct radeon_winsys
*ws
;
776 struct radeon_winsys_ctx
*ctx
;
777 struct radeon_cmdbuf
*gfx_cs
;
778 struct radeon_cmdbuf
*dma_cs
;
779 struct pipe_fence_handle
*last_gfx_fence
;
780 struct pipe_fence_handle
*last_sdma_fence
;
781 struct r600_resource
*eop_bug_scratch
;
782 struct u_upload_mgr
*cached_gtt_allocator
;
783 struct threaded_context
*tc
;
784 struct u_suballocator
*allocator_zeroed_memory
;
785 struct slab_child_pool pool_transfers
;
786 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
787 struct pipe_device_reset_callback device_reset_callback
;
788 struct u_log_context
*log
;
789 void *query_result_shader
;
790 struct blitter_context
*blitter
;
791 void *custom_dsa_flush
;
792 void *custom_blend_resolve
;
793 void *custom_blend_fmask_decompress
;
794 void *custom_blend_eliminate_fastclear
;
795 void *custom_blend_dcc_decompress
;
797 void *vs_blit_pos_layered
;
799 void *vs_blit_color_layered
;
800 void *vs_blit_texcoord
;
801 void *cs_clear_buffer
;
802 void *cs_copy_buffer
;
803 struct si_screen
*screen
;
804 struct pipe_debug_callback debug
;
805 struct ac_llvm_compiler compiler
; /* only non-threaded compilation */
806 struct si_shader_ctx_state fixed_func_tcs_shader
;
807 struct r600_resource
*wait_mem_scratch
;
808 unsigned wait_mem_number
;
809 uint16_t prefetch_L2_mask
;
811 bool gfx_flush_in_progress
:1;
812 bool gfx_last_ib_is_busy
:1;
813 bool compute_is_busy
:1;
815 unsigned num_gfx_cs_flushes
;
816 unsigned initial_gfx_cs_size
;
817 unsigned gpu_reset_counter
;
818 unsigned last_dirty_tex_counter
;
819 unsigned last_compressed_colortex_counter
;
820 unsigned last_num_draw_calls
;
821 unsigned flags
; /* flush flags */
822 /* Current unaccounted memory usage. */
826 /* Atoms (direct states). */
827 union si_state_atoms atoms
;
828 unsigned dirty_atoms
; /* mask */
829 /* PM4 states (precomputed immutable states) */
830 unsigned dirty_states
;
831 union si_state queued
;
832 union si_state emitted
;
834 /* Atom declarations. */
835 struct si_framebuffer framebuffer
;
836 unsigned sample_locs_num_samples
;
837 uint16_t sample_mask
;
838 unsigned last_cb_target_mask
;
839 struct si_blend_color blend_color
;
840 struct si_clip_state clip_state
;
841 struct si_shader_data shader_pointers
;
842 struct si_stencil_ref stencil_ref
;
843 struct si_scissors scissors
;
844 struct si_streamout streamout
;
845 struct si_viewports viewports
;
846 unsigned num_window_rectangles
;
847 bool window_rectangles_include
;
848 struct pipe_scissor_state window_rectangles
[4];
850 /* Precomputed states. */
851 struct si_pm4_state
*init_config
;
852 struct si_pm4_state
*init_config_gs_rings
;
853 bool init_config_has_vgt_flush
;
854 struct si_pm4_state
*vgt_shader_config
[4];
857 struct si_shader_ctx_state ps_shader
;
858 struct si_shader_ctx_state gs_shader
;
859 struct si_shader_ctx_state vs_shader
;
860 struct si_shader_ctx_state tcs_shader
;
861 struct si_shader_ctx_state tes_shader
;
862 struct si_cs_shader_state cs_shader_state
;
864 /* shader information */
865 struct si_vertex_elements
*vertex_elements
;
866 unsigned sprite_coord_enable
;
867 unsigned cs_max_waves_per_sh
;
869 bool do_update_shaders
;
871 /* vertex buffer descriptors */
872 uint32_t *vb_descriptors_gpu_list
;
873 struct r600_resource
*vb_descriptors_buffer
;
874 unsigned vb_descriptors_offset
;
876 /* shader descriptors */
877 struct si_descriptors descriptors
[SI_NUM_DESCS
];
878 unsigned descriptors_dirty
;
879 unsigned shader_pointers_dirty
;
880 unsigned shader_needs_decompress_mask
;
881 struct si_buffer_resources rw_buffers
;
882 struct si_buffer_resources const_and_shader_buffers
[SI_NUM_SHADERS
];
883 struct si_samplers samplers
[SI_NUM_SHADERS
];
884 struct si_images images
[SI_NUM_SHADERS
];
886 /* other shader resources */
887 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on CIK */
888 struct pipe_resource
*esgs_ring
;
889 struct pipe_resource
*gsvs_ring
;
890 struct pipe_resource
*tess_rings
;
891 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
892 struct r600_resource
*border_color_buffer
;
893 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
894 unsigned border_color_count
;
895 unsigned num_vs_blit_sgprs
;
896 uint32_t vs_blit_sh_data
[SI_VS_BLIT_SGPRS_POS_TEXCOORD
];
897 uint32_t cs_user_data
[4];
900 * last_block allows disabling threads at the farthermost grid boundary.
901 * Full blocks as specified by "block" are launched, but the threads
902 * outside of "last_block" dimensions are disabled.
904 * If a block touches the grid boundary in the i-th axis, threads with
905 * THREAD_ID[i] >= last_block[i] are disabled.
907 * If last_block[i] is 0, it has the same behavior as last_block[i] = block[i],
910 * It's equivalent to doing this at the beginning of the compute shader:
912 * for (i = 0; i < 3; i++) {
913 * if (block_id[i] == grid[i] - 1 &&
914 * last_block[i] && last_block[i] >= thread_id[i])
917 * (this could be moved into pipe_grid_info)
919 uint compute_last_block
[3];
921 /* Vertex and index buffers. */
922 bool vertex_buffers_dirty
;
923 bool vertex_buffer_pointer_dirty
;
924 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
926 /* MSAA config state. */
928 bool ps_uses_fbfetch
;
929 bool smoothing_enabled
;
931 /* DB render state. */
932 unsigned ps_db_shader_control
;
933 unsigned dbcb_copy_sample
;
934 bool dbcb_depth_copy_enabled
:1;
935 bool dbcb_stencil_copy_enabled
:1;
936 bool db_flush_depth_inplace
:1;
937 bool db_flush_stencil_inplace
:1;
938 bool db_depth_clear
:1;
939 bool db_depth_disable_expclear
:1;
940 bool db_stencil_clear
:1;
941 bool db_stencil_disable_expclear
:1;
942 bool occlusion_queries_disabled
:1;
943 bool generate_mipmap_for_depth
:1;
945 /* Emitted draw state. */
946 bool gs_tri_strip_adj_fix
:1;
949 int last_base_vertex
;
950 int last_start_instance
;
951 int last_instance_count
;
953 int last_sh_base_reg
;
954 int last_primitive_restart_en
;
955 int last_restart_index
;
957 int last_multi_vgt_param
;
959 unsigned last_sc_line_stipple
;
960 unsigned current_vs_state
;
961 unsigned last_vs_state
;
962 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
965 struct r600_resource
*scratch_buffer
;
966 unsigned scratch_waves
;
967 unsigned spi_tmpring_size
;
969 struct r600_resource
*compute_scratch_buffer
;
971 /* Emitted derived tessellation state. */
972 /* Local shader (VS), or HS if LS-HS are merged. */
973 struct si_shader
*last_ls
;
974 struct si_shader_selector
*last_tcs
;
975 int last_num_tcs_input_cp
;
976 int last_tes_sh_base
;
977 bool last_tess_uses_primid
;
978 unsigned last_num_patches
;
979 int last_ls_hs_config
;
983 struct si_saved_cs
*current_saved_cs
;
984 uint64_t dmesg_timestamp
;
985 unsigned apitrace_call_number
;
988 bool need_check_render_feedback
;
989 bool decompression_enabled
;
991 bool vs_writes_viewport_index
;
992 bool vs_disables_clipping_viewport
;
994 /* Precomputed IA_MULTI_VGT_PARAM */
995 union si_vgt_param_key ia_multi_vgt_param_key
;
996 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
998 /* Bindless descriptors. */
999 struct si_descriptors bindless_descriptors
;
1000 struct util_idalloc bindless_used_slots
;
1001 unsigned num_bindless_descriptors
;
1002 bool bindless_descriptors_dirty
;
1003 bool graphics_bindless_pointer_dirty
;
1004 bool compute_bindless_pointer_dirty
;
1006 /* Allocated bindless handles */
1007 struct hash_table
*tex_handles
;
1008 struct hash_table
*img_handles
;
1010 /* Resident bindless handles */
1011 struct util_dynarray resident_tex_handles
;
1012 struct util_dynarray resident_img_handles
;
1014 /* Resident bindless handles which need decompression */
1015 struct util_dynarray resident_tex_needs_color_decompress
;
1016 struct util_dynarray resident_img_needs_color_decompress
;
1017 struct util_dynarray resident_tex_needs_depth_decompress
;
1019 /* Bindless state */
1020 bool uses_bindless_samplers
;
1021 bool uses_bindless_images
;
1023 /* MSAA sample locations.
1024 * The first index is the sample index.
1025 * The second index is the coordinate: X, Y. */
1033 struct pipe_resource
*sample_pos_buffer
;
1036 unsigned num_draw_calls
;
1037 unsigned num_decompress_calls
;
1038 unsigned num_mrt_draw_calls
;
1039 unsigned num_prim_restart_calls
;
1040 unsigned num_spill_draw_calls
;
1041 unsigned num_compute_calls
;
1042 unsigned num_spill_compute_calls
;
1043 unsigned num_dma_calls
;
1044 unsigned num_cp_dma_calls
;
1045 unsigned num_vs_flushes
;
1046 unsigned num_ps_flushes
;
1047 unsigned num_cs_flushes
;
1048 unsigned num_cb_cache_flushes
;
1049 unsigned num_db_cache_flushes
;
1050 unsigned num_L2_invalidates
;
1051 unsigned num_L2_writebacks
;
1052 unsigned num_resident_handles
;
1053 uint64_t num_alloc_tex_transfer_bytes
;
1054 unsigned last_tex_ps_draw_ratio
; /* for query */
1055 unsigned context_roll_counter
;
1058 /* Maintain the list of active queries for pausing between IBs. */
1059 int num_occlusion_queries
;
1060 int num_perfect_occlusion_queries
;
1061 struct list_head active_queries
;
1062 unsigned num_cs_dw_queries_suspend
;
1064 /* Render condition. */
1065 struct pipe_query
*render_cond
;
1066 unsigned render_cond_mode
;
1067 bool render_cond_invert
;
1068 bool render_cond_force_off
; /* for u_blitter */
1070 /* Statistics gathering for the DCC enablement heuristic. It can't be
1071 * in si_texture because si_texture can be shared by multiple
1072 * contexts. This is for back buffers only. We shouldn't get too many
1075 * X11 DRI3 rotates among a finite set of back buffers. They should
1076 * all fit in this array. If they don't, separate DCC might never be
1077 * enabled by DCC stat gathering.
1080 struct si_texture
*tex
;
1081 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1082 struct pipe_query
*ps_stats
[3];
1083 /* If all slots are used and another slot is needed,
1084 * the least recently used slot is evicted based on this. */
1085 int64_t last_use_timestamp
;
1089 /* Copy one resource to another using async DMA. */
1090 void (*dma_copy
)(struct pipe_context
*ctx
,
1091 struct pipe_resource
*dst
,
1093 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
1094 struct pipe_resource
*src
,
1096 const struct pipe_box
*src_box
);
1098 struct si_tracked_regs tracked_regs
;
1102 void cik_init_sdma_functions(struct si_context
*sctx
);
1105 enum si_blitter_op
/* bitmask */
1107 SI_SAVE_TEXTURES
= 1,
1108 SI_SAVE_FRAMEBUFFER
= 2,
1109 SI_SAVE_FRAGMENT_STATE
= 4,
1110 SI_DISABLE_RENDER_COND
= 8,
1113 void si_blitter_begin(struct si_context
*sctx
, enum si_blitter_op op
);
1114 void si_blitter_end(struct si_context
*sctx
);
1115 void si_init_blit_functions(struct si_context
*sctx
);
1116 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
);
1117 void si_resource_copy_region(struct pipe_context
*ctx
,
1118 struct pipe_resource
*dst
,
1120 unsigned dstx
, unsigned dsty
, unsigned dstz
,
1121 struct pipe_resource
*src
,
1123 const struct pipe_box
*src_box
);
1124 void si_decompress_dcc(struct si_context
*sctx
, struct si_texture
*tex
);
1125 void si_blit_decompress_depth(struct pipe_context
*ctx
,
1126 struct si_texture
*texture
,
1127 struct si_texture
*staging
,
1128 unsigned first_level
, unsigned last_level
,
1129 unsigned first_layer
, unsigned last_layer
,
1130 unsigned first_sample
, unsigned last_sample
);
1133 bool si_rings_is_buffer_referenced(struct si_context
*sctx
,
1134 struct pb_buffer
*buf
,
1135 enum radeon_bo_usage usage
);
1136 void *si_buffer_map_sync_with_rings(struct si_context
*sctx
,
1137 struct r600_resource
*resource
,
1139 void si_init_resource_fields(struct si_screen
*sscreen
,
1140 struct r600_resource
*res
,
1141 uint64_t size
, unsigned alignment
);
1142 bool si_alloc_resource(struct si_screen
*sscreen
,
1143 struct r600_resource
*res
);
1144 struct pipe_resource
*pipe_aligned_buffer_create(struct pipe_screen
*screen
,
1145 unsigned flags
, unsigned usage
,
1146 unsigned size
, unsigned alignment
);
1147 struct r600_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
,
1148 unsigned flags
, unsigned usage
,
1149 unsigned size
, unsigned alignment
);
1150 void si_replace_buffer_storage(struct pipe_context
*ctx
,
1151 struct pipe_resource
*dst
,
1152 struct pipe_resource
*src
);
1153 void si_init_screen_buffer_functions(struct si_screen
*sscreen
);
1154 void si_init_buffer_functions(struct si_context
*sctx
);
1157 enum pipe_format
si_simplify_cb_format(enum pipe_format format
);
1158 bool vi_alpha_is_on_msb(enum pipe_format format
);
1159 void vi_dcc_clear_level(struct si_context
*sctx
,
1160 struct si_texture
*tex
,
1161 unsigned level
, unsigned clear_value
);
1162 void si_init_clear_functions(struct si_context
*sctx
);
1164 /* si_compute_blit.c */
1165 unsigned si_get_flush_flags(struct si_context
*sctx
, enum si_coherency coher
,
1166 enum si_cache_policy cache_policy
);
1167 void si_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1168 uint64_t offset
, uint64_t size
, uint32_t *clear_value
,
1169 uint32_t clear_value_size
, enum si_coherency coher
);
1170 void si_copy_buffer(struct si_context
*sctx
,
1171 struct pipe_resource
*dst
, struct pipe_resource
*src
,
1172 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
);
1173 void si_init_compute_blit_functions(struct si_context
*sctx
);
1176 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1177 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1178 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1179 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1180 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1181 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1182 SI_CPDMA_SKIP_SYNC_AFTER | \
1183 SI_CPDMA_SKIP_SYNC_BEFORE | \
1184 SI_CPDMA_SKIP_GFX_SYNC | \
1185 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1187 void si_cp_dma_wait_for_idle(struct si_context
*sctx
);
1188 void si_cp_dma_clear_buffer(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
,
1189 struct pipe_resource
*dst
, uint64_t offset
,
1190 uint64_t size
, unsigned value
, unsigned user_flags
,
1191 enum si_coherency coher
, enum si_cache_policy cache_policy
);
1192 void si_cp_dma_copy_buffer(struct si_context
*sctx
,
1193 struct pipe_resource
*dst
, struct pipe_resource
*src
,
1194 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
1195 unsigned user_flags
, enum si_coherency coher
,
1196 enum si_cache_policy cache_policy
);
1197 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
1198 uint64_t offset
, unsigned size
);
1199 void cik_emit_prefetch_L2(struct si_context
*sctx
, bool vertex_stage_only
);
1200 void si_test_gds(struct si_context
*sctx
);
1201 void si_cp_write_data(struct si_context
*sctx
, struct r600_resource
*buf
,
1202 unsigned offset
, unsigned size
, unsigned dst_sel
,
1203 unsigned engine
, const void *data
);
1206 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_cmdbuf
*cs
,
1207 struct radeon_saved_cs
*saved
, bool get_buffer_list
);
1208 void si_clear_saved_cs(struct radeon_saved_cs
*saved
);
1209 void si_destroy_saved_cs(struct si_saved_cs
*scs
);
1210 void si_auto_log_cs(void *data
, struct u_log_context
*log
);
1211 void si_log_hw_flush(struct si_context
*sctx
);
1212 void si_log_draw_state(struct si_context
*sctx
, struct u_log_context
*log
);
1213 void si_log_compute_state(struct si_context
*sctx
, struct u_log_context
*log
);
1214 void si_init_debug_functions(struct si_context
*sctx
);
1215 void si_check_vm_faults(struct si_context
*sctx
,
1216 struct radeon_saved_cs
*saved
, enum ring_type ring
);
1217 bool si_replace_shader(unsigned num
, struct ac_shader_binary
*binary
);
1220 void si_init_dma_functions(struct si_context
*sctx
);
1223 void si_dma_emit_timestamp(struct si_context
*sctx
, struct r600_resource
*dst
,
1225 void si_sdma_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1226 uint64_t offset
, uint64_t size
, unsigned clear_value
);
1227 void si_need_dma_space(struct si_context
*ctx
, unsigned num_dw
,
1228 struct r600_resource
*dst
, struct r600_resource
*src
);
1229 void si_flush_dma_cs(struct si_context
*ctx
, unsigned flags
,
1230 struct pipe_fence_handle
**fence
);
1231 void si_screen_clear_buffer(struct si_screen
*sscreen
, struct pipe_resource
*dst
,
1232 uint64_t offset
, uint64_t size
, unsigned value
);
1235 void si_cp_release_mem(struct si_context
*ctx
,
1236 unsigned event
, unsigned event_flags
,
1237 unsigned dst_sel
, unsigned int_sel
, unsigned data_sel
,
1238 struct r600_resource
*buf
, uint64_t va
,
1239 uint32_t new_fence
, unsigned query_type
);
1240 unsigned si_cp_write_fence_dwords(struct si_screen
*screen
);
1241 void si_cp_wait_mem(struct si_context
*ctx
, struct radeon_cmdbuf
*cs
,
1242 uint64_t va
, uint32_t ref
, uint32_t mask
, unsigned flags
);
1243 void si_init_fence_functions(struct si_context
*ctx
);
1244 void si_init_screen_fence_functions(struct si_screen
*screen
);
1245 struct pipe_fence_handle
*si_create_fence(struct pipe_context
*ctx
,
1246 struct tc_unflushed_batch_token
*tc_token
);
1249 void si_init_screen_get_functions(struct si_screen
*sscreen
);
1252 void si_flush_gfx_cs(struct si_context
*ctx
, unsigned flags
,
1253 struct pipe_fence_handle
**fence
);
1254 void si_begin_new_gfx_cs(struct si_context
*ctx
);
1255 void si_need_gfx_cs_space(struct si_context
*ctx
);
1257 /* r600_gpu_load.c */
1258 void si_gpu_load_kill_thread(struct si_screen
*sscreen
);
1259 uint64_t si_begin_counter(struct si_screen
*sscreen
, unsigned type
);
1260 unsigned si_end_counter(struct si_screen
*sscreen
, unsigned type
,
1264 void si_init_compute_functions(struct si_context
*sctx
);
1266 /* si_perfcounters.c */
1267 void si_init_perfcounters(struct si_screen
*screen
);
1268 void si_destroy_perfcounters(struct si_screen
*screen
);
1271 bool si_check_device_reset(struct si_context
*sctx
);
1274 void si_init_screen_query_functions(struct si_screen
*sscreen
);
1275 void si_init_query_functions(struct si_context
*sctx
);
1276 void si_suspend_queries(struct si_context
*sctx
);
1277 void si_resume_queries(struct si_context
*sctx
);
1279 /* si_shaderlib_tgsi.c */
1280 void *si_get_blitter_vs(struct si_context
*sctx
, enum blitter_attrib_type type
,
1281 unsigned num_layers
);
1282 void *si_create_fixed_func_tcs(struct si_context
*sctx
);
1283 void *si_create_dma_compute_shader(struct pipe_context
*ctx
,
1284 unsigned num_dwords_per_thread
,
1285 bool dst_stream_cache_policy
, bool is_copy
);
1286 void *si_create_query_result_cs(struct si_context
*sctx
);
1289 void si_test_dma(struct si_screen
*sscreen
);
1291 /* si_test_clearbuffer.c */
1292 void si_test_dma_perf(struct si_screen
*sscreen
);
1295 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
1296 const struct pipe_video_codec
*templ
);
1298 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
1299 const struct pipe_video_buffer
*tmpl
);
1302 void si_update_vs_viewport_state(struct si_context
*ctx
);
1303 void si_init_viewport_functions(struct si_context
*ctx
);
1306 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
1307 struct si_texture
*dst
,
1308 unsigned dst_level
, unsigned dstx
,
1309 unsigned dsty
, unsigned dstz
,
1310 struct si_texture
*src
,
1312 const struct pipe_box
*src_box
);
1313 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
1314 struct si_texture
*tex
);
1315 void si_texture_discard_cmask(struct si_screen
*sscreen
,
1316 struct si_texture
*tex
);
1317 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1318 struct pipe_resource
*texture
,
1319 struct si_texture
**staging
);
1320 void si_print_texture_info(struct si_screen
*sscreen
,
1321 struct si_texture
*tex
, struct u_log_context
*log
);
1322 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1323 const struct pipe_resource
*templ
);
1324 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1325 enum pipe_format format2
);
1326 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1328 enum pipe_format view_format
);
1329 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
1330 struct pipe_resource
*tex
,
1332 enum pipe_format view_format
);
1333 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1334 struct pipe_resource
*texture
,
1335 const struct pipe_surface
*templ
,
1336 unsigned width0
, unsigned height0
,
1337 unsigned width
, unsigned height
);
1338 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
1339 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
1340 struct si_texture
*tex
);
1341 void vi_separate_dcc_start_query(struct si_context
*sctx
,
1342 struct si_texture
*tex
);
1343 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
1344 struct si_texture
*tex
);
1345 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
1346 struct si_texture
*tex
);
1347 bool si_texture_disable_dcc(struct si_context
*sctx
,
1348 struct si_texture
*tex
);
1349 void si_init_screen_texture_functions(struct si_screen
*sscreen
);
1350 void si_init_context_texture_functions(struct si_context
*sctx
);
1357 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
1359 return (struct r600_resource
*)r
;
1363 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
1365 pipe_resource_reference((struct pipe_resource
**)ptr
,
1366 (struct pipe_resource
*)res
);
1370 si_texture_reference(struct si_texture
**ptr
, struct si_texture
*res
)
1372 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->buffer
.b
.b
);
1376 vi_dcc_enabled(struct si_texture
*tex
, unsigned level
)
1378 return tex
->dcc_offset
&& level
< tex
->surface
.num_dcc_levels
;
1381 static inline unsigned
1382 si_tile_mode_index(struct si_texture
*tex
, unsigned level
, bool stencil
)
1385 return tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
1387 return tex
->surface
.u
.legacy
.tiling_index
[level
];
1391 si_context_add_resource_size(struct si_context
*sctx
, struct pipe_resource
*r
)
1394 /* Add memory usage for need_gfx_cs_space */
1395 sctx
->vram
+= r600_resource(r
)->vram_usage
;
1396 sctx
->gtt
+= r600_resource(r
)->gart_usage
;
1401 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
1403 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
1404 sctx
->last_instance_count
= SI_INSTANCE_COUNT_UNKNOWN
;
1407 static inline unsigned
1408 si_get_atom_bit(struct si_context
*sctx
, struct si_atom
*atom
)
1410 return 1 << (atom
- sctx
->atoms
.array
);
1414 si_set_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
, bool dirty
)
1416 unsigned bit
= si_get_atom_bit(sctx
, atom
);
1419 sctx
->dirty_atoms
|= bit
;
1421 sctx
->dirty_atoms
&= ~bit
;
1425 si_is_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1427 return (sctx
->dirty_atoms
& si_get_atom_bit(sctx
, atom
)) != 0;
1431 si_mark_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1433 si_set_atom_dirty(sctx
, atom
, true);
1436 static inline struct si_shader_ctx_state
*si_get_vs(struct si_context
*sctx
)
1438 if (sctx
->gs_shader
.cso
)
1439 return &sctx
->gs_shader
;
1440 if (sctx
->tes_shader
.cso
)
1441 return &sctx
->tes_shader
;
1443 return &sctx
->vs_shader
;
1446 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
1448 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1450 return vs
->cso
? &vs
->cso
->info
: NULL
;
1453 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
1455 if (sctx
->gs_shader
.cso
)
1456 return sctx
->gs_shader
.cso
->gs_copy_shader
;
1458 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1459 return vs
->current
? vs
->current
: NULL
;
1462 static inline bool si_can_dump_shader(struct si_screen
*sscreen
,
1465 return sscreen
->debug_flags
& (1 << processor
);
1468 static inline bool si_get_strmout_en(struct si_context
*sctx
)
1470 return sctx
->streamout
.streamout_enabled
||
1471 sctx
->streamout
.prims_gen_query_enabled
;
1474 static inline unsigned
1475 si_optimal_tcc_alignment(struct si_context
*sctx
, unsigned upload_size
)
1477 unsigned alignment
, tcc_cache_line_size
;
1479 /* If the upload size is less than the cache line size (e.g. 16, 32),
1480 * the whole thing will fit into a cache line if we align it to its size.
1481 * The idea is that multiple small uploads can share a cache line.
1482 * If the upload size is greater, align it to the cache line size.
1484 alignment
= util_next_power_of_two(upload_size
);
1485 tcc_cache_line_size
= sctx
->screen
->info
.tcc_cache_line_size
;
1486 return MIN2(alignment
, tcc_cache_line_size
);
1490 si_saved_cs_reference(struct si_saved_cs
**dst
, struct si_saved_cs
*src
)
1492 if (pipe_reference(&(*dst
)->reference
, &src
->reference
))
1493 si_destroy_saved_cs(*dst
);
1499 si_make_CB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1500 bool shaders_read_metadata
)
1502 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
|
1503 SI_CONTEXT_INV_VMEM_L1
;
1505 if (sctx
->chip_class
>= GFX9
) {
1506 /* Single-sample color is coherent with shaders on GFX9, but
1507 * L2 metadata must be flushed if shaders read metadata.
1510 if (num_samples
>= 2)
1511 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1512 else if (shaders_read_metadata
)
1513 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1516 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1521 si_make_DB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1522 bool include_stencil
, bool shaders_read_metadata
)
1524 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB
|
1525 SI_CONTEXT_INV_VMEM_L1
;
1527 if (sctx
->chip_class
>= GFX9
) {
1528 /* Single-sample depth (not stencil) is coherent with shaders
1529 * on GFX9, but L2 metadata must be flushed if shaders read
1532 if (num_samples
>= 2 || include_stencil
)
1533 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1534 else if (shaders_read_metadata
)
1535 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1538 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1543 si_can_sample_zs(struct si_texture
*tex
, bool stencil_sampler
)
1545 return (stencil_sampler
&& tex
->can_sample_s
) ||
1546 (!stencil_sampler
&& tex
->can_sample_z
);
1550 si_htile_enabled(struct si_texture
*tex
, unsigned level
)
1552 return tex
->htile_offset
&& level
== 0;
1556 vi_tc_compat_htile_enabled(struct si_texture
*tex
, unsigned level
)
1558 assert(!tex
->tc_compatible_htile
|| tex
->htile_offset
);
1559 return tex
->tc_compatible_htile
&& level
== 0;
1562 static inline unsigned si_get_ps_iter_samples(struct si_context
*sctx
)
1564 if (sctx
->ps_uses_fbfetch
)
1565 return sctx
->framebuffer
.nr_color_samples
;
1567 return MIN2(sctx
->ps_iter_samples
, sctx
->framebuffer
.nr_color_samples
);
1570 static inline unsigned si_get_total_colormask(struct si_context
*sctx
)
1572 if (sctx
->queued
.named
.rasterizer
->rasterizer_discard
)
1575 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1579 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
1580 sctx
->queued
.named
.blend
->cb_target_mask
;
1582 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
1583 colormask
&= ps
->colors_written_4bit
;
1584 else if (!ps
->colors_written_4bit
)
1585 colormask
= 0; /* color0 writes all cbufs, but it's not written */
1590 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1591 (1 << PIPE_PRIM_LINE_LOOP) | \
1592 (1 << PIPE_PRIM_LINE_STRIP) | \
1593 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1594 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1596 static inline bool util_prim_is_lines(unsigned prim
)
1598 return ((1 << prim
) & UTIL_ALL_PRIM_LINE_MODES
) != 0;
1601 static inline bool util_prim_is_points_or_lines(unsigned prim
)
1603 return ((1 << prim
) & (UTIL_ALL_PRIM_LINE_MODES
|
1604 (1 << PIPE_PRIM_POINTS
))) != 0;
1608 * Return true if there is enough memory in VRAM and GTT for the buffers
1611 * \param vram VRAM memory size not added to the buffer list yet
1612 * \param gtt GTT memory size not added to the buffer list yet
1615 radeon_cs_memory_below_limit(struct si_screen
*screen
,
1616 struct radeon_cmdbuf
*cs
,
1617 uint64_t vram
, uint64_t gtt
)
1619 vram
+= cs
->used_vram
;
1620 gtt
+= cs
->used_gart
;
1622 /* Anything that goes above the VRAM size should go to GTT. */
1623 if (vram
> screen
->info
.vram_size
)
1624 gtt
+= vram
- screen
->info
.vram_size
;
1626 /* Now we just need to check if we have enough GTT. */
1627 return gtt
< screen
->info
.gart_size
* 0.7;
1631 * Add a buffer to the buffer list for the given command stream (CS).
1633 * All buffers used by a CS must be added to the list. This tells the kernel
1634 * driver which buffers are used by GPU commands. Other buffers can
1635 * be swapped out (not accessible) during execution.
1637 * The buffer list becomes empty after every context flush and must be
1640 static inline void radeon_add_to_buffer_list(struct si_context
*sctx
,
1641 struct radeon_cmdbuf
*cs
,
1642 struct r600_resource
*rbo
,
1643 enum radeon_bo_usage usage
,
1644 enum radeon_bo_priority priority
)
1647 sctx
->ws
->cs_add_buffer(
1649 (enum radeon_bo_usage
)(usage
| RADEON_USAGE_SYNCHRONIZED
),
1650 rbo
->domains
, priority
);
1654 * Same as above, but also checks memory usage and flushes the context
1657 * When this SHOULD NOT be used:
1659 * - if si_context_add_resource_size has been called for the buffer
1660 * followed by *_need_cs_space for checking the memory usage
1662 * - if si_need_dma_space has been called for the buffer
1664 * - when emitting state packets and draw packets (because preceding packets
1665 * can't be re-emitted at that point)
1667 * - if shader resource "enabled_mask" is not up-to-date or there is
1668 * a different constraint disallowing a context flush
1671 radeon_add_to_gfx_buffer_list_check_mem(struct si_context
*sctx
,
1672 struct r600_resource
*rbo
,
1673 enum radeon_bo_usage usage
,
1674 enum radeon_bo_priority priority
,
1678 !radeon_cs_memory_below_limit(sctx
->screen
, sctx
->gfx_cs
,
1679 sctx
->vram
+ rbo
->vram_usage
,
1680 sctx
->gtt
+ rbo
->gart_usage
))
1681 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1683 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, rbo
, usage
, priority
);
1686 #define PRINT_ERR(fmt, args...) \
1687 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)