2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "si_shader.h"
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_range.h"
34 #include "util/u_threaded_context.h"
36 #ifdef PIPE_ARCH_BIG_ENDIAN
37 #define SI_BIG_ENDIAN 1
39 #define SI_BIG_ENDIAN 0
42 #define ATI_VENDOR_ID 0x1002
44 #define SI_NOT_QUERY 0xffffffff
46 /* The base vertex and primitive restart can be any number, but we must pick
47 * one which will mean "unknown" for the purpose of state tracking and
48 * the number shouldn't be a commonly-used one. */
49 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
50 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_GS_PER_ES 128
53 /* Alignment for optimal CP DMA performance. */
54 #define SI_CPDMA_ALIGNMENT 32
56 /* Pipeline & streamout query controls. */
57 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
58 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
59 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
60 /* Instruction cache. */
61 #define SI_CONTEXT_INV_ICACHE (1 << 3)
62 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
63 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
64 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
65 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
66 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
67 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
68 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
69 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
70 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
71 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
72 * a CB or DB flush. */
73 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
74 /* Framebuffer caches. */
75 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
76 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
77 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
78 /* Engine synchronization. */
79 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
80 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
81 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
82 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
83 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
85 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
86 #define SI_PREFETCH_LS (1 << 1)
87 #define SI_PREFETCH_HS (1 << 2)
88 #define SI_PREFETCH_ES (1 << 3)
89 #define SI_PREFETCH_GS (1 << 4)
90 #define SI_PREFETCH_VS (1 << 5)
91 #define SI_PREFETCH_PS (1 << 6)
93 #define SI_MAX_BORDER_COLORS 4096
94 #define SI_MAX_VIEWPORTS 16
96 #define SI_MAP_BUFFER_ALIGNMENT 64
97 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
99 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
100 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
101 #define SI_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
102 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
103 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
104 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
105 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
109 /* Shader logging options: */
110 DBG_VS
= PIPE_SHADER_VERTEX
,
111 DBG_PS
= PIPE_SHADER_FRAGMENT
,
112 DBG_GS
= PIPE_SHADER_GEOMETRY
,
113 DBG_TCS
= PIPE_SHADER_TESS_CTRL
,
114 DBG_TES
= PIPE_SHADER_TESS_EVAL
,
115 DBG_CS
= PIPE_SHADER_COMPUTE
,
121 /* Shader compiler options the shader cache should be aware of: */
122 DBG_FS_CORRECT_DERIVS_AFTER_KILL
,
126 /* Shader compiler options (with no effect on the shader cache): */
129 DBG_MONOLITHIC_SHADERS
,
132 /* Information logging options: */
138 /* Driver options: */
145 /* 3D engine options: */
165 DBG_TEST_VMFAULT_SDMA
,
166 DBG_TEST_VMFAULT_SHADER
,
169 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
170 #define DBG(name) (1ull << DBG_##name)
174 struct u_suballocator
;
176 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
179 struct r600_resource
{
180 struct threaded_resource b
;
182 /* Winsys objects. */
183 struct pb_buffer
*buf
;
184 uint64_t gpu_address
;
185 /* Memory usage if the buffer placement is optimal. */
189 /* Resource properties. */
191 unsigned bo_alignment
;
192 enum radeon_bo_domain domains
;
193 enum radeon_bo_flag flags
;
194 unsigned bind_history
;
195 int max_forced_staging_uploads
;
197 /* The buffer range which is initialized (with a write transfer,
198 * streamout, DMA, or as a random access target). The rest of
199 * the buffer is considered invalid and can be mapped unsynchronized.
201 * This allows unsychronized mapping of a buffer range which hasn't
202 * been used yet. It's for applications which forget to use
203 * the unsynchronized map flag and expect the driver to figure it out.
205 struct util_range valid_buffer_range
;
207 /* For buffers only. This indicates that a write operation has been
208 * performed by TC L2, but the cache hasn't been flushed.
209 * Any hw block which doesn't use or bypasses TC L2 should check this
210 * flag and flush the cache before using the buffer.
212 * For example, TC L2 must be flushed if a buffer which has been
213 * modified by a shader store instruction is about to be used as
214 * an index buffer. The reason is that VGT DMA index fetching doesn't
219 /* Whether the resource has been exported via resource_get_handle. */
220 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
222 /* Whether this resource is referenced by bindless handles. */
223 bool texture_handle_allocated
;
224 bool image_handle_allocated
;
227 struct r600_transfer
{
228 struct threaded_transfer b
;
229 struct r600_resource
*staging
;
233 struct r600_fmask_info
{
237 unsigned pitch_in_pixels
;
238 unsigned bank_height
;
239 unsigned slice_tile_max
;
240 unsigned tile_mode_index
;
241 unsigned tile_swizzle
;
244 struct r600_cmask_info
{
248 unsigned slice_tile_max
;
249 uint64_t base_address_reg
;
252 struct r600_texture
{
253 struct r600_resource resource
;
255 struct radeon_surf surface
;
257 struct r600_texture
*flushed_depth_texture
;
259 /* Colorbuffer compression and fast clear. */
260 struct r600_fmask_info fmask
;
261 struct r600_cmask_info cmask
;
262 struct r600_resource
*cmask_buffer
;
263 uint64_t dcc_offset
; /* 0 = disabled */
264 unsigned cb_color_info
; /* fast clear enable bit */
265 unsigned color_clear_value
[2];
266 unsigned last_msaa_resolve_target_micro_mode
;
267 unsigned num_level0_transfers
;
269 /* Depth buffer compression and fast clear. */
270 uint64_t htile_offset
;
271 float depth_clear_value
;
272 uint16_t dirty_level_mask
; /* each bit says if that mipmap is compressed */
273 uint16_t stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
274 enum pipe_format db_render_format
:16;
275 uint8_t stencil_clear_value
;
276 bool tc_compatible_htile
:1;
277 bool depth_cleared
:1; /* if it was cleared at least once */
278 bool stencil_cleared
:1; /* if it was cleared at least once */
279 bool upgraded_depth
:1; /* upgraded from unorm to Z32_FLOAT */
281 bool db_compatible
:1;
285 /* We need to track DCC dirtiness, because st/dri usually calls
286 * flush_resource twice per frame (not a bug) and we don't wanna
287 * decompress DCC twice. Also, the dirty tracking must be done even
288 * if DCC isn't used, because it's required by the DCC usage analysis
289 * for a possible future enablement.
291 bool separate_dcc_dirty
:1;
292 /* Statistics gathering for the DCC enablement heuristic. */
293 bool dcc_gather_statistics
:1;
294 /* Counter that should be non-zero if the texture is bound to a
297 unsigned framebuffers_bound
;
298 /* Whether the texture is a displayable back buffer and needs DCC
299 * decompression, which is expensive. Therefore, it's enabled only
300 * if statistics suggest that it will pay off and it's allocated
301 * separately. It can't be bound as a sampler by apps. Limited to
302 * target == 2D and last_level == 0. If enabled, dcc_offset contains
303 * the absolute GPUVM address, not the relative one.
305 struct r600_resource
*dcc_separate_buffer
;
306 /* When DCC is temporarily disabled, the separate buffer is here. */
307 struct r600_resource
*last_dcc_separate_buffer
;
308 /* Estimate of how much this color buffer is written to in units of
309 * full-screen draws: ps_invocations / (width * height)
310 * Shader kills, late Z, and blending with trivial discards make it
311 * inaccurate (we need to count CB updates, not PS invocations).
313 unsigned ps_draw_ratio
;
314 /* The number of clears since the last DCC usage analysis. */
315 unsigned num_slow_clears
;
318 struct r600_surface
{
319 struct pipe_surface base
;
321 /* These can vary with block-compressed textures. */
325 bool color_initialized
:1;
326 bool depth_initialized
:1;
328 /* Misc. color flags. */
329 bool color_is_int8
:1;
330 bool color_is_int10
:1;
331 bool dcc_incompatible
:1;
333 /* Color registers. */
334 unsigned cb_color_info
;
335 unsigned cb_color_view
;
336 unsigned cb_color_attrib
;
337 unsigned cb_color_attrib2
; /* GFX9 and later */
338 unsigned cb_dcc_control
; /* VI and later */
339 unsigned spi_shader_col_format
:8; /* no blending, no alpha-to-coverage. */
340 unsigned spi_shader_col_format_alpha
:8; /* alpha-to-coverage */
341 unsigned spi_shader_col_format_blend
:8; /* blending without alpha. */
342 unsigned spi_shader_col_format_blend_alpha
:8; /* blending with alpha. */
345 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE */
346 uint64_t db_stencil_base
;
347 uint64_t db_htile_data_base
;
348 unsigned db_depth_info
;
350 unsigned db_z_info2
; /* GFX9+ */
351 unsigned db_depth_view
;
352 unsigned db_depth_size
;
353 unsigned db_depth_slice
;
354 unsigned db_stencil_info
;
355 unsigned db_stencil_info2
; /* GFX9+ */
356 unsigned db_htile_surface
;
359 struct si_mmio_counter
{
364 union si_mmio_counters
{
366 /* For global GPU load including SDMA. */
367 struct si_mmio_counter gpu
;
370 struct si_mmio_counter spi
;
371 struct si_mmio_counter gui
;
372 struct si_mmio_counter ta
;
373 struct si_mmio_counter gds
;
374 struct si_mmio_counter vgt
;
375 struct si_mmio_counter ia
;
376 struct si_mmio_counter sx
;
377 struct si_mmio_counter wd
;
378 struct si_mmio_counter bci
;
379 struct si_mmio_counter sc
;
380 struct si_mmio_counter pa
;
381 struct si_mmio_counter db
;
382 struct si_mmio_counter cp
;
383 struct si_mmio_counter cb
;
386 struct si_mmio_counter sdma
;
389 struct si_mmio_counter pfp
;
390 struct si_mmio_counter meq
;
391 struct si_mmio_counter me
;
392 struct si_mmio_counter surf_sync
;
393 struct si_mmio_counter cp_dma
;
394 struct si_mmio_counter scratch_ram
;
399 struct r600_memory_object
{
400 struct pipe_memory_object b
;
401 struct pb_buffer
*buf
;
406 /* Saved CS data for debugging features. */
407 struct radeon_saved_cs
{
411 struct radeon_bo_list_item
*bo_list
;
416 struct pipe_screen b
;
417 struct radeon_winsys
*ws
;
418 struct disk_cache
*disk_shader_cache
;
420 struct radeon_info info
;
421 uint64_t debug_flags
;
422 char renderer_string
[100];
424 unsigned gs_table_depth
;
425 unsigned tess_offchip_block_dw_size
;
426 unsigned tess_offchip_ring_size
;
427 unsigned tess_factor_ring_size
;
428 unsigned vgt_hs_offchip_param
;
429 bool has_clear_state
;
430 bool has_distributed_tess
;
431 bool has_draw_indirect_multi
;
432 bool has_out_of_order_rast
;
433 bool assume_no_z_fights
;
434 bool commutative_blend_add
;
435 bool clear_db_cache_before_clear
;
436 bool has_msaa_sample_loc_bug
;
437 bool has_ls_vgpr_init_bug
;
440 bool llvm_has_working_vgpr_indexing
;
442 /* Whether shaders are monolithic (1-part) or separate (3-part). */
443 bool use_monolithic_shaders
;
445 bool has_rbplus
; /* if RB+ registers exist */
446 bool rbplus_allowed
; /* if RB+ is allowed */
447 bool dcc_msaa_allowed
;
448 bool cpdma_prefetch_writes_memory
;
450 struct slab_parent_pool pool_transfers
;
452 /* Texture filter settings. */
453 int force_aniso
; /* -1 = disabled */
455 /* Auxiliary context. Mainly used to initialize resources.
456 * It must be locked prior to using and flushed before unlocking. */
457 struct pipe_context
*aux_context
;
458 mtx_t aux_context_lock
;
460 /* This must be in the screen, because UE4 uses one context for
461 * compilation and another one for rendering.
463 unsigned num_compilations
;
464 /* Along with ST_DEBUG=precompile, this should show if applications
465 * are loading shaders on demand. This is a monotonic counter.
467 unsigned num_shaders_created
;
468 unsigned num_shader_cache_hits
;
470 /* GPU load thread. */
471 mtx_t gpu_load_mutex
;
472 thrd_t gpu_load_thread
;
473 union si_mmio_counters mmio_counters
;
474 volatile unsigned gpu_load_stop_thread
; /* bool */
476 /* Performance counters. */
477 struct si_perfcounters
*perfcounters
;
479 /* If pipe_screen wants to recompute and re-emit the framebuffer,
480 * sampler, and image states of all contexts, it should atomically
483 * Each context will compare this with its own last known value of
484 * the counter before drawing and re-emit the states accordingly.
486 unsigned dirty_tex_counter
;
488 /* Atomically increment this counter when an existing texture's
489 * metadata is enabled or disabled in a way that requires changing
490 * contexts' compressed texture binding masks.
492 unsigned compressed_colortex_counter
;
495 /* Context flags to set so that all writes from earlier jobs
496 * in the CP are seen by L2 clients.
500 /* Context flags to set so that all writes from earlier jobs
501 * that end in L2 are seen by CP.
506 mtx_t shader_parts_mutex
;
507 struct si_shader_part
*vs_prologs
;
508 struct si_shader_part
*tcs_epilogs
;
509 struct si_shader_part
*gs_prologs
;
510 struct si_shader_part
*ps_prologs
;
511 struct si_shader_part
*ps_epilogs
;
513 /* Shader cache in memory.
515 * Design & limitations:
516 * - The shader cache is per screen (= per process), never saved to
517 * disk, and skips redundant shader compilations from TGSI to bytecode.
518 * - It can only be used with one-variant-per-shader support, in which
519 * case only the main (typically middle) part of shaders is cached.
520 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
521 * variants of VS and TES are cached, so LS and ES aren't.
522 * - GS and CS aren't cached, but it's certainly possible to cache
525 mtx_t shader_cache_mutex
;
526 struct hash_table
*shader_cache
;
528 /* Shader compiler queue for multithreaded compilation. */
529 struct util_queue shader_compiler_queue
;
530 /* Use at most 3 normal compiler threads on quadcore and better.
531 * Hyperthreaded CPUs report the number of threads, but we want
532 * the number of cores. */
533 LLVMTargetMachineRef tm
[3]; /* used by the queue only */
535 struct util_queue shader_compiler_queue_low_priority
;
536 /* Use at most 2 low priority threads on quadcore and better.
537 * We want to minimize the impact on multithreaded Mesa. */
538 LLVMTargetMachineRef tm_low_priority
[2]; /* at most 2 threads */
541 struct si_blend_color
{
543 struct pipe_blend_color state
;
547 struct si_sampler_view
{
548 struct pipe_sampler_view base
;
549 /* [0..7] = image descriptor
550 * [4..7] = buffer descriptor */
552 uint32_t fmask_state
[8];
553 const struct legacy_surf_level
*base_level_info
;
556 bool is_stencil_sampler
;
558 bool dcc_incompatible
;
561 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
563 struct si_sampler_state
{
568 uint32_t integer_val
[4];
569 uint32_t upgraded_depth_val
[4];
572 struct si_cs_shader_state
{
573 struct si_compute
*program
;
574 struct si_compute
*emitted_program
;
581 struct pipe_sampler_view
*views
[SI_NUM_SAMPLERS
];
582 struct si_sampler_state
*sampler_states
[SI_NUM_SAMPLERS
];
584 /* The i-th bit is set if that element is enabled (non-NULL resource). */
585 unsigned enabled_mask
;
586 uint32_t needs_depth_decompress_mask
;
587 uint32_t needs_color_decompress_mask
;
591 struct pipe_image_view views
[SI_NUM_IMAGES
];
592 uint32_t needs_color_decompress_mask
;
593 unsigned enabled_mask
;
596 struct si_framebuffer
{
598 struct pipe_framebuffer_state state
;
599 unsigned colorbuf_enabled_4bit
;
600 unsigned spi_shader_col_format
;
601 unsigned spi_shader_col_format_alpha
;
602 unsigned spi_shader_col_format_blend
;
603 unsigned spi_shader_col_format_blend_alpha
;
604 ubyte nr_samples
:5; /* at most 16xAA */
605 ubyte log_samples
:3; /* at most 4 = 16xAA */
606 ubyte compressed_cb_mask
;
607 ubyte uncompressed_cb_mask
;
609 ubyte color_is_int10
;
613 bool CB_has_shader_readable_metadata
;
614 bool DB_has_shader_readable_metadata
;
617 struct si_signed_scissor
{
627 struct pipe_scissor_state states
[SI_MAX_VIEWPORTS
];
630 struct si_viewports
{
633 unsigned depth_range_dirty_mask
;
634 struct pipe_viewport_state states
[SI_MAX_VIEWPORTS
];
635 struct si_signed_scissor as_scissor
[SI_MAX_VIEWPORTS
];
638 struct si_clip_state
{
640 struct pipe_clip_state state
;
644 struct si_sample_locs
{
649 struct si_sample_mask
{
651 uint16_t sample_mask
;
654 struct si_streamout_target
{
655 struct pipe_stream_output_target b
;
657 /* The buffer where BUFFER_FILLED_SIZE is stored. */
658 struct r600_resource
*buf_filled_size
;
659 unsigned buf_filled_size_offset
;
660 bool buf_filled_size_valid
;
662 unsigned stride_in_dw
;
665 struct si_streamout
{
666 struct si_atom begin_atom
;
669 unsigned enabled_mask
;
670 unsigned num_targets
;
671 struct si_streamout_target
*targets
[PIPE_MAX_SO_BUFFERS
];
673 unsigned append_bitmask
;
676 /* External state which comes from the vertex shader,
677 * it must be set explicitly when binding a shader. */
678 uint16_t *stride_in_dw
;
679 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
681 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
682 unsigned hw_enabled_mask
;
684 /* The state of VGT_STRMOUT_(CONFIG|EN). */
685 struct si_atom enable_atom
;
686 bool streamout_enabled
;
687 bool prims_gen_query_enabled
;
688 int num_prims_gen_queries
;
691 /* A shader state consists of the shader selector, which is a constant state
692 * object shared by multiple contexts and shouldn't be modified, and
693 * the current shader variant selected for this context.
695 struct si_shader_ctx_state
{
696 struct si_shader_selector
*cso
;
697 struct si_shader
*current
;
700 #define SI_NUM_VGT_PARAM_KEY_BITS 12
701 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
703 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
704 * Some fields are set by state-change calls, most are set by draw_vbo.
706 union si_vgt_param_key
{
708 #ifdef PIPE_ARCH_LITTLE_ENDIAN
710 unsigned uses_instancing
:1;
711 unsigned multi_instances_smaller_than_primgroup
:1;
712 unsigned primitive_restart
:1;
713 unsigned count_from_stream_output
:1;
714 unsigned line_stipple_enabled
:1;
715 unsigned uses_tess
:1;
716 unsigned tess_uses_prim_id
:1;
718 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
719 #else /* PIPE_ARCH_BIG_ENDIAN */
720 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
722 unsigned tess_uses_prim_id
:1;
723 unsigned uses_tess
:1;
724 unsigned line_stipple_enabled
:1;
725 unsigned count_from_stream_output
:1;
726 unsigned primitive_restart
:1;
727 unsigned multi_instances_smaller_than_primgroup
:1;
728 unsigned uses_instancing
:1;
735 struct si_texture_handle
739 struct pipe_sampler_view
*view
;
740 struct si_sampler_state sstate
;
743 struct si_image_handle
747 struct pipe_image_view view
;
751 struct pipe_reference reference
;
752 struct si_context
*ctx
;
753 struct radeon_saved_cs gfx
;
754 struct r600_resource
*trace_buf
;
757 unsigned gfx_last_dw
;
763 struct pipe_context b
; /* base class */
765 enum radeon_family family
;
766 enum chip_class chip_class
;
768 struct radeon_winsys
*ws
;
769 struct radeon_winsys_ctx
*ctx
;
770 struct radeon_winsys_cs
*gfx_cs
;
771 struct radeon_winsys_cs
*dma_cs
;
772 struct pipe_fence_handle
*last_gfx_fence
;
773 struct pipe_fence_handle
*last_sdma_fence
;
774 struct r600_resource
*eop_bug_scratch
;
775 struct u_upload_mgr
*cached_gtt_allocator
;
776 struct threaded_context
*tc
;
777 struct u_suballocator
*allocator_zeroed_memory
;
778 struct slab_child_pool pool_transfers
;
779 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
780 struct pipe_device_reset_callback device_reset_callback
;
781 struct u_log_context
*log
;
782 void *query_result_shader
;
783 struct blitter_context
*blitter
;
784 void *custom_dsa_flush
;
785 void *custom_blend_resolve
;
786 void *custom_blend_fmask_decompress
;
787 void *custom_blend_eliminate_fastclear
;
788 void *custom_blend_dcc_decompress
;
790 void *vs_blit_pos_layered
;
792 void *vs_blit_color_layered
;
793 void *vs_blit_texcoord
;
794 struct si_screen
*screen
;
795 struct pipe_debug_callback debug
;
796 LLVMTargetMachineRef tm
; /* only non-threaded compilation */
797 struct si_shader_ctx_state fixed_func_tcs_shader
;
798 struct r600_resource
*wait_mem_scratch
;
799 unsigned wait_mem_number
;
800 uint16_t prefetch_L2_mask
;
802 bool gfx_flush_in_progress
:1;
803 bool gfx_last_ib_is_busy
:1;
804 bool compute_is_busy
:1;
806 unsigned num_gfx_cs_flushes
;
807 unsigned initial_gfx_cs_size
;
808 unsigned gpu_reset_counter
;
809 unsigned last_dirty_tex_counter
;
810 unsigned last_compressed_colortex_counter
;
811 unsigned last_num_draw_calls
;
812 unsigned flags
; /* flush flags */
813 /* Current unaccounted memory usage. */
817 /* Atoms (direct states). */
818 union si_state_atoms atoms
;
819 unsigned dirty_atoms
; /* mask */
820 /* PM4 states (precomputed immutable states) */
821 unsigned dirty_states
;
822 union si_state queued
;
823 union si_state emitted
;
825 /* Atom declarations. */
826 struct si_framebuffer framebuffer
;
827 struct si_sample_locs msaa_sample_locs
;
828 struct si_atom db_render_state
;
829 struct si_atom dpbb_state
;
830 struct si_atom msaa_config
;
831 struct si_sample_mask sample_mask
;
832 struct si_atom cb_render_state
;
833 unsigned last_cb_target_mask
;
834 struct si_blend_color blend_color
;
835 struct si_atom clip_regs
;
836 struct si_clip_state clip_state
;
837 struct si_shader_data shader_pointers
;
838 struct si_stencil_ref stencil_ref
;
839 struct si_atom spi_map
;
840 struct si_scissors scissors
;
841 struct si_streamout streamout
;
842 struct si_viewports viewports
;
844 /* Precomputed states. */
845 struct si_pm4_state
*init_config
;
846 struct si_pm4_state
*init_config_gs_rings
;
847 bool init_config_has_vgt_flush
;
848 struct si_pm4_state
*vgt_shader_config
[4];
851 struct si_shader_ctx_state ps_shader
;
852 struct si_shader_ctx_state gs_shader
;
853 struct si_shader_ctx_state vs_shader
;
854 struct si_shader_ctx_state tcs_shader
;
855 struct si_shader_ctx_state tes_shader
;
856 struct si_cs_shader_state cs_shader_state
;
858 /* shader information */
859 struct si_vertex_elements
*vertex_elements
;
860 unsigned sprite_coord_enable
;
862 bool do_update_shaders
;
864 /* vertex buffer descriptors */
865 uint32_t *vb_descriptors_gpu_list
;
866 struct r600_resource
*vb_descriptors_buffer
;
867 unsigned vb_descriptors_offset
;
869 /* shader descriptors */
870 struct si_descriptors descriptors
[SI_NUM_DESCS
];
871 unsigned descriptors_dirty
;
872 unsigned shader_pointers_dirty
;
873 unsigned shader_needs_decompress_mask
;
874 struct si_buffer_resources rw_buffers
;
875 struct si_buffer_resources const_and_shader_buffers
[SI_NUM_SHADERS
];
876 struct si_samplers samplers
[SI_NUM_SHADERS
];
877 struct si_images images
[SI_NUM_SHADERS
];
879 /* other shader resources */
880 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on CIK */
881 struct pipe_resource
*esgs_ring
;
882 struct pipe_resource
*gsvs_ring
;
883 struct pipe_resource
*tess_rings
;
884 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
885 struct r600_resource
*border_color_buffer
;
886 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
887 unsigned border_color_count
;
888 unsigned num_vs_blit_sgprs
;
889 uint32_t vs_blit_sh_data
[SI_VS_BLIT_SGPRS_POS_TEXCOORD
];
891 /* Vertex and index buffers. */
892 bool vertex_buffers_dirty
;
893 bool vertex_buffer_pointer_dirty
;
894 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
896 /* MSAA config state. */
898 bool ps_uses_fbfetch
;
899 bool smoothing_enabled
;
901 /* DB render state. */
902 unsigned ps_db_shader_control
;
903 unsigned dbcb_copy_sample
;
904 bool dbcb_depth_copy_enabled
:1;
905 bool dbcb_stencil_copy_enabled
:1;
906 bool db_flush_depth_inplace
:1;
907 bool db_flush_stencil_inplace
:1;
908 bool db_depth_clear
:1;
909 bool db_depth_disable_expclear
:1;
910 bool db_stencil_clear
:1;
911 bool db_stencil_disable_expclear
:1;
912 bool occlusion_queries_disabled
:1;
913 bool generate_mipmap_for_depth
:1;
915 /* Emitted draw state. */
916 bool gs_tri_strip_adj_fix
:1;
919 int last_base_vertex
;
920 int last_start_instance
;
922 int last_sh_base_reg
;
923 int last_primitive_restart_en
;
924 int last_restart_index
;
925 int last_gs_out_prim
;
927 int last_multi_vgt_param
;
929 unsigned last_sc_line_stipple
;
930 unsigned current_vs_state
;
931 unsigned last_vs_state
;
932 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
935 struct si_atom scratch_state
;
936 struct r600_resource
*scratch_buffer
;
937 unsigned scratch_waves
;
938 unsigned spi_tmpring_size
;
940 struct r600_resource
*compute_scratch_buffer
;
942 /* Emitted derived tessellation state. */
943 /* Local shader (VS), or HS if LS-HS are merged. */
944 struct si_shader
*last_ls
;
945 struct si_shader_selector
*last_tcs
;
946 int last_num_tcs_input_cp
;
947 int last_tes_sh_base
;
948 bool last_tess_uses_primid
;
949 unsigned last_num_patches
;
953 struct si_saved_cs
*current_saved_cs
;
954 uint64_t dmesg_timestamp
;
955 unsigned apitrace_call_number
;
958 bool need_check_render_feedback
;
959 bool decompression_enabled
;
961 bool vs_writes_viewport_index
;
962 bool vs_disables_clipping_viewport
;
964 /* Precomputed IA_MULTI_VGT_PARAM */
965 union si_vgt_param_key ia_multi_vgt_param_key
;
966 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
968 /* Bindless descriptors. */
969 struct si_descriptors bindless_descriptors
;
970 struct util_idalloc bindless_used_slots
;
971 unsigned num_bindless_descriptors
;
972 bool bindless_descriptors_dirty
;
973 bool graphics_bindless_pointer_dirty
;
974 bool compute_bindless_pointer_dirty
;
976 /* Allocated bindless handles */
977 struct hash_table
*tex_handles
;
978 struct hash_table
*img_handles
;
980 /* Resident bindless handles */
981 struct util_dynarray resident_tex_handles
;
982 struct util_dynarray resident_img_handles
;
984 /* Resident bindless handles which need decompression */
985 struct util_dynarray resident_tex_needs_color_decompress
;
986 struct util_dynarray resident_img_needs_color_decompress
;
987 struct util_dynarray resident_tex_needs_depth_decompress
;
990 bool uses_bindless_samplers
;
991 bool uses_bindless_images
;
993 /* MSAA sample locations.
994 * The first index is the sample index.
995 * The second index is the coordinate: X, Y. */
996 float sample_locations_1x
[1][2];
997 float sample_locations_2x
[2][2];
998 float sample_locations_4x
[4][2];
999 float sample_locations_8x
[8][2];
1000 float sample_locations_16x
[16][2];
1003 unsigned num_draw_calls
;
1004 unsigned num_decompress_calls
;
1005 unsigned num_mrt_draw_calls
;
1006 unsigned num_prim_restart_calls
;
1007 unsigned num_spill_draw_calls
;
1008 unsigned num_compute_calls
;
1009 unsigned num_spill_compute_calls
;
1010 unsigned num_dma_calls
;
1011 unsigned num_cp_dma_calls
;
1012 unsigned num_vs_flushes
;
1013 unsigned num_ps_flushes
;
1014 unsigned num_cs_flushes
;
1015 unsigned num_cb_cache_flushes
;
1016 unsigned num_db_cache_flushes
;
1017 unsigned num_L2_invalidates
;
1018 unsigned num_L2_writebacks
;
1019 unsigned num_resident_handles
;
1020 uint64_t num_alloc_tex_transfer_bytes
;
1021 unsigned last_tex_ps_draw_ratio
; /* for query */
1024 /* Maintain the list of active queries for pausing between IBs. */
1025 int num_occlusion_queries
;
1026 int num_perfect_occlusion_queries
;
1027 struct list_head active_queries
;
1028 unsigned num_cs_dw_queries_suspend
;
1030 /* Render condition. */
1031 struct si_atom render_cond_atom
;
1032 struct pipe_query
*render_cond
;
1033 unsigned render_cond_mode
;
1034 bool render_cond_invert
;
1035 bool render_cond_force_off
; /* for u_blitter */
1037 /* Statistics gathering for the DCC enablement heuristic. It can't be
1038 * in r600_texture because r600_texture can be shared by multiple
1039 * contexts. This is for back buffers only. We shouldn't get too many
1042 * X11 DRI3 rotates among a finite set of back buffers. They should
1043 * all fit in this array. If they don't, separate DCC might never be
1044 * enabled by DCC stat gathering.
1047 struct r600_texture
*tex
;
1048 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1049 struct pipe_query
*ps_stats
[3];
1050 /* If all slots are used and another slot is needed,
1051 * the least recently used slot is evicted based on this. */
1052 int64_t last_use_timestamp
;
1056 /* Copy one resource to another using async DMA. */
1057 void (*dma_copy
)(struct pipe_context
*ctx
,
1058 struct pipe_resource
*dst
,
1060 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
1061 struct pipe_resource
*src
,
1063 const struct pipe_box
*src_box
);
1065 void (*dma_clear_buffer
)(struct si_context
*sctx
, struct pipe_resource
*dst
,
1066 uint64_t offset
, uint64_t size
, unsigned value
);
1070 void cik_init_sdma_functions(struct si_context
*sctx
);
1073 enum si_blitter_op
/* bitmask */
1075 SI_SAVE_TEXTURES
= 1,
1076 SI_SAVE_FRAMEBUFFER
= 2,
1077 SI_SAVE_FRAGMENT_STATE
= 4,
1078 SI_DISABLE_RENDER_COND
= 8,
1081 void si_blitter_begin(struct si_context
*sctx
, enum si_blitter_op op
);
1082 void si_blitter_end(struct si_context
*sctx
);
1083 void si_init_blit_functions(struct si_context
*sctx
);
1084 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
);
1085 void si_resource_copy_region(struct pipe_context
*ctx
,
1086 struct pipe_resource
*dst
,
1088 unsigned dstx
, unsigned dsty
, unsigned dstz
,
1089 struct pipe_resource
*src
,
1091 const struct pipe_box
*src_box
);
1092 void si_decompress_dcc(struct si_context
*sctx
, struct r600_texture
*rtex
);
1093 void si_blit_decompress_depth(struct pipe_context
*ctx
,
1094 struct r600_texture
*texture
,
1095 struct r600_texture
*staging
,
1096 unsigned first_level
, unsigned last_level
,
1097 unsigned first_layer
, unsigned last_layer
,
1098 unsigned first_sample
, unsigned last_sample
);
1101 bool si_rings_is_buffer_referenced(struct si_context
*sctx
,
1102 struct pb_buffer
*buf
,
1103 enum radeon_bo_usage usage
);
1104 void *si_buffer_map_sync_with_rings(struct si_context
*sctx
,
1105 struct r600_resource
*resource
,
1107 void si_init_resource_fields(struct si_screen
*sscreen
,
1108 struct r600_resource
*res
,
1109 uint64_t size
, unsigned alignment
);
1110 bool si_alloc_resource(struct si_screen
*sscreen
,
1111 struct r600_resource
*res
);
1112 struct pipe_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
,
1116 unsigned alignment
);
1117 void si_replace_buffer_storage(struct pipe_context
*ctx
,
1118 struct pipe_resource
*dst
,
1119 struct pipe_resource
*src
);
1120 void si_init_screen_buffer_functions(struct si_screen
*sscreen
);
1121 void si_init_buffer_functions(struct si_context
*sctx
);
1124 enum pipe_format
si_simplify_cb_format(enum pipe_format format
);
1125 bool vi_alpha_is_on_msb(enum pipe_format format
);
1126 void vi_dcc_clear_level(struct si_context
*sctx
,
1127 struct r600_texture
*rtex
,
1128 unsigned level
, unsigned clear_value
);
1129 void si_init_clear_functions(struct si_context
*sctx
);
1132 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1133 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1134 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1135 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1136 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1137 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1138 SI_CPDMA_SKIP_SYNC_AFTER | \
1139 SI_CPDMA_SKIP_SYNC_BEFORE | \
1140 SI_CPDMA_SKIP_GFX_SYNC | \
1141 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1144 SI_COHERENCY_NONE
, /* no cache flushes needed */
1145 SI_COHERENCY_SHADER
,
1146 SI_COHERENCY_CB_META
,
1149 void si_cp_dma_wait_for_idle(struct si_context
*sctx
);
1150 void si_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1151 uint64_t offset
, uint64_t size
, unsigned value
,
1152 enum si_coherency coher
);
1153 void si_copy_buffer(struct si_context
*sctx
,
1154 struct pipe_resource
*dst
, struct pipe_resource
*src
,
1155 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
1156 unsigned user_flags
);
1157 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
1158 uint64_t offset
, unsigned size
);
1159 void cik_emit_prefetch_L2(struct si_context
*sctx
, bool vertex_stage_only
);
1160 void si_init_cp_dma_functions(struct si_context
*sctx
);
1163 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_winsys_cs
*cs
,
1164 struct radeon_saved_cs
*saved
, bool get_buffer_list
);
1165 void si_clear_saved_cs(struct radeon_saved_cs
*saved
);
1166 void si_destroy_saved_cs(struct si_saved_cs
*scs
);
1167 void si_auto_log_cs(void *data
, struct u_log_context
*log
);
1168 void si_log_hw_flush(struct si_context
*sctx
);
1169 void si_log_draw_state(struct si_context
*sctx
, struct u_log_context
*log
);
1170 void si_log_compute_state(struct si_context
*sctx
, struct u_log_context
*log
);
1171 void si_init_debug_functions(struct si_context
*sctx
);
1172 void si_check_vm_faults(struct si_context
*sctx
,
1173 struct radeon_saved_cs
*saved
, enum ring_type ring
);
1174 bool si_replace_shader(unsigned num
, struct ac_shader_binary
*binary
);
1177 void si_init_dma_functions(struct si_context
*sctx
);
1180 void si_need_dma_space(struct si_context
*ctx
, unsigned num_dw
,
1181 struct r600_resource
*dst
, struct r600_resource
*src
);
1182 void si_flush_dma_cs(struct si_context
*ctx
, unsigned flags
,
1183 struct pipe_fence_handle
**fence
);
1184 void si_screen_clear_buffer(struct si_screen
*sscreen
, struct pipe_resource
*dst
,
1185 uint64_t offset
, uint64_t size
, unsigned value
);
1188 void si_gfx_write_event_eop(struct si_context
*ctx
,
1189 unsigned event
, unsigned event_flags
,
1191 struct r600_resource
*buf
, uint64_t va
,
1192 uint32_t new_fence
, unsigned query_type
);
1193 unsigned si_gfx_write_fence_dwords(struct si_screen
*screen
);
1194 void si_gfx_wait_fence(struct si_context
*ctx
,
1195 uint64_t va
, uint32_t ref
, uint32_t mask
);
1196 void si_init_fence_functions(struct si_context
*ctx
);
1197 void si_init_screen_fence_functions(struct si_screen
*screen
);
1198 struct pipe_fence_handle
*si_create_fence(struct pipe_context
*ctx
,
1199 struct tc_unflushed_batch_token
*tc_token
);
1202 const char *si_get_family_name(const struct si_screen
*sscreen
);
1203 void si_init_screen_get_functions(struct si_screen
*sscreen
);
1206 void si_flush_gfx_cs(struct si_context
*ctx
, unsigned flags
,
1207 struct pipe_fence_handle
**fence
);
1208 void si_begin_new_gfx_cs(struct si_context
*ctx
);
1209 void si_need_gfx_cs_space(struct si_context
*ctx
);
1211 /* r600_gpu_load.c */
1212 void si_gpu_load_kill_thread(struct si_screen
*sscreen
);
1213 uint64_t si_begin_counter(struct si_screen
*sscreen
, unsigned type
);
1214 unsigned si_end_counter(struct si_screen
*sscreen
, unsigned type
,
1218 void si_init_compute_functions(struct si_context
*sctx
);
1220 /* r600_perfcounters.c */
1221 void si_perfcounters_destroy(struct si_screen
*sscreen
);
1223 /* si_perfcounters.c */
1224 void si_init_perfcounters(struct si_screen
*screen
);
1227 bool si_check_device_reset(struct si_context
*sctx
);
1230 void si_init_screen_query_functions(struct si_screen
*sscreen
);
1231 void si_init_query_functions(struct si_context
*sctx
);
1232 void si_suspend_queries(struct si_context
*sctx
);
1233 void si_resume_queries(struct si_context
*sctx
);
1236 void si_test_dma(struct si_screen
*sscreen
);
1239 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
1240 const struct pipe_video_codec
*templ
);
1242 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
1243 const struct pipe_video_buffer
*tmpl
);
1246 void si_update_vs_viewport_state(struct si_context
*ctx
);
1247 void si_init_viewport_functions(struct si_context
*ctx
);
1249 /* r600_texture.c */
1250 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
1251 struct r600_texture
*rdst
,
1252 unsigned dst_level
, unsigned dstx
,
1253 unsigned dsty
, unsigned dstz
,
1254 struct r600_texture
*rsrc
,
1256 const struct pipe_box
*src_box
);
1257 void si_texture_get_fmask_info(struct si_screen
*sscreen
,
1258 struct r600_texture
*rtex
,
1259 unsigned nr_samples
,
1260 struct r600_fmask_info
*out
);
1261 void si_texture_get_cmask_info(struct si_screen
*sscreen
,
1262 struct r600_texture
*rtex
,
1263 struct r600_cmask_info
*out
);
1264 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
1265 struct r600_texture
*rtex
);
1266 void si_texture_discard_cmask(struct si_screen
*sscreen
,
1267 struct r600_texture
*rtex
);
1268 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1269 struct pipe_resource
*texture
,
1270 struct r600_texture
**staging
);
1271 void si_print_texture_info(struct si_screen
*sscreen
,
1272 struct r600_texture
*rtex
, struct u_log_context
*log
);
1273 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1274 const struct pipe_resource
*templ
);
1275 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1276 enum pipe_format format2
);
1277 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1279 enum pipe_format view_format
);
1280 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
1281 struct pipe_resource
*tex
,
1283 enum pipe_format view_format
);
1284 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1285 struct pipe_resource
*texture
,
1286 const struct pipe_surface
*templ
,
1287 unsigned width0
, unsigned height0
,
1288 unsigned width
, unsigned height
);
1289 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
1290 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
1291 struct r600_texture
*tex
);
1292 void vi_separate_dcc_start_query(struct si_context
*sctx
,
1293 struct r600_texture
*tex
);
1294 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
1295 struct r600_texture
*tex
);
1296 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
1297 struct r600_texture
*tex
);
1298 bool si_texture_disable_dcc(struct si_context
*sctx
,
1299 struct r600_texture
*rtex
);
1300 void si_init_screen_texture_functions(struct si_screen
*sscreen
);
1301 void si_init_context_texture_functions(struct si_context
*sctx
);
1308 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
1310 return (struct r600_resource
*)r
;
1314 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
1316 pipe_resource_reference((struct pipe_resource
**)ptr
,
1317 (struct pipe_resource
*)res
);
1321 r600_texture_reference(struct r600_texture
**ptr
, struct r600_texture
*res
)
1323 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->resource
.b
.b
);
1327 vi_dcc_enabled(struct r600_texture
*tex
, unsigned level
)
1329 return tex
->dcc_offset
&& level
< tex
->surface
.num_dcc_levels
;
1332 static inline unsigned
1333 si_tile_mode_index(struct r600_texture
*rtex
, unsigned level
, bool stencil
)
1336 return rtex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
1338 return rtex
->surface
.u
.legacy
.tiling_index
[level
];
1342 si_context_add_resource_size(struct si_context
*sctx
, struct pipe_resource
*r
)
1344 struct r600_resource
*res
= (struct r600_resource
*)r
;
1347 /* Add memory usage for need_gfx_cs_space */
1348 sctx
->vram
+= res
->vram_usage
;
1349 sctx
->gtt
+= res
->gart_usage
;
1354 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
1356 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
1360 si_set_atom_dirty(struct si_context
*sctx
,
1361 struct si_atom
*atom
, bool dirty
)
1363 unsigned bit
= 1 << atom
->id
;
1366 sctx
->dirty_atoms
|= bit
;
1368 sctx
->dirty_atoms
&= ~bit
;
1372 si_is_atom_dirty(struct si_context
*sctx
,
1373 struct si_atom
*atom
)
1375 unsigned bit
= 1 << atom
->id
;
1377 return sctx
->dirty_atoms
& bit
;
1381 si_mark_atom_dirty(struct si_context
*sctx
,
1382 struct si_atom
*atom
)
1384 si_set_atom_dirty(sctx
, atom
, true);
1387 static inline struct si_shader_ctx_state
*si_get_vs(struct si_context
*sctx
)
1389 if (sctx
->gs_shader
.cso
)
1390 return &sctx
->gs_shader
;
1391 if (sctx
->tes_shader
.cso
)
1392 return &sctx
->tes_shader
;
1394 return &sctx
->vs_shader
;
1397 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
1399 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1401 return vs
->cso
? &vs
->cso
->info
: NULL
;
1404 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
1406 if (sctx
->gs_shader
.cso
)
1407 return sctx
->gs_shader
.cso
->gs_copy_shader
;
1409 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1410 return vs
->current
? vs
->current
: NULL
;
1413 static inline bool si_can_dump_shader(struct si_screen
*sscreen
,
1416 return sscreen
->debug_flags
& (1 << processor
);
1419 static inline bool si_extra_shader_checks(struct si_screen
*sscreen
,
1422 return (sscreen
->debug_flags
& DBG(CHECK_IR
)) ||
1423 si_can_dump_shader(sscreen
, processor
);
1426 static inline bool si_get_strmout_en(struct si_context
*sctx
)
1428 return sctx
->streamout
.streamout_enabled
||
1429 sctx
->streamout
.prims_gen_query_enabled
;
1432 static inline unsigned
1433 si_optimal_tcc_alignment(struct si_context
*sctx
, unsigned upload_size
)
1435 unsigned alignment
, tcc_cache_line_size
;
1437 /* If the upload size is less than the cache line size (e.g. 16, 32),
1438 * the whole thing will fit into a cache line if we align it to its size.
1439 * The idea is that multiple small uploads can share a cache line.
1440 * If the upload size is greater, align it to the cache line size.
1442 alignment
= util_next_power_of_two(upload_size
);
1443 tcc_cache_line_size
= sctx
->screen
->info
.tcc_cache_line_size
;
1444 return MIN2(alignment
, tcc_cache_line_size
);
1448 si_saved_cs_reference(struct si_saved_cs
**dst
, struct si_saved_cs
*src
)
1450 if (pipe_reference(&(*dst
)->reference
, &src
->reference
))
1451 si_destroy_saved_cs(*dst
);
1457 si_make_CB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1458 bool shaders_read_metadata
)
1460 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
|
1461 SI_CONTEXT_INV_VMEM_L1
;
1463 if (sctx
->chip_class
>= GFX9
) {
1464 /* Single-sample color is coherent with shaders on GFX9, but
1465 * L2 metadata must be flushed if shaders read metadata.
1468 if (num_samples
>= 2)
1469 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1470 else if (shaders_read_metadata
)
1471 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1474 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1479 si_make_DB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1480 bool include_stencil
, bool shaders_read_metadata
)
1482 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB
|
1483 SI_CONTEXT_INV_VMEM_L1
;
1485 if (sctx
->chip_class
>= GFX9
) {
1486 /* Single-sample depth (not stencil) is coherent with shaders
1487 * on GFX9, but L2 metadata must be flushed if shaders read
1490 if (num_samples
>= 2 || include_stencil
)
1491 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1492 else if (shaders_read_metadata
)
1493 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1496 sctx
->flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
1501 si_can_sample_zs(struct r600_texture
*tex
, bool stencil_sampler
)
1503 return (stencil_sampler
&& tex
->can_sample_s
) ||
1504 (!stencil_sampler
&& tex
->can_sample_z
);
1508 si_htile_enabled(struct r600_texture
*tex
, unsigned level
)
1510 return tex
->htile_offset
&& level
== 0;
1514 vi_tc_compat_htile_enabled(struct r600_texture
*tex
, unsigned level
)
1516 assert(!tex
->tc_compatible_htile
|| tex
->htile_offset
);
1517 return tex
->tc_compatible_htile
&& level
== 0;
1520 static inline unsigned si_get_ps_iter_samples(struct si_context
*sctx
)
1522 if (sctx
->ps_uses_fbfetch
)
1523 return sctx
->framebuffer
.nr_samples
;
1525 return sctx
->ps_iter_samples
;
1528 static inline unsigned si_get_total_colormask(struct si_context
*sctx
)
1530 if (sctx
->queued
.named
.rasterizer
->rasterizer_discard
)
1533 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1537 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
1538 sctx
->queued
.named
.blend
->cb_target_mask
;
1540 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
1541 colormask
&= ps
->colors_written_4bit
;
1542 else if (!ps
->colors_written_4bit
)
1543 colormask
= 0; /* color0 writes all cbufs, but it's not written */
1549 * Return true if there is enough memory in VRAM and GTT for the buffers
1552 * \param vram VRAM memory size not added to the buffer list yet
1553 * \param gtt GTT memory size not added to the buffer list yet
1556 radeon_cs_memory_below_limit(struct si_screen
*screen
,
1557 struct radeon_winsys_cs
*cs
,
1558 uint64_t vram
, uint64_t gtt
)
1560 vram
+= cs
->used_vram
;
1561 gtt
+= cs
->used_gart
;
1563 /* Anything that goes above the VRAM size should go to GTT. */
1564 if (vram
> screen
->info
.vram_size
)
1565 gtt
+= vram
- screen
->info
.vram_size
;
1567 /* Now we just need to check if we have enough GTT. */
1568 return gtt
< screen
->info
.gart_size
* 0.7;
1572 * Add a buffer to the buffer list for the given command stream (CS).
1574 * All buffers used by a CS must be added to the list. This tells the kernel
1575 * driver which buffers are used by GPU commands. Other buffers can
1576 * be swapped out (not accessible) during execution.
1578 * The buffer list becomes empty after every context flush and must be
1581 static inline void radeon_add_to_buffer_list(struct si_context
*sctx
,
1582 struct radeon_winsys_cs
*cs
,
1583 struct r600_resource
*rbo
,
1584 enum radeon_bo_usage usage
,
1585 enum radeon_bo_priority priority
)
1588 sctx
->ws
->cs_add_buffer(
1590 (enum radeon_bo_usage
)(usage
| RADEON_USAGE_SYNCHRONIZED
),
1591 rbo
->domains
, priority
);
1595 * Same as above, but also checks memory usage and flushes the context
1598 * When this SHOULD NOT be used:
1600 * - if si_context_add_resource_size has been called for the buffer
1601 * followed by *_need_cs_space for checking the memory usage
1603 * - if si_need_dma_space has been called for the buffer
1605 * - when emitting state packets and draw packets (because preceding packets
1606 * can't be re-emitted at that point)
1608 * - if shader resource "enabled_mask" is not up-to-date or there is
1609 * a different constraint disallowing a context flush
1612 radeon_add_to_gfx_buffer_list_check_mem(struct si_context
*sctx
,
1613 struct r600_resource
*rbo
,
1614 enum radeon_bo_usage usage
,
1615 enum radeon_bo_priority priority
,
1619 !radeon_cs_memory_below_limit(sctx
->screen
, sctx
->gfx_cs
,
1620 sctx
->vram
+ rbo
->vram_usage
,
1621 sctx
->gtt
+ rbo
->gart_usage
))
1622 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1624 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, rbo
, usage
, priority
);
1627 #define PRINT_ERR(fmt, args...) \
1628 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)