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radeonsi/gfx10: add global use_ngg and use_ngg_streamout flags
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
34
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
37 #else
38 #define SI_BIG_ENDIAN 0
39 #endif
40
41 #define ATI_VENDOR_ID 0x1002
42 #define SI_PRIM_DISCARD_DEBUG 0
43 #define SI_NOT_QUERY 0xffffffff
44
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
56
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
61
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
69 * GFX10: This also invalidates the L1 shader array cache. */
70 #define SI_CONTEXT_INV_SCACHE (1 << 4)
71 /* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
72 * GFX10: This also invalidates the L1 shader array cache. */
73 #define SI_CONTEXT_INV_VCACHE (1 << 5)
74 /* L2 cache + L2 metadata cache writeback & invalidate.
75 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
76 #define SI_CONTEXT_INV_L2 (1 << 6)
77 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
78 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
79 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
80 #define SI_CONTEXT_WB_L2 (1 << 7)
81 /* Writeback & invalidate the L2 metadata cache only. It can only be coupled with
82 * a CB or DB flush. */
83 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
84 /* Framebuffer caches. */
85 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
86 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
87 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
88 /* Engine synchronization. */
89 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
90 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
91 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
92 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
93 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
94
95 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
96 #define SI_PREFETCH_LS (1 << 1)
97 #define SI_PREFETCH_HS (1 << 2)
98 #define SI_PREFETCH_ES (1 << 3)
99 #define SI_PREFETCH_GS (1 << 4)
100 #define SI_PREFETCH_VS (1 << 5)
101 #define SI_PREFETCH_PS (1 << 6)
102
103 #define SI_MAX_BORDER_COLORS 4096
104 #define SI_MAX_VIEWPORTS 16
105 #define SIX_BITS 0x3F
106 #define SI_MAP_BUFFER_ALIGNMENT 64
107 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
108
109 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
110 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
111 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
112 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
113 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
114 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
115 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
116 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
117 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
118 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
119
120 enum si_clear_code
121 {
122 DCC_CLEAR_COLOR_0000 = 0x00000000,
123 DCC_CLEAR_COLOR_0001 = 0x40404040,
124 DCC_CLEAR_COLOR_1110 = 0x80808080,
125 DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
126 DCC_CLEAR_COLOR_REG = 0x20202020,
127 DCC_UNCOMPRESSED = 0xFFFFFFFF,
128 };
129
130 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
131
132 /* Debug flags. */
133 enum {
134 /* Shader logging options: */
135 DBG_VS = PIPE_SHADER_VERTEX,
136 DBG_PS = PIPE_SHADER_FRAGMENT,
137 DBG_GS = PIPE_SHADER_GEOMETRY,
138 DBG_TCS = PIPE_SHADER_TESS_CTRL,
139 DBG_TES = PIPE_SHADER_TESS_EVAL,
140 DBG_CS = PIPE_SHADER_COMPUTE,
141 DBG_NO_IR,
142 DBG_NO_TGSI,
143 DBG_NO_ASM,
144 DBG_PREOPT_IR,
145
146 /* Shader compiler options the shader cache should be aware of: */
147 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
148 DBG_UNSAFE_MATH,
149 DBG_SI_SCHED,
150 DBG_GISEL,
151 DBG_W32_GE,
152 DBG_W32_PS,
153 DBG_W32_CS,
154 DBG_W64_GE,
155 DBG_W64_PS,
156 DBG_W64_CS,
157
158 /* Shader compiler options (with no effect on the shader cache): */
159 DBG_CHECK_IR,
160 DBG_MONOLITHIC_SHADERS,
161 DBG_NO_OPT_VARIANT,
162
163 /* Information logging options: */
164 DBG_INFO,
165 DBG_TEX,
166 DBG_COMPUTE,
167 DBG_VM,
168
169 /* Driver options: */
170 DBG_FORCE_DMA,
171 DBG_NO_ASYNC_DMA,
172 DBG_NO_WC,
173 DBG_CHECK_VM,
174 DBG_RESERVE_VMID,
175 DBG_ZERO_VRAM,
176
177 /* 3D engine options: */
178 DBG_NO_GFX,
179 DBG_ALWAYS_PD,
180 DBG_PD,
181 DBG_NO_PD,
182 DBG_SWITCH_ON_EOP,
183 DBG_NO_OUT_OF_ORDER,
184 DBG_NO_DPBB,
185 DBG_NO_DFSM,
186 DBG_DPBB,
187 DBG_DFSM,
188 DBG_NO_HYPERZ,
189 DBG_NO_RB_PLUS,
190 DBG_NO_2D_TILING,
191 DBG_NO_TILING,
192 DBG_NO_DCC,
193 DBG_NO_DCC_CLEAR,
194 DBG_NO_DCC_FB,
195 DBG_NO_DCC_MSAA,
196 DBG_NO_FMASK,
197
198 /* Tests: */
199 DBG_TEST_DMA,
200 DBG_TEST_VMFAULT_CP,
201 DBG_TEST_VMFAULT_SDMA,
202 DBG_TEST_VMFAULT_SHADER,
203 DBG_TEST_DMA_PERF,
204 DBG_TEST_GDS,
205 DBG_TEST_GDS_MM,
206 DBG_TEST_GDS_OA_MM,
207 };
208
209 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
210 #define DBG(name) (1ull << DBG_##name)
211
212 enum si_cache_policy {
213 L2_BYPASS,
214 L2_STREAM, /* same as SLC=1 */
215 L2_LRU, /* same as SLC=0 */
216 };
217
218 enum si_coherency {
219 SI_COHERENCY_NONE, /* no cache flushes needed */
220 SI_COHERENCY_SHADER,
221 SI_COHERENCY_CB_META,
222 SI_COHERENCY_CP,
223 };
224
225 struct si_compute;
226 struct si_shader_context;
227 struct hash_table;
228 struct u_suballocator;
229
230 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
231 * at the moment.
232 */
233 struct si_resource {
234 struct threaded_resource b;
235
236 /* Winsys objects. */
237 struct pb_buffer *buf;
238 uint64_t gpu_address;
239 /* Memory usage if the buffer placement is optimal. */
240 uint64_t vram_usage;
241 uint64_t gart_usage;
242
243 /* Resource properties. */
244 uint64_t bo_size;
245 unsigned bo_alignment;
246 enum radeon_bo_domain domains;
247 enum radeon_bo_flag flags;
248 unsigned bind_history;
249 int max_forced_staging_uploads;
250
251 /* The buffer range which is initialized (with a write transfer,
252 * streamout, DMA, or as a random access target). The rest of
253 * the buffer is considered invalid and can be mapped unsynchronized.
254 *
255 * This allows unsychronized mapping of a buffer range which hasn't
256 * been used yet. It's for applications which forget to use
257 * the unsynchronized map flag and expect the driver to figure it out.
258 */
259 struct util_range valid_buffer_range;
260
261 /* For buffers only. This indicates that a write operation has been
262 * performed by TC L2, but the cache hasn't been flushed.
263 * Any hw block which doesn't use or bypasses TC L2 should check this
264 * flag and flush the cache before using the buffer.
265 *
266 * For example, TC L2 must be flushed if a buffer which has been
267 * modified by a shader store instruction is about to be used as
268 * an index buffer. The reason is that VGT DMA index fetching doesn't
269 * use TC L2.
270 */
271 bool TC_L2_dirty;
272
273 /* Whether this resource is referenced by bindless handles. */
274 bool texture_handle_allocated;
275 bool image_handle_allocated;
276
277 /* Whether the resource has been exported via resource_get_handle. */
278 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
279 };
280
281 struct si_transfer {
282 struct threaded_transfer b;
283 struct si_resource *staging;
284 unsigned offset;
285 };
286
287 struct si_texture {
288 struct si_resource buffer;
289
290 struct radeon_surf surface;
291 uint64_t size;
292 struct si_texture *flushed_depth_texture;
293
294 /* One texture allocation can contain these buffers:
295 * - image (pixel data)
296 * - FMASK buffer (MSAA compression)
297 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
298 * - HTILE buffer (Z/S compression and fast Z/S clear)
299 * - DCC buffer (color compression and new fast color clear)
300 * - displayable DCC buffer (if the DCC buffer is not displayable)
301 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
302 */
303 uint64_t fmask_offset;
304 uint64_t cmask_offset;
305 uint64_t cmask_base_address_reg;
306 struct si_resource *cmask_buffer;
307 uint64_t dcc_offset; /* 0 = disabled */
308 uint64_t display_dcc_offset;
309 uint64_t dcc_retile_map_offset;
310 unsigned cb_color_info; /* fast clear enable bit */
311 unsigned color_clear_value[2];
312 unsigned last_msaa_resolve_target_micro_mode;
313 unsigned num_level0_transfers;
314
315 /* Depth buffer compression and fast clear. */
316 uint64_t htile_offset;
317 float depth_clear_value;
318 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
319 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
320 enum pipe_format db_render_format:16;
321 uint8_t stencil_clear_value;
322 bool tc_compatible_htile:1;
323 bool htile_stencil_disabled:1;
324 bool depth_cleared:1; /* if it was cleared at least once */
325 bool stencil_cleared:1; /* if it was cleared at least once */
326 bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
327 bool is_depth:1;
328 bool db_compatible:1;
329 bool can_sample_z:1;
330 bool can_sample_s:1;
331
332 /* We need to track DCC dirtiness, because st/dri usually calls
333 * flush_resource twice per frame (not a bug) and we don't wanna
334 * decompress DCC twice. Also, the dirty tracking must be done even
335 * if DCC isn't used, because it's required by the DCC usage analysis
336 * for a possible future enablement.
337 */
338 bool separate_dcc_dirty:1;
339 /* Statistics gathering for the DCC enablement heuristic. */
340 bool dcc_gather_statistics:1;
341 /* Counter that should be non-zero if the texture is bound to a
342 * framebuffer.
343 */
344 unsigned framebuffers_bound;
345 /* Whether the texture is a displayable back buffer and needs DCC
346 * decompression, which is expensive. Therefore, it's enabled only
347 * if statistics suggest that it will pay off and it's allocated
348 * separately. It can't be bound as a sampler by apps. Limited to
349 * target == 2D and last_level == 0. If enabled, dcc_offset contains
350 * the absolute GPUVM address, not the relative one.
351 */
352 struct si_resource *dcc_separate_buffer;
353 /* When DCC is temporarily disabled, the separate buffer is here. */
354 struct si_resource *last_dcc_separate_buffer;
355 /* Estimate of how much this color buffer is written to in units of
356 * full-screen draws: ps_invocations / (width * height)
357 * Shader kills, late Z, and blending with trivial discards make it
358 * inaccurate (we need to count CB updates, not PS invocations).
359 */
360 unsigned ps_draw_ratio;
361 /* The number of clears since the last DCC usage analysis. */
362 unsigned num_slow_clears;
363 };
364
365 struct si_surface {
366 struct pipe_surface base;
367
368 /* These can vary with block-compressed textures. */
369 uint16_t width0;
370 uint16_t height0;
371
372 bool color_initialized:1;
373 bool depth_initialized:1;
374
375 /* Misc. color flags. */
376 bool color_is_int8:1;
377 bool color_is_int10:1;
378 bool dcc_incompatible:1;
379
380 /* Color registers. */
381 unsigned cb_color_info;
382 unsigned cb_color_view;
383 unsigned cb_color_attrib;
384 unsigned cb_color_attrib2; /* GFX9 and later */
385 unsigned cb_color_attrib3; /* GFX10 and later */
386 unsigned cb_dcc_control; /* GFX8 and later */
387 unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */
388 unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
389 unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
390 unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
391
392 /* DB registers. */
393 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
394 uint64_t db_stencil_base;
395 uint64_t db_htile_data_base;
396 unsigned db_depth_info;
397 unsigned db_z_info;
398 unsigned db_z_info2; /* GFX9 only */
399 unsigned db_depth_view;
400 unsigned db_depth_size;
401 unsigned db_depth_slice;
402 unsigned db_stencil_info;
403 unsigned db_stencil_info2; /* GFX9 only */
404 unsigned db_htile_surface;
405 };
406
407 struct si_mmio_counter {
408 unsigned busy;
409 unsigned idle;
410 };
411
412 union si_mmio_counters {
413 struct {
414 /* For global GPU load including SDMA. */
415 struct si_mmio_counter gpu;
416
417 /* GRBM_STATUS */
418 struct si_mmio_counter spi;
419 struct si_mmio_counter gui;
420 struct si_mmio_counter ta;
421 struct si_mmio_counter gds;
422 struct si_mmio_counter vgt;
423 struct si_mmio_counter ia;
424 struct si_mmio_counter sx;
425 struct si_mmio_counter wd;
426 struct si_mmio_counter bci;
427 struct si_mmio_counter sc;
428 struct si_mmio_counter pa;
429 struct si_mmio_counter db;
430 struct si_mmio_counter cp;
431 struct si_mmio_counter cb;
432
433 /* SRBM_STATUS2 */
434 struct si_mmio_counter sdma;
435
436 /* CP_STAT */
437 struct si_mmio_counter pfp;
438 struct si_mmio_counter meq;
439 struct si_mmio_counter me;
440 struct si_mmio_counter surf_sync;
441 struct si_mmio_counter cp_dma;
442 struct si_mmio_counter scratch_ram;
443 } named;
444 unsigned array[0];
445 };
446
447 struct si_memory_object {
448 struct pipe_memory_object b;
449 struct pb_buffer *buf;
450 uint32_t stride;
451 };
452
453 /* Saved CS data for debugging features. */
454 struct radeon_saved_cs {
455 uint32_t *ib;
456 unsigned num_dw;
457
458 struct radeon_bo_list_item *bo_list;
459 unsigned bo_count;
460 };
461
462 struct si_screen {
463 struct pipe_screen b;
464 struct radeon_winsys *ws;
465 struct disk_cache *disk_shader_cache;
466
467 struct radeon_info info;
468 uint64_t debug_flags;
469 char renderer_string[183];
470
471 void (*make_texture_descriptor)(
472 struct si_screen *screen,
473 struct si_texture *tex,
474 bool sampler,
475 enum pipe_texture_target target,
476 enum pipe_format pipe_format,
477 const unsigned char state_swizzle[4],
478 unsigned first_level, unsigned last_level,
479 unsigned first_layer, unsigned last_layer,
480 unsigned width, unsigned height, unsigned depth,
481 uint32_t *state,
482 uint32_t *fmask_state);
483
484 unsigned pa_sc_raster_config;
485 unsigned pa_sc_raster_config_1;
486 unsigned se_tile_repeat;
487 unsigned gs_table_depth;
488 unsigned tess_offchip_block_dw_size;
489 unsigned tess_offchip_ring_size;
490 unsigned tess_factor_ring_size;
491 unsigned vgt_hs_offchip_param;
492 unsigned eqaa_force_coverage_samples;
493 unsigned eqaa_force_z_samples;
494 unsigned eqaa_force_color_samples;
495 bool has_clear_state;
496 bool has_distributed_tess;
497 bool has_draw_indirect_multi;
498 bool has_out_of_order_rast;
499 bool assume_no_z_fights;
500 bool commutative_blend_add;
501 bool has_gfx9_scissor_bug;
502 bool has_msaa_sample_loc_bug;
503 bool has_ls_vgpr_init_bug;
504 bool has_dcc_constant_encode;
505 bool dpbb_allowed;
506 bool dfsm_allowed;
507 bool llvm_has_working_vgpr_indexing;
508 bool use_ngg;
509 bool use_ngg_streamout;
510
511 struct {
512 #define OPT_BOOL(name, dflt, description) bool name:1;
513 #include "si_debug_options.h"
514 } options;
515
516 /* Whether shaders are monolithic (1-part) or separate (3-part). */
517 bool use_monolithic_shaders;
518 bool record_llvm_ir;
519 bool has_rbplus; /* if RB+ registers exist */
520 bool rbplus_allowed; /* if RB+ is allowed */
521 bool dcc_msaa_allowed;
522 bool cpdma_prefetch_writes_memory;
523
524 struct slab_parent_pool pool_transfers;
525
526 /* Texture filter settings. */
527 int force_aniso; /* -1 = disabled */
528
529 /* Auxiliary context. Mainly used to initialize resources.
530 * It must be locked prior to using and flushed before unlocking. */
531 struct pipe_context *aux_context;
532 mtx_t aux_context_lock;
533
534 /* This must be in the screen, because UE4 uses one context for
535 * compilation and another one for rendering.
536 */
537 unsigned num_compilations;
538 /* Along with ST_DEBUG=precompile, this should show if applications
539 * are loading shaders on demand. This is a monotonic counter.
540 */
541 unsigned num_shaders_created;
542 unsigned num_shader_cache_hits;
543
544 /* GPU load thread. */
545 mtx_t gpu_load_mutex;
546 thrd_t gpu_load_thread;
547 union si_mmio_counters mmio_counters;
548 volatile unsigned gpu_load_stop_thread; /* bool */
549
550 /* Performance counters. */
551 struct si_perfcounters *perfcounters;
552
553 /* If pipe_screen wants to recompute and re-emit the framebuffer,
554 * sampler, and image states of all contexts, it should atomically
555 * increment this.
556 *
557 * Each context will compare this with its own last known value of
558 * the counter before drawing and re-emit the states accordingly.
559 */
560 unsigned dirty_tex_counter;
561 unsigned dirty_buf_counter;
562
563 /* Atomically increment this counter when an existing texture's
564 * metadata is enabled or disabled in a way that requires changing
565 * contexts' compressed texture binding masks.
566 */
567 unsigned compressed_colortex_counter;
568
569 struct {
570 /* Context flags to set so that all writes from earlier jobs
571 * in the CP are seen by L2 clients.
572 */
573 unsigned cp_to_L2;
574
575 /* Context flags to set so that all writes from earlier jobs
576 * that end in L2 are seen by CP.
577 */
578 unsigned L2_to_cp;
579 } barrier_flags;
580
581 mtx_t shader_parts_mutex;
582 struct si_shader_part *vs_prologs;
583 struct si_shader_part *tcs_epilogs;
584 struct si_shader_part *gs_prologs;
585 struct si_shader_part *ps_prologs;
586 struct si_shader_part *ps_epilogs;
587
588 /* Shader cache in memory.
589 *
590 * Design & limitations:
591 * - The shader cache is per screen (= per process), never saved to
592 * disk, and skips redundant shader compilations from TGSI to bytecode.
593 * - It can only be used with one-variant-per-shader support, in which
594 * case only the main (typically middle) part of shaders is cached.
595 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
596 * variants of VS and TES are cached, so LS and ES aren't.
597 * - GS and CS aren't cached, but it's certainly possible to cache
598 * those as well.
599 */
600 mtx_t shader_cache_mutex;
601 struct hash_table *shader_cache;
602
603 /* Shader compiler queue for multithreaded compilation. */
604 struct util_queue shader_compiler_queue;
605 /* Use at most 3 normal compiler threads on quadcore and better.
606 * Hyperthreaded CPUs report the number of threads, but we want
607 * the number of cores. We only need this many threads for shader-db. */
608 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
609
610 struct util_queue shader_compiler_queue_low_priority;
611 /* Use at most 2 low priority threads on quadcore and better.
612 * We want to minimize the impact on multithreaded Mesa. */
613 struct ac_llvm_compiler compiler_lowp[10];
614
615 unsigned compute_wave_size;
616 unsigned ps_wave_size;
617 unsigned ge_wave_size;
618 };
619
620 struct si_blend_color {
621 struct pipe_blend_color state;
622 bool any_nonzeros;
623 };
624
625 struct si_sampler_view {
626 struct pipe_sampler_view base;
627 /* [0..7] = image descriptor
628 * [4..7] = buffer descriptor */
629 uint32_t state[8];
630 uint32_t fmask_state[8];
631 const struct legacy_surf_level *base_level_info;
632 ubyte base_level;
633 ubyte block_width;
634 bool is_stencil_sampler;
635 bool is_integer;
636 bool dcc_incompatible;
637 };
638
639 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
640
641 struct si_sampler_state {
642 #ifndef NDEBUG
643 unsigned magic;
644 #endif
645 uint32_t val[4];
646 uint32_t integer_val[4];
647 uint32_t upgraded_depth_val[4];
648 };
649
650 struct si_cs_shader_state {
651 struct si_compute *program;
652 struct si_compute *emitted_program;
653 unsigned offset;
654 bool initialized;
655 bool uses_scratch;
656 };
657
658 struct si_samplers {
659 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
660 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
661
662 /* The i-th bit is set if that element is enabled (non-NULL resource). */
663 unsigned enabled_mask;
664 uint32_t needs_depth_decompress_mask;
665 uint32_t needs_color_decompress_mask;
666 };
667
668 struct si_images {
669 struct pipe_image_view views[SI_NUM_IMAGES];
670 uint32_t needs_color_decompress_mask;
671 unsigned enabled_mask;
672 };
673
674 struct si_framebuffer {
675 struct pipe_framebuffer_state state;
676 unsigned colorbuf_enabled_4bit;
677 unsigned spi_shader_col_format;
678 unsigned spi_shader_col_format_alpha;
679 unsigned spi_shader_col_format_blend;
680 unsigned spi_shader_col_format_blend_alpha;
681 ubyte nr_samples:5; /* at most 16xAA */
682 ubyte log_samples:3; /* at most 4 = 16xAA */
683 ubyte nr_color_samples; /* at most 8xAA */
684 ubyte compressed_cb_mask;
685 ubyte uncompressed_cb_mask;
686 ubyte color_is_int8;
687 ubyte color_is_int10;
688 ubyte dirty_cbufs;
689 ubyte dcc_overwrite_combiner_watermark;
690 ubyte min_bytes_per_pixel;
691 bool dirty_zsbuf;
692 bool any_dst_linear;
693 bool CB_has_shader_readable_metadata;
694 bool DB_has_shader_readable_metadata;
695 bool all_DCC_pipe_aligned;
696 };
697
698 enum si_quant_mode {
699 /* This is the list we want to support. */
700 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
701 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
702 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
703 };
704
705 struct si_signed_scissor {
706 int minx;
707 int miny;
708 int maxx;
709 int maxy;
710 enum si_quant_mode quant_mode;
711 };
712
713 struct si_viewports {
714 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
715 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
716 bool y_inverted;
717 };
718
719 struct si_clip_state {
720 struct pipe_clip_state state;
721 bool any_nonzeros;
722 };
723
724 struct si_streamout_target {
725 struct pipe_stream_output_target b;
726
727 /* The buffer where BUFFER_FILLED_SIZE is stored. */
728 struct si_resource *buf_filled_size;
729 unsigned buf_filled_size_offset;
730 bool buf_filled_size_valid;
731
732 unsigned stride_in_dw;
733 };
734
735 struct si_streamout {
736 bool begin_emitted;
737
738 unsigned enabled_mask;
739 unsigned num_targets;
740 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
741
742 unsigned append_bitmask;
743 bool suspended;
744
745 /* External state which comes from the vertex shader,
746 * it must be set explicitly when binding a shader. */
747 uint16_t *stride_in_dw;
748 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
749
750 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
751 unsigned hw_enabled_mask;
752
753 /* The state of VGT_STRMOUT_(CONFIG|EN). */
754 bool streamout_enabled;
755 bool prims_gen_query_enabled;
756 int num_prims_gen_queries;
757 };
758
759 /* A shader state consists of the shader selector, which is a constant state
760 * object shared by multiple contexts and shouldn't be modified, and
761 * the current shader variant selected for this context.
762 */
763 struct si_shader_ctx_state {
764 struct si_shader_selector *cso;
765 struct si_shader *current;
766 };
767
768 #define SI_NUM_VGT_PARAM_KEY_BITS 12
769 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
770
771 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
772 * Some fields are set by state-change calls, most are set by draw_vbo.
773 */
774 union si_vgt_param_key {
775 struct {
776 #ifdef PIPE_ARCH_LITTLE_ENDIAN
777 unsigned prim:4;
778 unsigned uses_instancing:1;
779 unsigned multi_instances_smaller_than_primgroup:1;
780 unsigned primitive_restart:1;
781 unsigned count_from_stream_output:1;
782 unsigned line_stipple_enabled:1;
783 unsigned uses_tess:1;
784 unsigned tess_uses_prim_id:1;
785 unsigned uses_gs:1;
786 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
787 #else /* PIPE_ARCH_BIG_ENDIAN */
788 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
789 unsigned uses_gs:1;
790 unsigned tess_uses_prim_id:1;
791 unsigned uses_tess:1;
792 unsigned line_stipple_enabled:1;
793 unsigned count_from_stream_output:1;
794 unsigned primitive_restart:1;
795 unsigned multi_instances_smaller_than_primgroup:1;
796 unsigned uses_instancing:1;
797 unsigned prim:4;
798 #endif
799 } u;
800 uint32_t index;
801 };
802
803 #define SI_NUM_VGT_STAGES_KEY_BITS 4
804 #define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS)
805
806 /* The VGT_SHADER_STAGES key used to index the table of precomputed values.
807 * Some fields are set by state-change calls, most are set by draw_vbo.
808 */
809 union si_vgt_stages_key {
810 struct {
811 #ifdef PIPE_ARCH_LITTLE_ENDIAN
812 unsigned tess:1;
813 unsigned gs:1;
814 unsigned ngg:1; /* gfx10+ */
815 unsigned streamout:1; /* only used with NGG */
816 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
817 #else /* PIPE_ARCH_BIG_ENDIAN */
818 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
819 unsigned streamout:1;
820 unsigned ngg:1;
821 unsigned gs:1;
822 unsigned tess:1;
823 #endif
824 } u;
825 uint32_t index;
826 };
827
828 struct si_texture_handle
829 {
830 unsigned desc_slot;
831 bool desc_dirty;
832 struct pipe_sampler_view *view;
833 struct si_sampler_state sstate;
834 };
835
836 struct si_image_handle
837 {
838 unsigned desc_slot;
839 bool desc_dirty;
840 struct pipe_image_view view;
841 };
842
843 struct si_saved_cs {
844 struct pipe_reference reference;
845 struct si_context *ctx;
846 struct radeon_saved_cs gfx;
847 struct radeon_saved_cs compute;
848 struct si_resource *trace_buf;
849 unsigned trace_id;
850
851 unsigned gfx_last_dw;
852 unsigned compute_last_dw;
853 bool flushed;
854 int64_t time_flush;
855 };
856
857 struct si_sdma_upload {
858 struct si_resource *dst;
859 struct si_resource *src;
860 unsigned src_offset;
861 unsigned dst_offset;
862 unsigned size;
863 };
864
865 struct si_context {
866 struct pipe_context b; /* base class */
867
868 enum radeon_family family;
869 enum chip_class chip_class;
870
871 struct radeon_winsys *ws;
872 struct radeon_winsys_ctx *ctx;
873 struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
874 struct radeon_cmdbuf *dma_cs;
875 struct pipe_fence_handle *last_gfx_fence;
876 struct pipe_fence_handle *last_sdma_fence;
877 struct si_resource *eop_bug_scratch;
878 struct u_upload_mgr *cached_gtt_allocator;
879 struct threaded_context *tc;
880 struct u_suballocator *allocator_zeroed_memory;
881 struct slab_child_pool pool_transfers;
882 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
883 struct pipe_device_reset_callback device_reset_callback;
884 struct u_log_context *log;
885 void *query_result_shader;
886 void *sh_query_result_shader;
887
888 void (*emit_cache_flush)(struct si_context *ctx);
889
890 struct blitter_context *blitter;
891 void *noop_blend;
892 void *noop_dsa;
893 void *discard_rasterizer_state;
894 void *custom_dsa_flush;
895 void *custom_blend_resolve;
896 void *custom_blend_fmask_decompress;
897 void *custom_blend_eliminate_fastclear;
898 void *custom_blend_dcc_decompress;
899 void *vs_blit_pos;
900 void *vs_blit_pos_layered;
901 void *vs_blit_color;
902 void *vs_blit_color_layered;
903 void *vs_blit_texcoord;
904 void *cs_clear_buffer;
905 void *cs_copy_buffer;
906 void *cs_copy_image;
907 void *cs_copy_image_1d_array;
908 void *cs_clear_render_target;
909 void *cs_clear_render_target_1d_array;
910 void *cs_dcc_retile;
911 struct si_screen *screen;
912 struct pipe_debug_callback debug;
913 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
914 struct si_shader_ctx_state fixed_func_tcs_shader;
915 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
916 struct si_resource *wait_mem_scratch;
917 unsigned wait_mem_number;
918 uint16_t prefetch_L2_mask;
919
920 bool has_graphics;
921 bool gfx_flush_in_progress:1;
922 bool gfx_last_ib_is_busy:1;
923 bool compute_is_busy:1;
924
925 unsigned num_gfx_cs_flushes;
926 unsigned initial_gfx_cs_size;
927 unsigned last_dirty_tex_counter;
928 unsigned last_dirty_buf_counter;
929 unsigned last_compressed_colortex_counter;
930 unsigned last_num_draw_calls;
931 unsigned flags; /* flush flags */
932 /* Current unaccounted memory usage. */
933 uint64_t vram;
934 uint64_t gtt;
935
936 /* Compute-based primitive discard. */
937 unsigned prim_discard_vertex_count_threshold;
938 struct pb_buffer *gds;
939 struct pb_buffer *gds_oa;
940 struct radeon_cmdbuf *prim_discard_compute_cs;
941 unsigned compute_gds_offset;
942 struct si_shader *compute_ib_last_shader;
943 uint32_t compute_rewind_va;
944 unsigned compute_num_prims_in_batch;
945 bool preserve_prim_restart_gds_at_flush;
946 /* index_ring is divided into 2 halves for doublebuffering. */
947 struct si_resource *index_ring;
948 unsigned index_ring_base; /* offset of a per-IB portion */
949 unsigned index_ring_offset; /* offset within a per-IB portion */
950 unsigned index_ring_size_per_ib; /* max available size per IB */
951 bool prim_discard_compute_ib_initialized;
952 /* For tracking the last execution barrier - it can be either
953 * a WRITE_DATA packet or a fence. */
954 uint32_t *last_pkt3_write_data;
955 struct si_resource *barrier_buf;
956 unsigned barrier_buf_offset;
957 struct pipe_fence_handle *last_ib_barrier_fence;
958 struct si_resource *last_ib_barrier_buf;
959 unsigned last_ib_barrier_buf_offset;
960
961 /* Atoms (direct states). */
962 union si_state_atoms atoms;
963 unsigned dirty_atoms; /* mask */
964 /* PM4 states (precomputed immutable states) */
965 unsigned dirty_states;
966 union si_state queued;
967 union si_state emitted;
968
969 /* Atom declarations. */
970 struct si_framebuffer framebuffer;
971 unsigned sample_locs_num_samples;
972 uint16_t sample_mask;
973 unsigned last_cb_target_mask;
974 struct si_blend_color blend_color;
975 struct si_clip_state clip_state;
976 struct si_shader_data shader_pointers;
977 struct si_stencil_ref stencil_ref;
978 struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
979 struct si_streamout streamout;
980 struct si_viewports viewports;
981 unsigned num_window_rectangles;
982 bool window_rectangles_include;
983 struct pipe_scissor_state window_rectangles[4];
984
985 /* Precomputed states. */
986 struct si_pm4_state *init_config;
987 struct si_pm4_state *init_config_gs_rings;
988 bool init_config_has_vgt_flush;
989 struct si_pm4_state *vgt_shader_config[SI_NUM_VGT_STAGES_STATES];
990
991 /* shaders */
992 struct si_shader_ctx_state ps_shader;
993 struct si_shader_ctx_state gs_shader;
994 struct si_shader_ctx_state vs_shader;
995 struct si_shader_ctx_state tcs_shader;
996 struct si_shader_ctx_state tes_shader;
997 struct si_shader_ctx_state cs_prim_discard_state;
998 struct si_cs_shader_state cs_shader_state;
999
1000 /* shader information */
1001 struct si_vertex_elements *vertex_elements;
1002 unsigned sprite_coord_enable;
1003 unsigned cs_max_waves_per_sh;
1004 bool flatshade;
1005 bool do_update_shaders;
1006
1007 /* vertex buffer descriptors */
1008 uint32_t *vb_descriptors_gpu_list;
1009 struct si_resource *vb_descriptors_buffer;
1010 unsigned vb_descriptors_offset;
1011
1012 /* shader descriptors */
1013 struct si_descriptors descriptors[SI_NUM_DESCS];
1014 unsigned descriptors_dirty;
1015 unsigned shader_pointers_dirty;
1016 unsigned shader_needs_decompress_mask;
1017 struct si_buffer_resources rw_buffers;
1018 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
1019 struct si_samplers samplers[SI_NUM_SHADERS];
1020 struct si_images images[SI_NUM_SHADERS];
1021 bool bo_list_add_all_resident_resources;
1022 bool bo_list_add_all_gfx_resources;
1023 bool bo_list_add_all_compute_resources;
1024
1025 /* other shader resources */
1026 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */
1027 struct pipe_resource *esgs_ring;
1028 struct pipe_resource *gsvs_ring;
1029 struct pipe_resource *tess_rings;
1030 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
1031 struct si_resource *border_color_buffer;
1032 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
1033 unsigned border_color_count;
1034 unsigned num_vs_blit_sgprs;
1035 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
1036 uint32_t cs_user_data[4];
1037
1038 /* Vertex and index buffers. */
1039 bool vertex_buffers_dirty;
1040 bool vertex_buffer_pointer_dirty;
1041 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
1042 uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
1043
1044 /* MSAA config state. */
1045 int ps_iter_samples;
1046 bool ps_uses_fbfetch;
1047 bool smoothing_enabled;
1048
1049 /* DB render state. */
1050 unsigned ps_db_shader_control;
1051 unsigned dbcb_copy_sample;
1052 bool dbcb_depth_copy_enabled:1;
1053 bool dbcb_stencil_copy_enabled:1;
1054 bool db_flush_depth_inplace:1;
1055 bool db_flush_stencil_inplace:1;
1056 bool db_depth_clear:1;
1057 bool db_depth_disable_expclear:1;
1058 bool db_stencil_clear:1;
1059 bool db_stencil_disable_expclear:1;
1060 bool occlusion_queries_disabled:1;
1061 bool generate_mipmap_for_depth:1;
1062
1063 /* Emitted draw state. */
1064 bool gs_tri_strip_adj_fix:1;
1065 bool ls_vgpr_fix:1;
1066 bool prim_discard_cs_instancing:1;
1067 bool ngg:1;
1068 int last_index_size;
1069 int last_base_vertex;
1070 int last_start_instance;
1071 int last_instance_count;
1072 int last_drawid;
1073 int last_sh_base_reg;
1074 int last_primitive_restart_en;
1075 int last_restart_index;
1076 int last_prim;
1077 int last_multi_vgt_param;
1078 int last_rast_prim;
1079 int last_flatshade_first;
1080 int last_binning_enabled;
1081 unsigned last_sc_line_stipple;
1082 unsigned current_vs_state;
1083 unsigned last_vs_state;
1084 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
1085
1086 /* Scratch buffer */
1087 struct si_resource *scratch_buffer;
1088 unsigned scratch_waves;
1089 unsigned spi_tmpring_size;
1090
1091 struct si_resource *compute_scratch_buffer;
1092
1093 /* Emitted derived tessellation state. */
1094 /* Local shader (VS), or HS if LS-HS are merged. */
1095 struct si_shader *last_ls;
1096 struct si_shader_selector *last_tcs;
1097 int last_num_tcs_input_cp;
1098 int last_tes_sh_base;
1099 bool last_tess_uses_primid;
1100 unsigned last_num_patches;
1101 int last_ls_hs_config;
1102
1103 /* Debug state. */
1104 bool is_debug;
1105 struct si_saved_cs *current_saved_cs;
1106 uint64_t dmesg_timestamp;
1107 unsigned apitrace_call_number;
1108
1109 /* Other state */
1110 bool need_check_render_feedback;
1111 bool decompression_enabled;
1112 bool dpbb_force_off;
1113 bool vs_writes_viewport_index;
1114 bool vs_disables_clipping_viewport;
1115
1116 /* Precomputed IA_MULTI_VGT_PARAM */
1117 union si_vgt_param_key ia_multi_vgt_param_key;
1118 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1119
1120 /* Bindless descriptors. */
1121 struct si_descriptors bindless_descriptors;
1122 struct util_idalloc bindless_used_slots;
1123 unsigned num_bindless_descriptors;
1124 bool bindless_descriptors_dirty;
1125 bool graphics_bindless_pointer_dirty;
1126 bool compute_bindless_pointer_dirty;
1127
1128 /* Allocated bindless handles */
1129 struct hash_table *tex_handles;
1130 struct hash_table *img_handles;
1131
1132 /* Resident bindless handles */
1133 struct util_dynarray resident_tex_handles;
1134 struct util_dynarray resident_img_handles;
1135
1136 /* Resident bindless handles which need decompression */
1137 struct util_dynarray resident_tex_needs_color_decompress;
1138 struct util_dynarray resident_img_needs_color_decompress;
1139 struct util_dynarray resident_tex_needs_depth_decompress;
1140
1141 /* Bindless state */
1142 bool uses_bindless_samplers;
1143 bool uses_bindless_images;
1144
1145 /* MSAA sample locations.
1146 * The first index is the sample index.
1147 * The second index is the coordinate: X, Y. */
1148 struct {
1149 float x1[1][2];
1150 float x2[2][2];
1151 float x4[4][2];
1152 float x8[8][2];
1153 float x16[16][2];
1154 } sample_positions;
1155 struct pipe_resource *sample_pos_buffer;
1156
1157 /* Misc stats. */
1158 unsigned num_draw_calls;
1159 unsigned num_decompress_calls;
1160 unsigned num_mrt_draw_calls;
1161 unsigned num_prim_restart_calls;
1162 unsigned num_spill_draw_calls;
1163 unsigned num_compute_calls;
1164 unsigned num_spill_compute_calls;
1165 unsigned num_dma_calls;
1166 unsigned num_cp_dma_calls;
1167 unsigned num_vs_flushes;
1168 unsigned num_ps_flushes;
1169 unsigned num_cs_flushes;
1170 unsigned num_cb_cache_flushes;
1171 unsigned num_db_cache_flushes;
1172 unsigned num_L2_invalidates;
1173 unsigned num_L2_writebacks;
1174 unsigned num_resident_handles;
1175 uint64_t num_alloc_tex_transfer_bytes;
1176 unsigned last_tex_ps_draw_ratio; /* for query */
1177 unsigned compute_num_verts_accepted;
1178 unsigned compute_num_verts_rejected;
1179 unsigned compute_num_verts_ineligible; /* due to low vertex count */
1180 unsigned context_roll;
1181
1182 /* Queries. */
1183 /* Maintain the list of active queries for pausing between IBs. */
1184 int num_occlusion_queries;
1185 int num_perfect_occlusion_queries;
1186 int num_pipeline_stat_queries;
1187 struct list_head active_queries;
1188 unsigned num_cs_dw_queries_suspend;
1189
1190 /* Render condition. */
1191 struct pipe_query *render_cond;
1192 unsigned render_cond_mode;
1193 bool render_cond_invert;
1194 bool render_cond_force_off; /* for u_blitter */
1195
1196 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1197 bool sdma_uploads_in_progress;
1198 struct si_sdma_upload *sdma_uploads;
1199 unsigned num_sdma_uploads;
1200 unsigned max_sdma_uploads;
1201
1202 /* Shader-based queries. */
1203 struct list_head shader_query_buffers;
1204 unsigned num_active_shader_queries;
1205
1206 /* Statistics gathering for the DCC enablement heuristic. It can't be
1207 * in si_texture because si_texture can be shared by multiple
1208 * contexts. This is for back buffers only. We shouldn't get too many
1209 * of those.
1210 *
1211 * X11 DRI3 rotates among a finite set of back buffers. They should
1212 * all fit in this array. If they don't, separate DCC might never be
1213 * enabled by DCC stat gathering.
1214 */
1215 struct {
1216 struct si_texture *tex;
1217 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1218 struct pipe_query *ps_stats[3];
1219 /* If all slots are used and another slot is needed,
1220 * the least recently used slot is evicted based on this. */
1221 int64_t last_use_timestamp;
1222 bool query_active;
1223 } dcc_stats[5];
1224
1225 /* Copy one resource to another using async DMA. */
1226 void (*dma_copy)(struct pipe_context *ctx,
1227 struct pipe_resource *dst,
1228 unsigned dst_level,
1229 unsigned dst_x, unsigned dst_y, unsigned dst_z,
1230 struct pipe_resource *src,
1231 unsigned src_level,
1232 const struct pipe_box *src_box);
1233
1234 struct si_tracked_regs tracked_regs;
1235 };
1236
1237 /* cik_sdma.c */
1238 void cik_init_sdma_functions(struct si_context *sctx);
1239
1240 /* si_blit.c */
1241 enum si_blitter_op /* bitmask */
1242 {
1243 SI_SAVE_TEXTURES = 1,
1244 SI_SAVE_FRAMEBUFFER = 2,
1245 SI_SAVE_FRAGMENT_STATE = 4,
1246 SI_DISABLE_RENDER_COND = 8,
1247 };
1248
1249 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1250 void si_blitter_end(struct si_context *sctx);
1251 void si_init_blit_functions(struct si_context *sctx);
1252 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1253 void si_resource_copy_region(struct pipe_context *ctx,
1254 struct pipe_resource *dst,
1255 unsigned dst_level,
1256 unsigned dstx, unsigned dsty, unsigned dstz,
1257 struct pipe_resource *src,
1258 unsigned src_level,
1259 const struct pipe_box *src_box);
1260 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1261
1262 /* si_buffer.c */
1263 bool si_rings_is_buffer_referenced(struct si_context *sctx,
1264 struct pb_buffer *buf,
1265 enum radeon_bo_usage usage);
1266 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
1267 struct si_resource *resource,
1268 unsigned usage);
1269 void si_init_resource_fields(struct si_screen *sscreen,
1270 struct si_resource *res,
1271 uint64_t size, unsigned alignment);
1272 bool si_alloc_resource(struct si_screen *sscreen,
1273 struct si_resource *res);
1274 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
1275 unsigned flags, unsigned usage,
1276 unsigned size, unsigned alignment);
1277 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen,
1278 unsigned flags, unsigned usage,
1279 unsigned size, unsigned alignment);
1280 void si_replace_buffer_storage(struct pipe_context *ctx,
1281 struct pipe_resource *dst,
1282 struct pipe_resource *src);
1283 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1284 void si_init_buffer_functions(struct si_context *sctx);
1285
1286 /* si_clear.c */
1287 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1288 bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format);
1289 bool vi_dcc_clear_level(struct si_context *sctx,
1290 struct si_texture *tex,
1291 unsigned level, unsigned clear_value);
1292 void si_init_clear_functions(struct si_context *sctx);
1293
1294 /* si_compute_blit.c */
1295 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1296 enum si_cache_policy cache_policy);
1297 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1298 uint64_t offset, uint64_t size, uint32_t *clear_value,
1299 uint32_t clear_value_size, enum si_coherency coher,
1300 bool force_cpdma);
1301 void si_copy_buffer(struct si_context *sctx,
1302 struct pipe_resource *dst, struct pipe_resource *src,
1303 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1304 void si_compute_copy_image(struct si_context *sctx,
1305 struct pipe_resource *dst,
1306 unsigned dst_level,
1307 struct pipe_resource *src,
1308 unsigned src_level,
1309 unsigned dstx, unsigned dsty, unsigned dstz,
1310 const struct pipe_box *src_box);
1311 void si_compute_clear_render_target(struct pipe_context *ctx,
1312 struct pipe_surface *dstsurf,
1313 const union pipe_color_union *color,
1314 unsigned dstx, unsigned dsty,
1315 unsigned width, unsigned height,
1316 bool render_condition_enabled);
1317 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1318 void si_init_compute_blit_functions(struct si_context *sctx);
1319
1320 /* si_cp_dma.c */
1321 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1322 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1323 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1324 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1325 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1326 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1327 SI_CPDMA_SKIP_SYNC_AFTER | \
1328 SI_CPDMA_SKIP_SYNC_BEFORE | \
1329 SI_CPDMA_SKIP_GFX_SYNC | \
1330 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1331
1332 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1333 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1334 struct pipe_resource *dst, uint64_t offset,
1335 uint64_t size, unsigned value, unsigned user_flags,
1336 enum si_coherency coher, enum si_cache_policy cache_policy);
1337 void si_cp_dma_copy_buffer(struct si_context *sctx,
1338 struct pipe_resource *dst, struct pipe_resource *src,
1339 uint64_t dst_offset, uint64_t src_offset, unsigned size,
1340 unsigned user_flags, enum si_coherency coher,
1341 enum si_cache_policy cache_policy);
1342 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
1343 uint64_t offset, unsigned size);
1344 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1345 void si_test_gds(struct si_context *sctx);
1346 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf,
1347 unsigned offset, unsigned size, unsigned dst_sel,
1348 unsigned engine, const void *data);
1349 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs,
1350 unsigned dst_sel, struct si_resource *dst, unsigned dst_offset,
1351 unsigned src_sel, struct si_resource *src, unsigned src_offset);
1352
1353 /* si_debug.c */
1354 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
1355 struct radeon_saved_cs *saved, bool get_buffer_list);
1356 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1357 void si_destroy_saved_cs(struct si_saved_cs *scs);
1358 void si_auto_log_cs(void *data, struct u_log_context *log);
1359 void si_log_hw_flush(struct si_context *sctx);
1360 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1361 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1362 void si_init_debug_functions(struct si_context *sctx);
1363 void si_check_vm_faults(struct si_context *sctx,
1364 struct radeon_saved_cs *saved, enum ring_type ring);
1365 bool si_replace_shader(unsigned num, struct si_shader_binary *binary);
1366
1367 /* si_dma.c */
1368 void si_init_dma_functions(struct si_context *sctx);
1369
1370 /* si_dma_cs.c */
1371 void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst,
1372 uint64_t offset);
1373 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1374 uint64_t offset, uint64_t size, unsigned clear_value);
1375 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
1376 struct si_resource *dst, struct si_resource *src);
1377 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
1378 struct pipe_fence_handle **fence);
1379 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
1380 uint64_t offset, uint64_t size, unsigned value);
1381
1382 /* si_fence.c */
1383 void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1384 unsigned event, unsigned event_flags,
1385 unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1386 struct si_resource *buf, uint64_t va,
1387 uint32_t new_fence, unsigned query_type);
1388 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1389 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1390 uint64_t va, uint32_t ref, uint32_t mask, unsigned flags);
1391 void si_init_fence_functions(struct si_context *ctx);
1392 void si_init_screen_fence_functions(struct si_screen *screen);
1393 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1394 struct tc_unflushed_batch_token *tc_token);
1395
1396 /* si_get.c */
1397 void si_init_screen_get_functions(struct si_screen *sscreen);
1398
1399 /* si_gfx_cs.c */
1400 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
1401 struct pipe_fence_handle **fence);
1402 void si_allocate_gds(struct si_context *ctx);
1403 void si_begin_new_gfx_cs(struct si_context *ctx);
1404 void si_need_gfx_cs_space(struct si_context *ctx);
1405 void si_unref_sdma_uploads(struct si_context *sctx);
1406
1407 /* si_gpu_load.c */
1408 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1409 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1410 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
1411 uint64_t begin);
1412
1413 /* si_compute.c */
1414 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
1415 void si_init_compute_functions(struct si_context *sctx);
1416
1417 /* si_compute_prim_discard.c */
1418 enum si_prim_discard_outcome {
1419 SI_PRIM_DISCARD_ENABLED,
1420 SI_PRIM_DISCARD_DISABLED,
1421 SI_PRIM_DISCARD_DRAW_SPLIT,
1422 };
1423
1424 void si_build_prim_discard_compute_shader(struct si_shader_context *ctx);
1425 enum si_prim_discard_outcome
1426 si_prepare_prim_discard_or_split_draw(struct si_context *sctx,
1427 const struct pipe_draw_info *info,
1428 bool primitive_restart);
1429 void si_compute_signal_gfx(struct si_context *sctx);
1430 void si_dispatch_prim_discard_cs_and_draw(struct si_context *sctx,
1431 const struct pipe_draw_info *info,
1432 unsigned index_size,
1433 unsigned base_vertex,
1434 uint64_t input_indexbuf_va,
1435 unsigned input_indexbuf_max_elements);
1436 void si_initialize_prim_discard_tunables(struct si_context *sctx);
1437
1438 /* si_perfcounters.c */
1439 void si_init_perfcounters(struct si_screen *screen);
1440 void si_destroy_perfcounters(struct si_screen *screen);
1441
1442 /* si_pipe.c */
1443 bool si_check_device_reset(struct si_context *sctx);
1444
1445 /* si_query.c */
1446 void si_init_screen_query_functions(struct si_screen *sscreen);
1447 void si_init_query_functions(struct si_context *sctx);
1448 void si_suspend_queries(struct si_context *sctx);
1449 void si_resume_queries(struct si_context *sctx);
1450
1451 /* si_shaderlib_tgsi.c */
1452 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1453 unsigned num_layers);
1454 void *si_create_fixed_func_tcs(struct si_context *sctx);
1455 void *si_create_dma_compute_shader(struct pipe_context *ctx,
1456 unsigned num_dwords_per_thread,
1457 bool dst_stream_cache_policy, bool is_copy);
1458 void *si_create_copy_image_compute_shader(struct pipe_context *ctx);
1459 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx);
1460 void *si_clear_render_target_shader(struct pipe_context *ctx);
1461 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
1462 void *si_create_dcc_retile_cs(struct pipe_context *ctx);
1463 void *si_create_query_result_cs(struct si_context *sctx);
1464 void *gfx10_create_sh_query_result_cs(struct si_context *sctx);
1465
1466 /* gfx10_query.c */
1467 void gfx10_init_query(struct si_context *sctx);
1468 void gfx10_destroy_query(struct si_context *sctx);
1469
1470 /* si_test_dma.c */
1471 void si_test_dma(struct si_screen *sscreen);
1472
1473 /* si_test_clearbuffer.c */
1474 void si_test_dma_perf(struct si_screen *sscreen);
1475
1476 /* si_uvd.c */
1477 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1478 const struct pipe_video_codec *templ);
1479
1480 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1481 const struct pipe_video_buffer *tmpl);
1482
1483 /* si_viewport.c */
1484 void si_update_vs_viewport_state(struct si_context *ctx);
1485 void si_init_viewport_functions(struct si_context *ctx);
1486
1487 /* si_texture.c */
1488 bool si_prepare_for_dma_blit(struct si_context *sctx,
1489 struct si_texture *dst,
1490 unsigned dst_level, unsigned dstx,
1491 unsigned dsty, unsigned dstz,
1492 struct si_texture *src,
1493 unsigned src_level,
1494 const struct pipe_box *src_box);
1495 void si_eliminate_fast_color_clear(struct si_context *sctx,
1496 struct si_texture *tex);
1497 void si_texture_discard_cmask(struct si_screen *sscreen,
1498 struct si_texture *tex);
1499 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1500 struct pipe_resource *texture);
1501 void si_print_texture_info(struct si_screen *sscreen,
1502 struct si_texture *tex, struct u_log_context *log);
1503 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1504 const struct pipe_resource *templ);
1505 bool vi_dcc_formats_compatible(struct si_screen *sscreen,
1506 enum pipe_format format1,
1507 enum pipe_format format2);
1508 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1509 unsigned level,
1510 enum pipe_format view_format);
1511 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1512 struct pipe_resource *tex,
1513 unsigned level,
1514 enum pipe_format view_format);
1515 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1516 struct pipe_resource *texture,
1517 const struct pipe_surface *templ,
1518 unsigned width0, unsigned height0,
1519 unsigned width, unsigned height);
1520 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1521 void vi_separate_dcc_try_enable(struct si_context *sctx,
1522 struct si_texture *tex);
1523 void vi_separate_dcc_start_query(struct si_context *sctx,
1524 struct si_texture *tex);
1525 void vi_separate_dcc_stop_query(struct si_context *sctx,
1526 struct si_texture *tex);
1527 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1528 struct si_texture *tex);
1529 bool si_texture_disable_dcc(struct si_context *sctx,
1530 struct si_texture *tex);
1531 void si_init_screen_texture_functions(struct si_screen *sscreen);
1532 void si_init_context_texture_functions(struct si_context *sctx);
1533
1534
1535 /*
1536 * common helpers
1537 */
1538
1539 static inline struct si_resource *si_resource(struct pipe_resource *r)
1540 {
1541 return (struct si_resource*)r;
1542 }
1543
1544 static inline void
1545 si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1546 {
1547 pipe_resource_reference((struct pipe_resource **)ptr,
1548 (struct pipe_resource *)res);
1549 }
1550
1551 static inline void
1552 si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1553 {
1554 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1555 }
1556
1557 static inline bool
1558 vi_dcc_enabled(struct si_texture *tex, unsigned level)
1559 {
1560 return tex->dcc_offset && level < tex->surface.num_dcc_levels;
1561 }
1562
1563 static inline unsigned
1564 si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1565 {
1566 if (stencil)
1567 return tex->surface.u.legacy.stencil_tiling_index[level];
1568 else
1569 return tex->surface.u.legacy.tiling_index[level];
1570 }
1571
1572 static inline unsigned
1573 si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx)
1574 {
1575 /* Don't count the needed CS space exactly and just use an upper bound.
1576 *
1577 * Also reserve space for stopping queries at the end of IB, because
1578 * the number of active queries is unlimited in theory.
1579 */
1580 return 2048 + sctx->num_cs_dw_queries_suspend;
1581 }
1582
1583 static inline void
1584 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1585 {
1586 if (r) {
1587 /* Add memory usage for need_gfx_cs_space */
1588 sctx->vram += si_resource(r)->vram_usage;
1589 sctx->gtt += si_resource(r)->gart_usage;
1590 }
1591 }
1592
1593 static inline void
1594 si_invalidate_draw_sh_constants(struct si_context *sctx)
1595 {
1596 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1597 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1598 }
1599
1600 static inline unsigned
1601 si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1602 {
1603 return 1 << (atom - sctx->atoms.array);
1604 }
1605
1606 static inline void
1607 si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1608 {
1609 unsigned bit = si_get_atom_bit(sctx, atom);
1610
1611 if (dirty)
1612 sctx->dirty_atoms |= bit;
1613 else
1614 sctx->dirty_atoms &= ~bit;
1615 }
1616
1617 static inline bool
1618 si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1619 {
1620 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1621 }
1622
1623 static inline void
1624 si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1625 {
1626 si_set_atom_dirty(sctx, atom, true);
1627 }
1628
1629 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1630 {
1631 if (sctx->gs_shader.cso)
1632 return &sctx->gs_shader;
1633 if (sctx->tes_shader.cso)
1634 return &sctx->tes_shader;
1635
1636 return &sctx->vs_shader;
1637 }
1638
1639 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1640 {
1641 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1642
1643 return vs->cso ? &vs->cso->info : NULL;
1644 }
1645
1646 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1647 {
1648 if (sctx->gs_shader.cso &&
1649 sctx->gs_shader.current &&
1650 !sctx->gs_shader.current->key.as_ngg)
1651 return sctx->gs_shader.cso->gs_copy_shader;
1652
1653 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1654 return vs->current ? vs->current : NULL;
1655 }
1656
1657 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1658 unsigned processor)
1659 {
1660 return sscreen->debug_flags & (1 << processor);
1661 }
1662
1663 static inline bool si_get_strmout_en(struct si_context *sctx)
1664 {
1665 return sctx->streamout.streamout_enabled ||
1666 sctx->streamout.prims_gen_query_enabled;
1667 }
1668
1669 static inline unsigned
1670 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1671 {
1672 unsigned alignment, tcc_cache_line_size;
1673
1674 /* If the upload size is less than the cache line size (e.g. 16, 32),
1675 * the whole thing will fit into a cache line if we align it to its size.
1676 * The idea is that multiple small uploads can share a cache line.
1677 * If the upload size is greater, align it to the cache line size.
1678 */
1679 alignment = util_next_power_of_two(upload_size);
1680 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1681 return MIN2(alignment, tcc_cache_line_size);
1682 }
1683
1684 static inline void
1685 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1686 {
1687 if (pipe_reference(&(*dst)->reference, &src->reference))
1688 si_destroy_saved_cs(*dst);
1689
1690 *dst = src;
1691 }
1692
1693 static inline void
1694 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1695 bool shaders_read_metadata, bool dcc_pipe_aligned)
1696 {
1697 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1698 SI_CONTEXT_INV_VCACHE;
1699
1700 if (sctx->chip_class >= GFX10) {
1701 if (shaders_read_metadata)
1702 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1703 } else if (sctx->chip_class == GFX9) {
1704 /* Single-sample color is coherent with shaders on GFX9, but
1705 * L2 metadata must be flushed if shaders read metadata.
1706 * (DCC, CMASK).
1707 */
1708 if (num_samples >= 2 ||
1709 (shaders_read_metadata && !dcc_pipe_aligned))
1710 sctx->flags |= SI_CONTEXT_INV_L2;
1711 else if (shaders_read_metadata)
1712 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1713 } else {
1714 /* GFX6-GFX8 */
1715 sctx->flags |= SI_CONTEXT_INV_L2;
1716 }
1717 }
1718
1719 static inline void
1720 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1721 bool include_stencil, bool shaders_read_metadata)
1722 {
1723 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1724 SI_CONTEXT_INV_VCACHE;
1725
1726 if (sctx->chip_class >= GFX10) {
1727 if (shaders_read_metadata)
1728 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1729 } else if (sctx->chip_class == GFX9) {
1730 /* Single-sample depth (not stencil) is coherent with shaders
1731 * on GFX9, but L2 metadata must be flushed if shaders read
1732 * metadata.
1733 */
1734 if (num_samples >= 2 || include_stencil)
1735 sctx->flags |= SI_CONTEXT_INV_L2;
1736 else if (shaders_read_metadata)
1737 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1738 } else {
1739 /* GFX6-GFX8 */
1740 sctx->flags |= SI_CONTEXT_INV_L2;
1741 }
1742 }
1743
1744 static inline bool
1745 si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1746 {
1747 return (stencil_sampler && tex->can_sample_s) ||
1748 (!stencil_sampler && tex->can_sample_z);
1749 }
1750
1751 static inline bool
1752 si_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1753 {
1754 if (zs_mask == PIPE_MASK_S && tex->htile_stencil_disabled)
1755 return false;
1756
1757 return tex->htile_offset && level == 0;
1758 }
1759
1760 static inline bool
1761 vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1762 {
1763 assert(!tex->tc_compatible_htile || tex->htile_offset);
1764 return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask);
1765 }
1766
1767 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1768 {
1769 if (sctx->ps_uses_fbfetch)
1770 return sctx->framebuffer.nr_color_samples;
1771
1772 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1773 }
1774
1775 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1776 {
1777 if (sctx->queued.named.rasterizer->rasterizer_discard)
1778 return 0;
1779
1780 struct si_shader_selector *ps = sctx->ps_shader.cso;
1781 if (!ps)
1782 return 0;
1783
1784 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1785 sctx->queued.named.blend->cb_target_mask;
1786
1787 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1788 colormask &= ps->colors_written_4bit;
1789 else if (!ps->colors_written_4bit)
1790 colormask = 0; /* color0 writes all cbufs, but it's not written */
1791
1792 return colormask;
1793 }
1794
1795 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1796 (1 << PIPE_PRIM_LINE_LOOP) | \
1797 (1 << PIPE_PRIM_LINE_STRIP) | \
1798 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1799 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1800
1801 static inline bool util_prim_is_lines(unsigned prim)
1802 {
1803 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1804 }
1805
1806 static inline bool util_prim_is_points_or_lines(unsigned prim)
1807 {
1808 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES |
1809 (1 << PIPE_PRIM_POINTS))) != 0;
1810 }
1811
1812 static inline bool util_rast_prim_is_triangles(unsigned prim)
1813 {
1814 return ((1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1815 (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1816 (1 << PIPE_PRIM_TRIANGLE_FAN) |
1817 (1 << PIPE_PRIM_QUADS) |
1818 (1 << PIPE_PRIM_QUAD_STRIP) |
1819 (1 << PIPE_PRIM_POLYGON) |
1820 (1 << PIPE_PRIM_TRIANGLES_ADJACENCY) |
1821 (1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY)));
1822 }
1823
1824 /**
1825 * Return true if there is enough memory in VRAM and GTT for the buffers
1826 * added so far.
1827 *
1828 * \param vram VRAM memory size not added to the buffer list yet
1829 * \param gtt GTT memory size not added to the buffer list yet
1830 */
1831 static inline bool
1832 radeon_cs_memory_below_limit(struct si_screen *screen,
1833 struct radeon_cmdbuf *cs,
1834 uint64_t vram, uint64_t gtt)
1835 {
1836 vram += cs->used_vram;
1837 gtt += cs->used_gart;
1838
1839 /* Anything that goes above the VRAM size should go to GTT. */
1840 if (vram > screen->info.vram_size)
1841 gtt += vram - screen->info.vram_size;
1842
1843 /* Now we just need to check if we have enough GTT. */
1844 return gtt < screen->info.gart_size * 0.7;
1845 }
1846
1847 /**
1848 * Add a buffer to the buffer list for the given command stream (CS).
1849 *
1850 * All buffers used by a CS must be added to the list. This tells the kernel
1851 * driver which buffers are used by GPU commands. Other buffers can
1852 * be swapped out (not accessible) during execution.
1853 *
1854 * The buffer list becomes empty after every context flush and must be
1855 * rebuilt.
1856 */
1857 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1858 struct radeon_cmdbuf *cs,
1859 struct si_resource *bo,
1860 enum radeon_bo_usage usage,
1861 enum radeon_bo_priority priority)
1862 {
1863 assert(usage);
1864 sctx->ws->cs_add_buffer(
1865 cs, bo->buf,
1866 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1867 bo->domains, priority);
1868 }
1869
1870 /**
1871 * Same as above, but also checks memory usage and flushes the context
1872 * accordingly.
1873 *
1874 * When this SHOULD NOT be used:
1875 *
1876 * - if si_context_add_resource_size has been called for the buffer
1877 * followed by *_need_cs_space for checking the memory usage
1878 *
1879 * - if si_need_dma_space has been called for the buffer
1880 *
1881 * - when emitting state packets and draw packets (because preceding packets
1882 * can't be re-emitted at that point)
1883 *
1884 * - if shader resource "enabled_mask" is not up-to-date or there is
1885 * a different constraint disallowing a context flush
1886 */
1887 static inline void
1888 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1889 struct si_resource *bo,
1890 enum radeon_bo_usage usage,
1891 enum radeon_bo_priority priority,
1892 bool check_mem)
1893 {
1894 if (check_mem &&
1895 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1896 sctx->vram + bo->vram_usage,
1897 sctx->gtt + bo->gart_usage))
1898 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1899
1900 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority);
1901 }
1902
1903 static inline bool si_compute_prim_discard_enabled(struct si_context *sctx)
1904 {
1905 return sctx->prim_discard_vertex_count_threshold != UINT_MAX;
1906 }
1907
1908 static inline unsigned si_get_wave_size(struct si_screen *sscreen,
1909 enum pipe_shader_type shader_type,
1910 bool ngg, bool es)
1911 {
1912 if (shader_type == PIPE_SHADER_COMPUTE)
1913 return sscreen->compute_wave_size;
1914 else if (shader_type == PIPE_SHADER_FRAGMENT)
1915 return sscreen->ps_wave_size;
1916 else if ((shader_type == PIPE_SHADER_TESS_EVAL && es && !ngg) ||
1917 (shader_type == PIPE_SHADER_GEOMETRY && !ngg)) /* legacy GS only supports Wave64 */
1918 return 64;
1919 else
1920 return sscreen->ge_wave_size;
1921 }
1922
1923 static inline unsigned si_get_shader_wave_size(struct si_shader *shader)
1924 {
1925 return si_get_wave_size(shader->selector->screen, shader->selector->type,
1926 shader->key.as_ngg, shader->key.as_es);
1927 }
1928
1929 #define PRINT_ERR(fmt, args...) \
1930 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1931
1932 #endif