src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  * Copyright 2018 Advanced Micro Devices, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * on the rights to use, copy, modify, merge, publish, distribute, sub
  10  * license, and/or sell copies of the Software, and to permit persons to whom
  11  * the Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  21  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  22  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25 #ifndef SI_PIPE_H
  26 #define SI_PIPE_H
  27
  28 #include "si_shader.h"
  29
  30 #include "util/u_dynarray.h"
  31 #include "util/u_idalloc.h"
  32
  33 #ifdef PIPE_ARCH_BIG_ENDIAN
  34 #define SI_BIG_ENDIAN 1
  35 #else
  36 #define SI_BIG_ENDIAN 0
  37 #endif
  38
  39 #define ATI_VENDOR_ID 0x1002
  40
  41 #define SI_NOT_QUERY            0xffffffff
  42
  43 /* The base vertex and primitive restart can be any number, but we must pick
  44  * one which will mean "unknown" for the purpose of state tracking and
  45  * the number shouldn't be a commonly-used one. */
  46 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  47 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  48 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  49 #define SI_GS_PER_ES 128
  50 /* Alignment for optimal CP DMA performance. */
  51 #define SI_CPDMA_ALIGNMENT      32
  52
  53 /* Pipeline & streamout query controls. */
  54 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
  55 #define SI_CONTEXT_STOP_PIPELINE_STATS  (1 << 1)
  56 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
  57 /* Instruction cache. */
  58 #define SI_CONTEXT_INV_ICACHE           (1 << 3)
  59 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  60 #define SI_CONTEXT_INV_SMEM_L1          (1 << 4)
  61 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  62 #define SI_CONTEXT_INV_VMEM_L1          (1 << 5)
  63 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  64 #define SI_CONTEXT_INV_GLOBAL_L2        (1 << 6)
  65 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  66  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
  67 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2  (1 << 7)
  68 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
  69  * a CB or DB flush. */
  70 #define SI_CONTEXT_INV_L2_METADATA      (1 << 8)
  71 /* Framebuffer caches. */
  72 #define SI_CONTEXT_FLUSH_AND_INV_DB     (1 << 9)
  73 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
  74 #define SI_CONTEXT_FLUSH_AND_INV_CB     (1 << 11)
  75 /* Engine synchronization. */
  76 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (1 << 12)
  77 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (1 << 13)
  78 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (1 << 14)
  79 #define SI_CONTEXT_VGT_FLUSH            (1 << 15)
  80 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (1 << 16)
  81
  82 #define SI_PREFETCH_VBO_DESCRIPTORS     (1 << 0)
  83 #define SI_PREFETCH_LS                  (1 << 1)
  84 #define SI_PREFETCH_HS                  (1 << 2)
  85 #define SI_PREFETCH_ES                  (1 << 3)
  86 #define SI_PREFETCH_GS                  (1 << 4)
  87 #define SI_PREFETCH_VS                  (1 << 5)
  88 #define SI_PREFETCH_PS                  (1 << 6)
  89
  90 #define SI_MAX_BORDER_COLORS    4096
  91 #define SI_MAX_VIEWPORTS        16
  92 #define SIX_BITS                0x3F
  93
  94 struct si_compute;
  95 struct hash_table;
  96 struct u_suballocator;
  97
  98 struct si_screen {
  99         struct pipe_screen              b;
 100         struct radeon_winsys            *ws;
 101         struct disk_cache               *disk_shader_cache;
 102
 103         struct radeon_info              info;
 104         uint64_t                        debug_flags;
 105         char                            renderer_string[100];
 106
 107         unsigned                        gs_table_depth;
 108         unsigned                        tess_offchip_block_dw_size;
 109         unsigned                        tess_offchip_ring_size;
 110         unsigned                        tess_factor_ring_size;
 111         unsigned                        vgt_hs_offchip_param;
 112         bool                            has_clear_state;
 113         bool                            has_distributed_tess;
 114         bool                            has_draw_indirect_multi;
 115         bool                            has_out_of_order_rast;
 116         bool                            assume_no_z_fights;
 117         bool                            commutative_blend_add;
 118         bool                            clear_db_cache_before_clear;
 119         bool                            has_msaa_sample_loc_bug;
 120         bool                            has_ls_vgpr_init_bug;
 121         bool                            dpbb_allowed;
 122         bool                            dfsm_allowed;
 123         bool                            llvm_has_working_vgpr_indexing;
 124
 125         /* Whether shaders are monolithic (1-part) or separate (3-part). */
 126         bool                            use_monolithic_shaders;
 127         bool                            record_llvm_ir;
 128         bool                            has_rbplus;     /* if RB+ registers exist */
 129         bool                            rbplus_allowed; /* if RB+ is allowed */
 130         bool                            dcc_msaa_allowed;
 131         bool                            cpdma_prefetch_writes_memory;
 132
 133         struct slab_parent_pool         pool_transfers;
 134
 135         /* Texture filter settings. */
 136         int                             force_aniso; /* -1 = disabled */
 137
 138         /* Auxiliary context. Mainly used to initialize resources.
 139          * It must be locked prior to using and flushed before unlocking. */
 140         struct pipe_context             *aux_context;
 141         mtx_t                           aux_context_lock;
 142
 143         /* This must be in the screen, because UE4 uses one context for
 144          * compilation and another one for rendering.
 145          */
 146         unsigned                        num_compilations;
 147         /* Along with ST_DEBUG=precompile, this should show if applications
 148          * are loading shaders on demand. This is a monotonic counter.
 149          */
 150         unsigned                        num_shaders_created;
 151         unsigned                        num_shader_cache_hits;
 152
 153         /* GPU load thread. */
 154         mtx_t                           gpu_load_mutex;
 155         thrd_t                          gpu_load_thread;
 156         union si_mmio_counters  mmio_counters;
 157         volatile unsigned               gpu_load_stop_thread; /* bool */
 158
 159         /* Performance counters. */
 160         struct si_perfcounters  *perfcounters;
 161
 162         /* If pipe_screen wants to recompute and re-emit the framebuffer,
 163          * sampler, and image states of all contexts, it should atomically
 164          * increment this.
 165          *
 166          * Each context will compare this with its own last known value of
 167          * the counter before drawing and re-emit the states accordingly.
 168          */
 169         unsigned                        dirty_tex_counter;
 170
 171         /* Atomically increment this counter when an existing texture's
 172          * metadata is enabled or disabled in a way that requires changing
 173          * contexts' compressed texture binding masks.
 174          */
 175         unsigned                        compressed_colortex_counter;
 176
 177         struct {
 178                 /* Context flags to set so that all writes from earlier jobs
 179                  * in the CP are seen by L2 clients.
 180                  */
 181                 unsigned cp_to_L2;
 182
 183                 /* Context flags to set so that all writes from earlier jobs
 184                  * that end in L2 are seen by CP.
 185                  */
 186                 unsigned L2_to_cp;
 187         } barrier_flags;
 188
 189         mtx_t                   shader_parts_mutex;
 190         struct si_shader_part           *vs_prologs;
 191         struct si_shader_part           *tcs_epilogs;
 192         struct si_shader_part           *gs_prologs;
 193         struct si_shader_part           *ps_prologs;
 194         struct si_shader_part           *ps_epilogs;
 195
 196         /* Shader cache in memory.
 197          *
 198          * Design & limitations:
 199          * - The shader cache is per screen (= per process), never saved to
 200          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 201          * - It can only be used with one-variant-per-shader support, in which
 202          *   case only the main (typically middle) part of shaders is cached.
 203          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 204          *   variants of VS and TES are cached, so LS and ES aren't.
 205          * - GS and CS aren't cached, but it's certainly possible to cache
 206          *   those as well.
 207          */
 208         mtx_t                   shader_cache_mutex;
 209         struct hash_table               *shader_cache;
 210
 211         /* Shader compiler queue for multithreaded compilation. */
 212         struct util_queue               shader_compiler_queue;
 213         /* Use at most 3 normal compiler threads on quadcore and better.
 214          * Hyperthreaded CPUs report the number of threads, but we want
 215          * the number of cores. */
 216         LLVMTargetMachineRef            tm[3]; /* used by the queue only */
 217
 218         struct util_queue               shader_compiler_queue_low_priority;
 219         /* Use at most 2 low priority threads on quadcore and better.
 220          * We want to minimize the impact on multithreaded Mesa. */
 221         LLVMTargetMachineRef            tm_low_priority[2]; /* at most 2 threads */
 222 };
 223
 224 struct si_blend_color {
 225         struct r600_atom                atom;
 226         struct pipe_blend_color         state;
 227         bool                            any_nonzeros;
 228 };
 229
 230 struct si_sampler_view {
 231         struct pipe_sampler_view        base;
 232         /* [0..7] = image descriptor
 233          * [4..7] = buffer descriptor */
 234         uint32_t                        state[8];
 235         uint32_t                        fmask_state[8];
 236         const struct legacy_surf_level  *base_level_info;
 237         ubyte                           base_level;
 238         ubyte                           block_width;
 239         bool is_stencil_sampler;
 240         bool is_integer;
 241         bool dcc_incompatible;
 242 };
 243
 244 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
 245
 246 struct si_sampler_state {
 247 #ifdef DEBUG
 248         unsigned                        magic;
 249 #endif
 250         uint32_t                        val[4];
 251         uint32_t                        integer_val[4];
 252         uint32_t                        upgraded_depth_val[4];
 253 };
 254
 255 struct si_cs_shader_state {
 256         struct si_compute               *program;
 257         struct si_compute               *emitted_program;
 258         unsigned                        offset;
 259         bool                            initialized;
 260         bool                            uses_scratch;
 261 };
 262
 263 struct si_samplers {
 264         struct pipe_sampler_view        *views[SI_NUM_SAMPLERS];
 265         struct si_sampler_state         *sampler_states[SI_NUM_SAMPLERS];
 266
 267         /* The i-th bit is set if that element is enabled (non-NULL resource). */
 268         unsigned                        enabled_mask;
 269         uint32_t                        needs_depth_decompress_mask;
 270         uint32_t                        needs_color_decompress_mask;
 271 };
 272
 273 struct si_images {
 274         struct pipe_image_view          views[SI_NUM_IMAGES];
 275         uint32_t                        needs_color_decompress_mask;
 276         unsigned                        enabled_mask;
 277 };
 278
 279 struct si_framebuffer {
 280         struct r600_atom                atom;
 281         struct pipe_framebuffer_state   state;
 282         unsigned                        colorbuf_enabled_4bit;
 283         unsigned                        spi_shader_col_format;
 284         unsigned                        spi_shader_col_format_alpha;
 285         unsigned                        spi_shader_col_format_blend;
 286         unsigned                        spi_shader_col_format_blend_alpha;
 287         ubyte                           nr_samples:5; /* at most 16xAA */
 288         ubyte                           log_samples:3; /* at most 4 = 16xAA */
 289         ubyte                           compressed_cb_mask;
 290         ubyte                           uncompressed_cb_mask;
 291         ubyte                           color_is_int8;
 292         ubyte                           color_is_int10;
 293         ubyte                           dirty_cbufs;
 294         bool                            dirty_zsbuf;
 295         bool                            any_dst_linear;
 296         bool                            CB_has_shader_readable_metadata;
 297         bool                            DB_has_shader_readable_metadata;
 298 };
 299
 300 struct si_signed_scissor {
 301         int minx;
 302         int miny;
 303         int maxx;
 304         int maxy;
 305 };
 306
 307 struct si_scissors {
 308         struct r600_atom                atom;
 309         unsigned                        dirty_mask;
 310         struct pipe_scissor_state       states[SI_MAX_VIEWPORTS];
 311 };
 312
 313 struct si_viewports {
 314         struct r600_atom                atom;
 315         unsigned                        dirty_mask;
 316         unsigned                        depth_range_dirty_mask;
 317         struct pipe_viewport_state      states[SI_MAX_VIEWPORTS];
 318         struct si_signed_scissor        as_scissor[SI_MAX_VIEWPORTS];
 319 };
 320
 321 struct si_clip_state {
 322         struct r600_atom                atom;
 323         struct pipe_clip_state          state;
 324         bool                            any_nonzeros;
 325 };
 326
 327 struct si_sample_locs {
 328         struct r600_atom        atom;
 329         unsigned                nr_samples;
 330 };
 331
 332 struct si_sample_mask {
 333         struct r600_atom        atom;
 334         uint16_t                sample_mask;
 335 };
 336
 337 struct si_streamout_target {
 338         struct pipe_stream_output_target b;
 339
 340         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 341         struct r600_resource    *buf_filled_size;
 342         unsigned                buf_filled_size_offset;
 343         bool                    buf_filled_size_valid;
 344
 345         unsigned                stride_in_dw;
 346 };
 347
 348 struct si_streamout {
 349         struct r600_atom                begin_atom;
 350         bool                            begin_emitted;
 351
 352         unsigned                        enabled_mask;
 353         unsigned                        num_targets;
 354         struct si_streamout_target      *targets[PIPE_MAX_SO_BUFFERS];
 355
 356         unsigned                        append_bitmask;
 357         bool                            suspended;
 358
 359         /* External state which comes from the vertex shader,
 360          * it must be set explicitly when binding a shader. */
 361         uint16_t                        *stride_in_dw;
 362         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 363
 364         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 365         unsigned                        hw_enabled_mask;
 366
 367         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 368         struct r600_atom                enable_atom;
 369         bool                            streamout_enabled;
 370         bool                            prims_gen_query_enabled;
 371         int                             num_prims_gen_queries;
 372 };
 373
 374 /* A shader state consists of the shader selector, which is a constant state
 375  * object shared by multiple contexts and shouldn't be modified, and
 376  * the current shader variant selected for this context.
 377  */
 378 struct si_shader_ctx_state {
 379         struct si_shader_selector       *cso;
 380         struct si_shader                *current;
 381 };
 382
 383 #define SI_NUM_VGT_PARAM_KEY_BITS 12
 384 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
 385
 386 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
 387  * Some fields are set by state-change calls, most are set by draw_vbo.
 388  */
 389 union si_vgt_param_key {
 390         struct {
 391                 unsigned prim:4;
 392                 unsigned uses_instancing:1;
 393                 unsigned multi_instances_smaller_than_primgroup:1;
 394                 unsigned primitive_restart:1;
 395                 unsigned count_from_stream_output:1;
 396                 unsigned line_stipple_enabled:1;
 397                 unsigned uses_tess:1;
 398                 unsigned tess_uses_prim_id:1;
 399                 unsigned uses_gs:1;
 400                 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
 401         } u;
 402         uint32_t index;
 403 };
 404
 405 struct si_texture_handle
 406 {
 407         unsigned                        desc_slot;
 408         bool                            desc_dirty;
 409         struct pipe_sampler_view        *view;
 410         struct si_sampler_state         sstate;
 411 };
 412
 413 struct si_image_handle
 414 {
 415         unsigned                        desc_slot;
 416         bool                            desc_dirty;
 417         struct pipe_image_view          view;
 418 };
 419
 420 struct si_saved_cs {
 421         struct pipe_reference   reference;
 422         struct si_context       *ctx;
 423         struct radeon_saved_cs  gfx;
 424         struct r600_resource    *trace_buf;
 425         unsigned                trace_id;
 426
 427         unsigned                gfx_last_dw;
 428         bool                    flushed;
 429         int64_t                 time_flush;
 430 };
 431
 432 struct si_context {
 433         struct r600_common_context      b;
 434         struct blitter_context          *blitter;
 435         void                            *custom_dsa_flush;
 436         void                            *custom_blend_resolve;
 437         void                            *custom_blend_fmask_decompress;
 438         void                            *custom_blend_eliminate_fastclear;
 439         void                            *custom_blend_dcc_decompress;
 440         void                            *vs_blit_pos;
 441         void                            *vs_blit_pos_layered;
 442         void                            *vs_blit_color;
 443         void                            *vs_blit_color_layered;
 444         void                            *vs_blit_texcoord;
 445         struct si_screen                *screen;
 446         struct pipe_debug_callback      debug;
 447         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 448         struct si_shader_ctx_state      fixed_func_tcs_shader;
 449         struct r600_resource            *wait_mem_scratch;
 450         unsigned                        wait_mem_number;
 451         uint16_t                        prefetch_L2_mask;
 452
 453         bool                            gfx_flush_in_progress:1;
 454         bool                            compute_is_busy:1;
 455
 456         /* Atoms (direct states). */
 457         union si_state_atoms            atoms;
 458         unsigned                        dirty_atoms; /* mask */
 459         /* PM4 states (precomputed immutable states) */
 460         unsigned                        dirty_states;
 461         union si_state                  queued;
 462         union si_state                  emitted;
 463
 464         /* Atom declarations. */
 465         struct si_framebuffer           framebuffer;
 466         struct si_sample_locs           msaa_sample_locs;
 467         struct r600_atom                db_render_state;
 468         struct r600_atom                dpbb_state;
 469         struct r600_atom                msaa_config;
 470         struct si_sample_mask           sample_mask;
 471         struct r600_atom                cb_render_state;
 472         unsigned                        last_cb_target_mask;
 473         struct si_blend_color           blend_color;
 474         struct r600_atom                clip_regs;
 475         struct si_clip_state            clip_state;
 476         struct si_shader_data           shader_pointers;
 477         struct si_stencil_ref           stencil_ref;
 478         struct r600_atom                spi_map;
 479         struct si_scissors              scissors;
 480         struct si_streamout             streamout;
 481         struct si_viewports             viewports;
 482
 483         /* Precomputed states. */
 484         struct si_pm4_state             *init_config;
 485         struct si_pm4_state             *init_config_gs_rings;
 486         bool                            init_config_has_vgt_flush;
 487         struct si_pm4_state             *vgt_shader_config[4];
 488
 489         /* shaders */
 490         struct si_shader_ctx_state      ps_shader;
 491         struct si_shader_ctx_state      gs_shader;
 492         struct si_shader_ctx_state      vs_shader;
 493         struct si_shader_ctx_state      tcs_shader;
 494         struct si_shader_ctx_state      tes_shader;
 495         struct si_cs_shader_state       cs_shader_state;
 496
 497         /* shader information */
 498         struct si_vertex_elements       *vertex_elements;
 499         unsigned                        sprite_coord_enable;
 500         bool                            flatshade;
 501         bool                            do_update_shaders;
 502
 503         /* vertex buffer descriptors */
 504         uint32_t *vb_descriptors_gpu_list;
 505         struct r600_resource *vb_descriptors_buffer;
 506         unsigned vb_descriptors_offset;
 507
 508         /* shader descriptors */
 509         struct si_descriptors           descriptors[SI_NUM_DESCS];
 510         unsigned                        descriptors_dirty;
 511         unsigned                        shader_pointers_dirty;
 512         unsigned                        shader_needs_decompress_mask;
 513         struct si_buffer_resources      rw_buffers;
 514         struct si_buffer_resources      const_and_shader_buffers[SI_NUM_SHADERS];
 515         struct si_samplers              samplers[SI_NUM_SHADERS];
 516         struct si_images                images[SI_NUM_SHADERS];
 517
 518         /* other shader resources */
 519         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 520         struct pipe_resource            *esgs_ring;
 521         struct pipe_resource            *gsvs_ring;
 522         struct pipe_resource            *tess_rings;
 523         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 524         struct r600_resource            *border_color_buffer;
 525         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 526         unsigned                        border_color_count;
 527         unsigned                        num_vs_blit_sgprs;
 528         uint32_t                        vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
 529
 530         /* Vertex and index buffers. */
 531         bool                            vertex_buffers_dirty;
 532         bool                            vertex_buffer_pointer_dirty;
 533         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 534
 535         /* MSAA config state. */
 536         int                             ps_iter_samples;
 537         bool                            ps_uses_fbfetch;
 538         bool                            smoothing_enabled;
 539
 540         /* DB render state. */
 541         unsigned                ps_db_shader_control;
 542         unsigned                dbcb_copy_sample;
 543         bool                    dbcb_depth_copy_enabled:1;
 544         bool                    dbcb_stencil_copy_enabled:1;
 545         bool                    db_flush_depth_inplace:1;
 546         bool                    db_flush_stencil_inplace:1;
 547         bool                    db_depth_clear:1;
 548         bool                    db_depth_disable_expclear:1;
 549         bool                    db_stencil_clear:1;
 550         bool                    db_stencil_disable_expclear:1;
 551         bool                    occlusion_queries_disabled:1;
 552         bool                    generate_mipmap_for_depth:1;
 553
 554         /* Emitted draw state. */
 555         bool                    gs_tri_strip_adj_fix:1;
 556         bool                    ls_vgpr_fix:1;
 557         int                     last_index_size;
 558         int                     last_base_vertex;
 559         int                     last_start_instance;
 560         int                     last_drawid;
 561         int                     last_sh_base_reg;
 562         int                     last_primitive_restart_en;
 563         int                     last_restart_index;
 564         int                     last_gs_out_prim;
 565         int                     last_prim;
 566         int                     last_multi_vgt_param;
 567         int                     last_rast_prim;
 568         unsigned                last_sc_line_stipple;
 569         unsigned                current_vs_state;
 570         unsigned                last_vs_state;
 571         enum pipe_prim_type     current_rast_prim; /* primitive type after TES, GS */
 572
 573         /* Scratch buffer */
 574         struct r600_atom        scratch_state;
 575         struct r600_resource    *scratch_buffer;
 576         unsigned                scratch_waves;
 577         unsigned                spi_tmpring_size;
 578
 579         struct r600_resource    *compute_scratch_buffer;
 580
 581         /* Emitted derived tessellation state. */
 582         /* Local shader (VS), or HS if LS-HS are merged. */
 583         struct si_shader        *last_ls;
 584         struct si_shader_selector *last_tcs;
 585         int                     last_num_tcs_input_cp;
 586         int                     last_tes_sh_base;
 587         bool                    last_tess_uses_primid;
 588         unsigned                last_num_patches;
 589
 590         /* Debug state. */
 591         bool                    is_debug;
 592         struct si_saved_cs      *current_saved_cs;
 593         uint64_t                dmesg_timestamp;
 594         unsigned                apitrace_call_number;
 595
 596         /* Other state */
 597         bool need_check_render_feedback;
 598         bool                    decompression_enabled;
 599
 600         bool                    vs_writes_viewport_index;
 601         bool                    vs_disables_clipping_viewport;
 602
 603         /* Precomputed IA_MULTI_VGT_PARAM */
 604         union si_vgt_param_key  ia_multi_vgt_param_key;
 605         unsigned                ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
 606
 607         /* Bindless descriptors. */
 608         struct si_descriptors   bindless_descriptors;
 609         struct util_idalloc     bindless_used_slots;
 610         unsigned                num_bindless_descriptors;
 611         bool                    bindless_descriptors_dirty;
 612         bool                    graphics_bindless_pointer_dirty;
 613         bool                    compute_bindless_pointer_dirty;
 614
 615         /* Allocated bindless handles */
 616         struct hash_table       *tex_handles;
 617         struct hash_table       *img_handles;
 618
 619         /* Resident bindless handles */
 620         struct util_dynarray    resident_tex_handles;
 621         struct util_dynarray    resident_img_handles;
 622
 623         /* Resident bindless handles which need decompression */
 624         struct util_dynarray    resident_tex_needs_color_decompress;
 625         struct util_dynarray    resident_img_needs_color_decompress;
 626         struct util_dynarray    resident_tex_needs_depth_decompress;
 627
 628         /* Bindless state */
 629         bool                    uses_bindless_samplers;
 630         bool                    uses_bindless_images;
 631
 632         /* MSAA sample locations.
 633          * The first index is the sample index.
 634          * The second index is the coordinate: X, Y. */
 635         float                   sample_locations_1x[1][2];
 636         float                   sample_locations_2x[2][2];
 637         float                   sample_locations_4x[4][2];
 638         float                   sample_locations_8x[8][2];
 639         float                   sample_locations_16x[16][2];
 640 };
 641
 642 /* cik_sdma.c */
 643 void cik_init_sdma_functions(struct si_context *sctx);
 644
 645 /* si_blit.c */
 646 enum si_blitter_op /* bitmask */
 647 {
 648         SI_SAVE_TEXTURES      = 1,
 649         SI_SAVE_FRAMEBUFFER   = 2,
 650         SI_SAVE_FRAGMENT_STATE = 4,
 651         SI_DISABLE_RENDER_COND = 8,
 652 };
 653
 654 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
 655 void si_blitter_end(struct si_context *sctx);
 656 void si_init_blit_functions(struct si_context *sctx);
 657 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
 658 void si_resource_copy_region(struct pipe_context *ctx,
 659                              struct pipe_resource *dst,
 660                              unsigned dst_level,
 661                              unsigned dstx, unsigned dsty, unsigned dstz,
 662                              struct pipe_resource *src,
 663                              unsigned src_level,
 664                              const struct pipe_box *src_box);
 665 void si_decompress_dcc(struct si_context *sctx, struct r600_texture *rtex);
 666 void si_blit_decompress_depth(struct pipe_context *ctx,
 667                               struct r600_texture *texture,
 668                               struct r600_texture *staging,
 669                               unsigned first_level, unsigned last_level,
 670                               unsigned first_layer, unsigned last_layer,
 671                               unsigned first_sample, unsigned last_sample);
 672
 673 /* si_clear.c */
 674 void vi_dcc_clear_level(struct si_context *sctx,
 675                         struct r600_texture *rtex,
 676                         unsigned level, unsigned clear_value);
 677 void si_init_clear_functions(struct si_context *sctx);
 678
 679 /* si_cp_dma.c */
 680 #define SI_CPDMA_SKIP_CHECK_CS_SPACE    (1 << 0) /* don't call need_cs_space */
 681 #define SI_CPDMA_SKIP_SYNC_AFTER        (1 << 1) /* don't wait for DMA after the copy */
 682 #define SI_CPDMA_SKIP_SYNC_BEFORE       (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
 683 #define SI_CPDMA_SKIP_GFX_SYNC          (1 << 3) /* don't flush caches and don't wait for PS/CS */
 684 #define SI_CPDMA_SKIP_BO_LIST_UPDATE    (1 << 4) /* don't update the BO list */
 685 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
 686                            SI_CPDMA_SKIP_SYNC_AFTER | \
 687                            SI_CPDMA_SKIP_SYNC_BEFORE | \
 688                            SI_CPDMA_SKIP_GFX_SYNC | \
 689                            SI_CPDMA_SKIP_BO_LIST_UPDATE)
 690
 691 enum r600_coherency {
 692         R600_COHERENCY_NONE, /* no cache flushes needed */
 693         R600_COHERENCY_SHADER,
 694         R600_COHERENCY_CB_META,
 695 };
 696
 697 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
 698                      uint64_t offset, uint64_t size, unsigned value,
 699                      enum r600_coherency coher);
 700 void si_copy_buffer(struct si_context *sctx,
 701                     struct pipe_resource *dst, struct pipe_resource *src,
 702                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 703                     unsigned user_flags);
 704 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 705                               uint64_t offset, unsigned size);
 706 void cik_emit_prefetch_L2(struct si_context *sctx);
 707 void si_init_cp_dma_functions(struct si_context *sctx);
 708
 709 /* si_debug.c */
 710 void si_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
 711                 struct radeon_saved_cs *saved, bool get_buffer_list);
 712 void si_clear_saved_cs(struct radeon_saved_cs *saved);
 713 void si_destroy_saved_cs(struct si_saved_cs *scs);
 714 void si_auto_log_cs(void *data, struct u_log_context *log);
 715 void si_log_hw_flush(struct si_context *sctx);
 716 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
 717 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
 718 void si_init_debug_functions(struct si_context *sctx);
 719 void si_check_vm_faults(struct si_context *sctx,
 720                         struct radeon_saved_cs *saved, enum ring_type ring);
 721 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
 722
 723 /* si_dma.c */
 724 void si_init_dma_functions(struct si_context *sctx);
 725
 726 /* si_dma_cs.c */
 727 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
 728                        struct r600_resource *dst, struct r600_resource *src);
 729 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
 730                      struct pipe_fence_handle **fence);
 731 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
 732                             uint64_t offset, uint64_t size, unsigned value);
 733
 734 /* si_fence.c */
 735 void si_gfx_write_event_eop(struct si_context *ctx,
 736                             unsigned event, unsigned event_flags,
 737                             unsigned data_sel,
 738                             struct r600_resource *buf, uint64_t va,
 739                             uint32_t new_fence, unsigned query_type);
 740 unsigned si_gfx_write_fence_dwords(struct si_screen *screen);
 741 void si_gfx_wait_fence(struct si_context *ctx,
 742                        uint64_t va, uint32_t ref, uint32_t mask);
 743 void si_init_fence_functions(struct si_context *ctx);
 744 void si_init_screen_fence_functions(struct si_screen *screen);
 745 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
 746                                           struct tc_unflushed_batch_token *tc_token);
 747
 748 /* si_get.c */
 749 const char *si_get_family_name(const struct si_screen *sscreen);
 750 void si_init_screen_get_functions(struct si_screen *sscreen);
 751
 752 /* si_gfx_cs.c */
 753 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
 754                      struct pipe_fence_handle **fence);
 755 void si_begin_new_gfx_cs(struct si_context *ctx);
 756 void si_need_gfx_cs_space(struct si_context *ctx);
 757
 758 /* si_compute.c */
 759 void si_init_compute_functions(struct si_context *sctx);
 760
 761 /* si_perfcounters.c */
 762 void si_init_perfcounters(struct si_screen *screen);
 763
 764 /* si_pipe.c */
 765 bool si_check_device_reset(struct si_context *sctx);
 766
 767 /* si_test_dma.c */
 768 void si_test_dma(struct si_screen *sscreen);
 769
 770 /* si_uvd.c */
 771 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 772                                                const struct pipe_video_codec *templ);
 773
 774 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 775                                                  const struct pipe_video_buffer *tmpl);
 776
 777 /* si_viewport.c */
 778 void si_update_vs_viewport_state(struct si_context *ctx);
 779 void si_init_viewport_functions(struct si_context *ctx);
 780
 781
 782 /*
 783  * common helpers
 784  */
 785
 786 static inline void
 787 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
 788 {
 789         struct r600_resource *res = (struct r600_resource *)r;
 790
 791         if (res) {
 792                 /* Add memory usage for need_gfx_cs_space */
 793                 sctx->b.vram += res->vram_usage;
 794                 sctx->b.gtt += res->gart_usage;
 795         }
 796 }
 797
 798 static inline void
 799 si_invalidate_draw_sh_constants(struct si_context *sctx)
 800 {
 801         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 802 }
 803
 804 static inline void
 805 si_set_atom_dirty(struct si_context *sctx,
 806                   struct r600_atom *atom, bool dirty)
 807 {
 808         unsigned bit = 1 << atom->id;
 809
 810         if (dirty)
 811                 sctx->dirty_atoms |= bit;
 812         else
 813                 sctx->dirty_atoms &= ~bit;
 814 }
 815
 816 static inline bool
 817 si_is_atom_dirty(struct si_context *sctx,
 818                   struct r600_atom *atom)
 819 {
 820         unsigned bit = 1 << atom->id;
 821
 822         return sctx->dirty_atoms & bit;
 823 }
 824
 825 static inline void
 826 si_mark_atom_dirty(struct si_context *sctx,
 827                    struct r600_atom *atom)
 828 {
 829         si_set_atom_dirty(sctx, atom, true);
 830 }
 831
 832 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
 833 {
 834         if (sctx->gs_shader.cso)
 835                 return &sctx->gs_shader;
 836         if (sctx->tes_shader.cso)
 837                 return &sctx->tes_shader;
 838
 839         return &sctx->vs_shader;
 840 }
 841
 842 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 843 {
 844         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 845
 846         return vs->cso ? &vs->cso->info : NULL;
 847 }
 848
 849 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 850 {
 851         if (sctx->gs_shader.cso)
 852                 return sctx->gs_shader.cso->gs_copy_shader;
 853
 854         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 855         return vs->current ? vs->current : NULL;
 856 }
 857
 858 static inline bool si_can_dump_shader(struct si_screen *sscreen,
 859                                       unsigned processor)
 860 {
 861         return sscreen->debug_flags & (1 << processor);
 862 }
 863
 864 static inline bool si_extra_shader_checks(struct si_screen *sscreen,
 865                                           unsigned processor)
 866 {
 867         return (sscreen->debug_flags & DBG(CHECK_IR)) ||
 868                si_can_dump_shader(sscreen, processor);
 869 }
 870
 871 static inline bool si_get_strmout_en(struct si_context *sctx)
 872 {
 873         return sctx->streamout.streamout_enabled ||
 874                sctx->streamout.prims_gen_query_enabled;
 875 }
 876
 877 static inline unsigned
 878 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
 879 {
 880         unsigned alignment, tcc_cache_line_size;
 881
 882         /* If the upload size is less than the cache line size (e.g. 16, 32),
 883          * the whole thing will fit into a cache line if we align it to its size.
 884          * The idea is that multiple small uploads can share a cache line.
 885          * If the upload size is greater, align it to the cache line size.
 886          */
 887         alignment = util_next_power_of_two(upload_size);
 888         tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
 889         return MIN2(alignment, tcc_cache_line_size);
 890 }
 891
 892 static inline void
 893 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
 894 {
 895         if (pipe_reference(&(*dst)->reference, &src->reference))
 896                 si_destroy_saved_cs(*dst);
 897
 898         *dst = src;
 899 }
 900
 901 static inline void
 902 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 903                            bool shaders_read_metadata)
 904 {
 905         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
 906                          SI_CONTEXT_INV_VMEM_L1;
 907
 908         if (sctx->b.chip_class >= GFX9) {
 909                 /* Single-sample color is coherent with shaders on GFX9, but
 910                  * L2 metadata must be flushed if shaders read metadata.
 911                  * (DCC, CMASK).
 912                  */
 913                 if (num_samples >= 2)
 914                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 915                 else if (shaders_read_metadata)
 916                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 917         } else {
 918                 /* SI-CI-VI */
 919                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 920         }
 921 }
 922
 923 static inline void
 924 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 925                            bool include_stencil, bool shaders_read_metadata)
 926 {
 927         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
 928                          SI_CONTEXT_INV_VMEM_L1;
 929
 930         if (sctx->b.chip_class >= GFX9) {
 931                 /* Single-sample depth (not stencil) is coherent with shaders
 932                  * on GFX9, but L2 metadata must be flushed if shaders read
 933                  * metadata.
 934                  */
 935                 if (num_samples >= 2 || include_stencil)
 936                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 937                 else if (shaders_read_metadata)
 938                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 939         } else {
 940                 /* SI-CI-VI */
 941                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 942         }
 943 }
 944
 945 static inline bool
 946 si_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
 947 {
 948         return (stencil_sampler && tex->can_sample_s) ||
 949                (!stencil_sampler && tex->can_sample_z);
 950 }
 951
 952 static inline bool
 953 si_htile_enabled(struct r600_texture *tex, unsigned level)
 954 {
 955         return tex->htile_offset && level == 0;
 956 }
 957
 958 static inline bool
 959 vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level)
 960 {
 961         assert(!tex->tc_compatible_htile || tex->htile_offset);
 962         return tex->tc_compatible_htile && level == 0;
 963 }
 964
 965 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
 966 {
 967         if (sctx->ps_uses_fbfetch)
 968                 return sctx->framebuffer.nr_samples;
 969
 970         return sctx->ps_iter_samples;
 971 }
 972
 973 static inline unsigned si_get_total_colormask(struct si_context *sctx)
 974 {
 975         if (sctx->queued.named.rasterizer->rasterizer_discard)
 976                 return 0;
 977
 978         struct si_shader_selector *ps = sctx->ps_shader.cso;
 979         unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
 980                              sctx->queued.named.blend->cb_target_mask;
 981
 982         if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
 983                 colormask &= ps->colors_written_4bit;
 984         else if (!ps->colors_written_4bit)
 985                 colormask = 0; /* color0 writes all cbufs, but it's not written */
 986
 987         return colormask;
 988 }
 989
 990 #endif