src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef SI_PIPE_H
  27 #define SI_PIPE_H
  28
  29 #include "si_shader.h"
  30
  31 #include "util/u_dynarray.h"
  32 #include "util/u_idalloc.h"
  33
  34 #ifdef PIPE_ARCH_BIG_ENDIAN
  35 #define SI_BIG_ENDIAN 1
  36 #else
  37 #define SI_BIG_ENDIAN 0
  38 #endif
  39
  40 /* The base vertex and primitive restart can be any number, but we must pick
  41  * one which will mean "unknown" for the purpose of state tracking and
  42  * the number shouldn't be a commonly-used one. */
  43 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  44 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  45 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  46 #define SI_GS_PER_ES 128
  47 /* Alignment for optimal CP DMA performance. */
  48 #define SI_CPDMA_ALIGNMENT      32
  49
  50 /* Instruction cache. */
  51 #define SI_CONTEXT_INV_ICACHE           (R600_CONTEXT_PRIVATE_FLAG << 0)
  52 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  53 #define SI_CONTEXT_INV_SMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 1)
  54 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  55 #define SI_CONTEXT_INV_VMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 2)
  56 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  57 #define SI_CONTEXT_INV_GLOBAL_L2        (R600_CONTEXT_PRIVATE_FLAG << 3)
  58 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  59  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
  60 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2  (R600_CONTEXT_PRIVATE_FLAG << 4)
  61 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
  62  * a CB or DB flush. */
  63 #define SI_CONTEXT_INV_L2_METADATA      (R600_CONTEXT_PRIVATE_FLAG << 5)
  64 /* gap */
  65 /* Framebuffer caches. */
  66 #define SI_CONTEXT_FLUSH_AND_INV_DB     (R600_CONTEXT_PRIVATE_FLAG << 7)
  67 #define SI_CONTEXT_FLUSH_AND_INV_CB     (R600_CONTEXT_PRIVATE_FLAG << 8)
  68 /* Engine synchronization. */
  69 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 9)
  70 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 10)
  71 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 11)
  72 #define SI_CONTEXT_VGT_FLUSH            (R600_CONTEXT_PRIVATE_FLAG << 12)
  73 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (R600_CONTEXT_PRIVATE_FLAG << 13)
  74
  75 #define SI_PREFETCH_VBO_DESCRIPTORS     (1 << 0)
  76 #define SI_PREFETCH_LS                  (1 << 1)
  77 #define SI_PREFETCH_HS                  (1 << 2)
  78 #define SI_PREFETCH_ES                  (1 << 3)
  79 #define SI_PREFETCH_GS                  (1 << 4)
  80 #define SI_PREFETCH_VS                  (1 << 5)
  81 #define SI_PREFETCH_PS                  (1 << 6)
  82
  83 #define SI_MAX_BORDER_COLORS    4096
  84 #define SIX_BITS                0x3F
  85
  86 struct si_compute;
  87 struct hash_table;
  88 struct u_suballocator;
  89
  90 struct si_screen {
  91         struct r600_common_screen       b;
  92         unsigned                        gs_table_depth;
  93         unsigned                        tess_offchip_block_dw_size;
  94         bool                            has_clear_state;
  95         bool                            has_distributed_tess;
  96         bool                            has_draw_indirect_multi;
  97         bool                            has_ds_bpermute;
  98         bool                            has_msaa_sample_loc_bug;
  99         bool                            llvm_has_working_vgpr_indexing;
 100
 101         /* Whether shaders are monolithic (1-part) or separate (3-part). */
 102         bool                            use_monolithic_shaders;
 103         bool                            record_llvm_ir;
 104
 105         mtx_t                   shader_parts_mutex;
 106         struct si_shader_part           *vs_prologs;
 107         struct si_shader_part           *tcs_epilogs;
 108         struct si_shader_part           *gs_prologs;
 109         struct si_shader_part           *ps_prologs;
 110         struct si_shader_part           *ps_epilogs;
 111
 112         /* Shader cache in memory.
 113          *
 114          * Design & limitations:
 115          * - The shader cache is per screen (= per process), never saved to
 116          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 117          * - It can only be used with one-variant-per-shader support, in which
 118          *   case only the main (typically middle) part of shaders is cached.
 119          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 120          *   variants of VS and TES are cached, so LS and ES aren't.
 121          * - GS and CS aren't cached, but it's certainly possible to cache
 122          *   those as well.
 123          */
 124         mtx_t                   shader_cache_mutex;
 125         struct hash_table               *shader_cache;
 126
 127         /* Shader compiler queue for multithreaded compilation. */
 128         struct util_queue               shader_compiler_queue;
 129         /* Use at most 3 normal compiler threads on quadcore and better.
 130          * Hyperthreaded CPUs report the number of threads, but we want
 131          * the number of cores. */
 132         LLVMTargetMachineRef            tm[3]; /* used by the queue only */
 133
 134         struct util_queue               shader_compiler_queue_low_priority;
 135         /* Use at most 2 low priority threads on quadcore and better.
 136          * We want to minimize the impact on multithreaded Mesa. */
 137         LLVMTargetMachineRef            tm_low_priority[2]; /* at most 2 threads */
 138 };
 139
 140 struct si_blend_color {
 141         struct r600_atom                atom;
 142         struct pipe_blend_color         state;
 143         bool                            any_nonzeros;
 144 };
 145
 146 struct si_sampler_view {
 147         struct pipe_sampler_view        base;
 148         /* [0..7] = image descriptor
 149          * [4..7] = buffer descriptor */
 150         uint32_t                        state[8];
 151         uint32_t                        fmask_state[8];
 152         const struct legacy_surf_level  *base_level_info;
 153         ubyte                           base_level;
 154         ubyte                           block_width;
 155         bool is_stencil_sampler;
 156         bool dcc_incompatible;
 157 };
 158
 159 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
 160
 161 struct si_sampler_state {
 162 #ifdef DEBUG
 163         unsigned                        magic;
 164 #endif
 165         uint32_t                        val[4];
 166 };
 167
 168 struct si_cs_shader_state {
 169         struct si_compute               *program;
 170         struct si_compute               *emitted_program;
 171         unsigned                        offset;
 172         bool                            initialized;
 173         bool                            uses_scratch;
 174 };
 175
 176 struct si_textures_info {
 177         struct si_sampler_views         views;
 178         uint32_t                        needs_depth_decompress_mask;
 179         uint32_t                        needs_color_decompress_mask;
 180 };
 181
 182 struct si_images_info {
 183         struct pipe_image_view          views[SI_NUM_IMAGES];
 184         uint32_t                        needs_color_decompress_mask;
 185         unsigned                        enabled_mask;
 186 };
 187
 188 struct si_framebuffer {
 189         struct r600_atom                atom;
 190         struct pipe_framebuffer_state   state;
 191         unsigned                        colorbuf_enabled_4bit;
 192         unsigned                        spi_shader_col_format;
 193         unsigned                        spi_shader_col_format_alpha;
 194         unsigned                        spi_shader_col_format_blend;
 195         unsigned                        spi_shader_col_format_blend_alpha;
 196         ubyte                           nr_samples:5; /* at most 16xAA */
 197         ubyte                           log_samples:3; /* at most 4 = 16xAA */
 198         ubyte                           compressed_cb_mask;
 199         ubyte                           color_is_int8;
 200         ubyte                           color_is_int10;
 201         ubyte                           dirty_cbufs;
 202         bool                            dirty_zsbuf;
 203         bool                            any_dst_linear;
 204         bool                            CB_has_shader_readable_metadata;
 205 };
 206
 207 struct si_clip_state {
 208         struct r600_atom                atom;
 209         struct pipe_clip_state          state;
 210         bool                            any_nonzeros;
 211 };
 212
 213 struct si_sample_locs {
 214         struct r600_atom        atom;
 215         unsigned                nr_samples;
 216 };
 217
 218 struct si_sample_mask {
 219         struct r600_atom        atom;
 220         uint16_t                sample_mask;
 221 };
 222
 223 /* A shader state consists of the shader selector, which is a constant state
 224  * object shared by multiple contexts and shouldn't be modified, and
 225  * the current shader variant selected for this context.
 226  */
 227 struct si_shader_ctx_state {
 228         struct si_shader_selector       *cso;
 229         struct si_shader                *current;
 230 };
 231
 232 #define SI_NUM_VGT_PARAM_KEY_BITS 12
 233 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
 234
 235 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
 236  * Some fields are set by state-change calls, most are set by draw_vbo.
 237  */
 238 union si_vgt_param_key {
 239         struct {
 240                 unsigned prim:4;
 241                 unsigned uses_instancing:1;
 242                 unsigned multi_instances_smaller_than_primgroup:1;
 243                 unsigned primitive_restart:1;
 244                 unsigned count_from_stream_output:1;
 245                 unsigned line_stipple_enabled:1;
 246                 unsigned uses_tess:1;
 247                 unsigned tess_uses_prim_id:1;
 248                 unsigned uses_gs:1;
 249                 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
 250         } u;
 251         uint32_t index;
 252 };
 253
 254 struct si_texture_handle
 255 {
 256         unsigned                        desc_slot;
 257         bool                            desc_dirty;
 258         struct pipe_sampler_view        *view;
 259         struct si_sampler_state         sstate;
 260 };
 261
 262 struct si_image_handle
 263 {
 264         unsigned                        desc_slot;
 265         bool                            desc_dirty;
 266         struct pipe_image_view          view;
 267 };
 268
 269 struct si_saved_cs {
 270         struct pipe_reference   reference;
 271         struct si_context       *ctx;
 272         struct radeon_saved_cs  gfx;
 273         struct r600_resource    *trace_buf;
 274         unsigned                trace_id;
 275
 276         unsigned                gfx_last_dw;
 277         bool                    flushed;
 278 };
 279
 280 struct si_context {
 281         struct r600_common_context      b;
 282         struct blitter_context          *blitter;
 283         void                            *custom_dsa_flush;
 284         void                            *custom_blend_resolve;
 285         void                            *custom_blend_fmask_decompress;
 286         void                            *custom_blend_eliminate_fastclear;
 287         void                            *custom_blend_dcc_decompress;
 288         struct si_screen                *screen;
 289         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 290         struct si_shader_ctx_state      fixed_func_tcs_shader;
 291         struct r600_resource            *wait_mem_scratch;
 292         unsigned                        wait_mem_number;
 293         uint16_t                        prefetch_L2_mask;
 294
 295         bool                            gfx_flush_in_progress:1;
 296         bool                            compute_is_busy:1;
 297
 298         /* Atoms (direct states). */
 299         union si_state_atoms            atoms;
 300         unsigned                        dirty_atoms; /* mask */
 301         /* PM4 states (precomputed immutable states) */
 302         unsigned                        dirty_states;
 303         union si_state                  queued;
 304         union si_state                  emitted;
 305
 306         /* Atom declarations. */
 307         struct si_framebuffer           framebuffer;
 308         struct si_sample_locs           msaa_sample_locs;
 309         struct r600_atom                db_render_state;
 310         struct r600_atom                msaa_config;
 311         struct si_sample_mask           sample_mask;
 312         struct r600_atom                cb_render_state;
 313         unsigned                        last_cb_target_mask;
 314         struct si_blend_color           blend_color;
 315         struct r600_atom                clip_regs;
 316         struct si_clip_state            clip_state;
 317         struct si_shader_data           shader_pointers;
 318         struct si_stencil_ref           stencil_ref;
 319         struct r600_atom                spi_map;
 320
 321         /* Precomputed states. */
 322         struct si_pm4_state             *init_config;
 323         struct si_pm4_state             *init_config_gs_rings;
 324         bool                            init_config_has_vgt_flush;
 325         struct si_pm4_state             *vgt_shader_config[4];
 326
 327         /* shaders */
 328         struct si_shader_ctx_state      ps_shader;
 329         struct si_shader_ctx_state      gs_shader;
 330         struct si_shader_ctx_state      vs_shader;
 331         struct si_shader_ctx_state      tcs_shader;
 332         struct si_shader_ctx_state      tes_shader;
 333         struct si_cs_shader_state       cs_shader_state;
 334
 335         /* shader information */
 336         struct si_vertex_elements       *vertex_elements;
 337         unsigned                        sprite_coord_enable;
 338         bool                            flatshade;
 339         bool                            do_update_shaders;
 340
 341         /* shader descriptors */
 342         struct si_descriptors           vertex_buffers;
 343         struct si_descriptors           descriptors[SI_NUM_DESCS];
 344         unsigned                        descriptors_dirty;
 345         unsigned                        shader_pointers_dirty;
 346         unsigned                        shader_needs_decompress_mask;
 347         struct si_buffer_resources      rw_buffers;
 348         struct si_buffer_resources      const_and_shader_buffers[SI_NUM_SHADERS];
 349         struct si_textures_info         samplers[SI_NUM_SHADERS];
 350         struct si_images_info           images[SI_NUM_SHADERS];
 351
 352         /* other shader resources */
 353         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 354         struct pipe_resource            *esgs_ring;
 355         struct pipe_resource            *gsvs_ring;
 356         struct pipe_resource            *tf_ring;
 357         struct pipe_resource            *tess_offchip_ring;
 358         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 359         struct r600_resource            *border_color_buffer;
 360         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 361         unsigned                        border_color_count;
 362
 363         /* Vertex and index buffers. */
 364         bool                            vertex_buffers_dirty;
 365         bool                            vertex_buffer_pointer_dirty;
 366         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 367
 368         /* MSAA config state. */
 369         int                             ps_iter_samples;
 370         bool                            smoothing_enabled;
 371
 372         /* DB render state. */
 373         unsigned                ps_db_shader_control;
 374         unsigned                dbcb_copy_sample;
 375         bool                    dbcb_depth_copy_enabled:1;
 376         bool                    dbcb_stencil_copy_enabled:1;
 377         bool                    db_flush_depth_inplace:1;
 378         bool                    db_flush_stencil_inplace:1;
 379         bool                    db_depth_clear:1;
 380         bool                    db_depth_disable_expclear:1;
 381         bool                    db_stencil_clear:1;
 382         bool                    db_stencil_disable_expclear:1;
 383         bool                    occlusion_queries_disabled:1;
 384         bool                    generate_mipmap_for_depth:1;
 385
 386         /* Emitted draw state. */
 387         bool                    gs_tri_strip_adj_fix:1;
 388         int                     last_index_size;
 389         int                     last_base_vertex;
 390         int                     last_start_instance;
 391         int                     last_drawid;
 392         int                     last_sh_base_reg;
 393         int                     last_primitive_restart_en;
 394         int                     last_restart_index;
 395         int                     last_gs_out_prim;
 396         int                     last_prim;
 397         int                     last_multi_vgt_param;
 398         int                     last_rast_prim;
 399         unsigned                last_sc_line_stipple;
 400         unsigned                current_vs_state;
 401         unsigned                last_vs_state;
 402         enum pipe_prim_type     current_rast_prim; /* primitive type after TES, GS */
 403
 404         /* Scratch buffer */
 405         struct r600_atom        scratch_state;
 406         struct r600_resource    *scratch_buffer;
 407         unsigned                scratch_waves;
 408         unsigned                spi_tmpring_size;
 409
 410         struct r600_resource    *compute_scratch_buffer;
 411
 412         /* Emitted derived tessellation state. */
 413         /* Local shader (VS), or HS if LS-HS are merged. */
 414         struct si_shader        *last_ls;
 415         struct si_shader_selector *last_tcs;
 416         int                     last_num_tcs_input_cp;
 417         int                     last_tes_sh_base;
 418         bool                    last_tess_uses_primid;
 419         unsigned                last_num_patches;
 420
 421         /* Debug state. */
 422         bool                    is_debug;
 423         struct si_saved_cs      *current_saved_cs;
 424         uint64_t                dmesg_timestamp;
 425         unsigned                apitrace_call_number;
 426
 427         /* Other state */
 428         bool need_check_render_feedback;
 429         bool                    decompression_enabled;
 430
 431         /* Precomputed IA_MULTI_VGT_PARAM */
 432         union si_vgt_param_key  ia_multi_vgt_param_key;
 433         unsigned                ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
 434
 435         /* Bindless descriptors. */
 436         struct si_descriptors   bindless_descriptors;
 437         struct util_idalloc     bindless_used_slots;
 438         unsigned                num_bindless_descriptors;
 439         bool                    bindless_descriptors_dirty;
 440         bool                    graphics_bindless_pointer_dirty;
 441         bool                    compute_bindless_pointer_dirty;
 442
 443         /* Allocated bindless handles */
 444         struct hash_table       *tex_handles;
 445         struct hash_table       *img_handles;
 446
 447         /* Resident bindless handles */
 448         struct util_dynarray    resident_tex_handles;
 449         struct util_dynarray    resident_img_handles;
 450
 451         /* Resident bindless handles which need decompression */
 452         struct util_dynarray    resident_tex_needs_color_decompress;
 453         struct util_dynarray    resident_img_needs_color_decompress;
 454         struct util_dynarray    resident_tex_needs_depth_decompress;
 455
 456         /* Bindless state */
 457         bool                    uses_bindless_samplers;
 458         bool                    uses_bindless_images;
 459 };
 460
 461 /* cik_sdma.c */
 462 void cik_init_sdma_functions(struct si_context *sctx);
 463
 464 /* si_blit.c */
 465 void si_init_blit_functions(struct si_context *sctx);
 466 void si_decompress_graphics_textures(struct si_context *sctx);
 467 void si_decompress_compute_textures(struct si_context *sctx);
 468 void si_resource_copy_region(struct pipe_context *ctx,
 469                              struct pipe_resource *dst,
 470                              unsigned dst_level,
 471                              unsigned dstx, unsigned dsty, unsigned dstz,
 472                              struct pipe_resource *src,
 473                              unsigned src_level,
 474                              const struct pipe_box *src_box);
 475
 476 /* si_cp_dma.c */
 477 #define SI_CPDMA_SKIP_CHECK_CS_SPACE    (1 << 0) /* don't call need_cs_space */
 478 #define SI_CPDMA_SKIP_SYNC_AFTER        (1 << 1) /* don't wait for DMA after the copy */
 479 #define SI_CPDMA_SKIP_SYNC_BEFORE       (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
 480 #define SI_CPDMA_SKIP_GFX_SYNC          (1 << 3) /* don't flush caches and don't wait for PS/CS */
 481 #define SI_CPDMA_SKIP_BO_LIST_UPDATE    (1 << 4) /* don't update the BO list */
 482 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
 483                            SI_CPDMA_SKIP_SYNC_AFTER | \
 484                            SI_CPDMA_SKIP_SYNC_BEFORE | \
 485                            SI_CPDMA_SKIP_GFX_SYNC | \
 486                            SI_CPDMA_SKIP_BO_LIST_UPDATE)
 487
 488 void si_copy_buffer(struct si_context *sctx,
 489                     struct pipe_resource *dst, struct pipe_resource *src,
 490                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 491                     unsigned user_flags);
 492 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 493                               uint64_t offset, unsigned size);
 494 void cik_emit_prefetch_L2(struct si_context *sctx);
 495 void si_init_cp_dma_functions(struct si_context *sctx);
 496
 497 /* si_debug.c */
 498 void si_auto_log_cs(void *data, struct u_log_context *log);
 499 void si_log_hw_flush(struct si_context *sctx);
 500 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
 501 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
 502 void si_init_debug_functions(struct si_context *sctx);
 503 void si_check_vm_faults(struct r600_common_context *ctx,
 504                         struct radeon_saved_cs *saved, enum ring_type ring);
 505 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
 506
 507 /* si_dma.c */
 508 void si_init_dma_functions(struct si_context *sctx);
 509
 510 /* si_hw_context.c */
 511 void si_destroy_saved_cs(struct si_saved_cs *scs);
 512 void si_context_gfx_flush(void *context, unsigned flags,
 513                           struct pipe_fence_handle **fence);
 514 void si_begin_new_cs(struct si_context *ctx);
 515 void si_need_cs_space(struct si_context *ctx);
 516
 517 /* si_compute.c */
 518 void si_init_compute_functions(struct si_context *sctx);
 519
 520 /* si_perfcounters.c */
 521 void si_init_perfcounters(struct si_screen *screen);
 522
 523 /* si_uvd.c */
 524 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 525                                                const struct pipe_video_codec *templ);
 526
 527 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 528                                                  const struct pipe_video_buffer *tmpl);
 529
 530 /*
 531  * common helpers
 532  */
 533
 534 static inline void
 535 si_invalidate_draw_sh_constants(struct si_context *sctx)
 536 {
 537         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 538 }
 539
 540 static inline void
 541 si_set_atom_dirty(struct si_context *sctx,
 542                   struct r600_atom *atom, bool dirty)
 543 {
 544         unsigned bit = 1 << atom->id;
 545
 546         if (dirty)
 547                 sctx->dirty_atoms |= bit;
 548         else
 549                 sctx->dirty_atoms &= ~bit;
 550 }
 551
 552 static inline bool
 553 si_is_atom_dirty(struct si_context *sctx,
 554                   struct r600_atom *atom)
 555 {
 556         unsigned bit = 1 << atom->id;
 557
 558         return sctx->dirty_atoms & bit;
 559 }
 560
 561 static inline void
 562 si_mark_atom_dirty(struct si_context *sctx,
 563                    struct r600_atom *atom)
 564 {
 565         si_set_atom_dirty(sctx, atom, true);
 566 }
 567
 568 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
 569 {
 570         if (sctx->gs_shader.cso)
 571                 return &sctx->gs_shader;
 572         if (sctx->tes_shader.cso)
 573                 return &sctx->tes_shader;
 574
 575         return &sctx->vs_shader;
 576 }
 577
 578 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 579 {
 580         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 581
 582         return vs->cso ? &vs->cso->info : NULL;
 583 }
 584
 585 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 586 {
 587         if (sctx->gs_shader.cso)
 588                 return sctx->gs_shader.cso->gs_copy_shader;
 589
 590         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 591         return vs->current ? vs->current : NULL;
 592 }
 593
 594 static inline unsigned
 595 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
 596 {
 597         unsigned alignment, tcc_cache_line_size;
 598
 599         /* If the upload size is less than the cache line size (e.g. 16, 32),
 600          * the whole thing will fit into a cache line if we align it to its size.
 601          * The idea is that multiple small uploads can share a cache line.
 602          * If the upload size is greater, align it to the cache line size.
 603          */
 604         alignment = util_next_power_of_two(upload_size);
 605         tcc_cache_line_size = sctx->screen->b.info.tcc_cache_line_size;
 606         return MIN2(alignment, tcc_cache_line_size);
 607 }
 608
 609 static inline void
 610 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
 611 {
 612         if (pipe_reference(&(*dst)->reference, &src->reference))
 613                 si_destroy_saved_cs(*dst);
 614
 615         *dst = src;
 616 }
 617
 618 static inline void
 619 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 620                            bool shaders_read_metadata)
 621 {
 622         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
 623                          SI_CONTEXT_INV_VMEM_L1;
 624
 625         if (sctx->b.chip_class >= GFX9) {
 626                 /* Single-sample color is coherent with shaders on GFX9, but
 627                  * L2 metadata must be flushed if shaders read metadata.
 628                  * (DCC, CMASK).
 629                  */
 630                 if (num_samples >= 2)
 631                         sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 632                 else if (shaders_read_metadata)
 633                         sctx->b.flags |= SI_CONTEXT_INV_L2_METADATA;
 634         } else {
 635                 /* SI-CI-VI */
 636                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 637         }
 638 }
 639
 640 static inline void
 641 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
 642                            bool include_stencil)
 643 {
 644         sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
 645                          SI_CONTEXT_INV_VMEM_L1;
 646
 647         /* Single-sample depth (not stencil) is coherent with shaders on GFX9. */
 648         if (sctx->b.chip_class <= VI || num_samples >= 2 || include_stencil)
 649                 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 650 }
 651
 652 #endif