2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "si_shader.h"
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
38 #define SI_BIG_ENDIAN 0
41 #define ATI_VENDOR_ID 0x1002
42 #define SI_PRIM_DISCARD_DEBUG 0
43 #define SI_NOT_QUERY 0xffffffff
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
69 * GFX10: This also invalidates the L1 shader array cache. */
70 #define SI_CONTEXT_INV_SCACHE (1 << 4)
71 /* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
72 * GFX10: This also invalidates the L1 shader array cache. */
73 #define SI_CONTEXT_INV_VCACHE (1 << 5)
74 /* L2 cache + L2 metadata cache writeback & invalidate.
75 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
76 #define SI_CONTEXT_INV_L2 (1 << 6)
77 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
78 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
79 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
80 #define SI_CONTEXT_WB_L2 (1 << 7)
81 /* Writeback & invalidate the L2 metadata cache only. It can only be coupled with
82 * a CB or DB flush. */
83 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
84 /* Framebuffer caches. */
85 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
86 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
87 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
88 /* Engine synchronization. */
89 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
90 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
91 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
92 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
93 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
95 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
96 #define SI_PREFETCH_LS (1 << 1)
97 #define SI_PREFETCH_HS (1 << 2)
98 #define SI_PREFETCH_ES (1 << 3)
99 #define SI_PREFETCH_GS (1 << 4)
100 #define SI_PREFETCH_VS (1 << 5)
101 #define SI_PREFETCH_PS (1 << 6)
103 #define SI_MAX_BORDER_COLORS 4096
104 #define SI_MAX_VIEWPORTS 16
105 #define SIX_BITS 0x3F
106 #define SI_MAP_BUFFER_ALIGNMENT 64
107 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
109 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
110 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
111 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
112 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
113 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
114 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
115 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
116 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
117 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
118 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
122 DCC_CLEAR_COLOR_0000
= 0x00000000,
123 DCC_CLEAR_COLOR_0001
= 0x40404040,
124 DCC_CLEAR_COLOR_1110
= 0x80808080,
125 DCC_CLEAR_COLOR_1111
= 0xC0C0C0C0,
126 DCC_CLEAR_COLOR_REG
= 0x20202020,
127 DCC_UNCOMPRESSED
= 0xFFFFFFFF,
130 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
134 /* Shader logging options: */
135 DBG_VS
= PIPE_SHADER_VERTEX
,
136 DBG_PS
= PIPE_SHADER_FRAGMENT
,
137 DBG_GS
= PIPE_SHADER_GEOMETRY
,
138 DBG_TCS
= PIPE_SHADER_TESS_CTRL
,
139 DBG_TES
= PIPE_SHADER_TESS_EVAL
,
140 DBG_CS
= PIPE_SHADER_COMPUTE
,
146 /* Shader compiler options the shader cache should be aware of: */
147 DBG_FS_CORRECT_DERIVS_AFTER_KILL
,
152 /* Shader compiler options (with no effect on the shader cache): */
154 DBG_MONOLITHIC_SHADERS
,
157 /* Information logging options: */
163 /* Driver options: */
171 /* 3D engine options: */
194 DBG_TEST_VMFAULT_SDMA
,
195 DBG_TEST_VMFAULT_SHADER
,
202 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
203 #define DBG(name) (1ull << DBG_##name)
205 enum si_cache_policy
{
207 L2_STREAM
, /* same as SLC=1 */
208 L2_LRU
, /* same as SLC=0 */
212 SI_COHERENCY_NONE
, /* no cache flushes needed */
214 SI_COHERENCY_CB_META
,
219 struct si_shader_context
;
221 struct u_suballocator
;
223 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
227 struct threaded_resource b
;
229 /* Winsys objects. */
230 struct pb_buffer
*buf
;
231 uint64_t gpu_address
;
232 /* Memory usage if the buffer placement is optimal. */
236 /* Resource properties. */
238 unsigned bo_alignment
;
239 enum radeon_bo_domain domains
;
240 enum radeon_bo_flag flags
;
241 unsigned bind_history
;
242 int max_forced_staging_uploads
;
244 /* The buffer range which is initialized (with a write transfer,
245 * streamout, DMA, or as a random access target). The rest of
246 * the buffer is considered invalid and can be mapped unsynchronized.
248 * This allows unsychronized mapping of a buffer range which hasn't
249 * been used yet. It's for applications which forget to use
250 * the unsynchronized map flag and expect the driver to figure it out.
252 struct util_range valid_buffer_range
;
254 /* For buffers only. This indicates that a write operation has been
255 * performed by TC L2, but the cache hasn't been flushed.
256 * Any hw block which doesn't use or bypasses TC L2 should check this
257 * flag and flush the cache before using the buffer.
259 * For example, TC L2 must be flushed if a buffer which has been
260 * modified by a shader store instruction is about to be used as
261 * an index buffer. The reason is that VGT DMA index fetching doesn't
266 /* Whether this resource is referenced by bindless handles. */
267 bool texture_handle_allocated
;
268 bool image_handle_allocated
;
270 /* Whether the resource has been exported via resource_get_handle. */
271 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
275 struct threaded_transfer b
;
276 struct si_resource
*staging
;
281 struct si_resource buffer
;
283 struct radeon_surf surface
;
285 struct si_texture
*flushed_depth_texture
;
287 /* One texture allocation can contain these buffers:
288 * - image (pixel data)
289 * - FMASK buffer (MSAA compression)
290 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
291 * - HTILE buffer (Z/S compression and fast Z/S clear)
292 * - DCC buffer (color compression and new fast color clear)
293 * - displayable DCC buffer (if the DCC buffer is not displayable)
294 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
296 uint64_t fmask_offset
;
297 uint64_t cmask_offset
;
298 uint64_t cmask_base_address_reg
;
299 struct si_resource
*cmask_buffer
;
300 uint64_t dcc_offset
; /* 0 = disabled */
301 uint64_t display_dcc_offset
;
302 uint64_t dcc_retile_map_offset
;
303 unsigned cb_color_info
; /* fast clear enable bit */
304 unsigned color_clear_value
[2];
305 unsigned last_msaa_resolve_target_micro_mode
;
306 unsigned num_level0_transfers
;
308 /* Depth buffer compression and fast clear. */
309 uint64_t htile_offset
;
310 float depth_clear_value
;
311 uint16_t dirty_level_mask
; /* each bit says if that mipmap is compressed */
312 uint16_t stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
313 enum pipe_format db_render_format
:16;
314 uint8_t stencil_clear_value
;
315 bool tc_compatible_htile
:1;
316 bool depth_cleared
:1; /* if it was cleared at least once */
317 bool stencil_cleared
:1; /* if it was cleared at least once */
318 bool upgraded_depth
:1; /* upgraded from unorm to Z32_FLOAT */
320 bool db_compatible
:1;
324 /* We need to track DCC dirtiness, because st/dri usually calls
325 * flush_resource twice per frame (not a bug) and we don't wanna
326 * decompress DCC twice. Also, the dirty tracking must be done even
327 * if DCC isn't used, because it's required by the DCC usage analysis
328 * for a possible future enablement.
330 bool separate_dcc_dirty
:1;
331 /* Statistics gathering for the DCC enablement heuristic. */
332 bool dcc_gather_statistics
:1;
333 /* Counter that should be non-zero if the texture is bound to a
336 unsigned framebuffers_bound
;
337 /* Whether the texture is a displayable back buffer and needs DCC
338 * decompression, which is expensive. Therefore, it's enabled only
339 * if statistics suggest that it will pay off and it's allocated
340 * separately. It can't be bound as a sampler by apps. Limited to
341 * target == 2D and last_level == 0. If enabled, dcc_offset contains
342 * the absolute GPUVM address, not the relative one.
344 struct si_resource
*dcc_separate_buffer
;
345 /* When DCC is temporarily disabled, the separate buffer is here. */
346 struct si_resource
*last_dcc_separate_buffer
;
347 /* Estimate of how much this color buffer is written to in units of
348 * full-screen draws: ps_invocations / (width * height)
349 * Shader kills, late Z, and blending with trivial discards make it
350 * inaccurate (we need to count CB updates, not PS invocations).
352 unsigned ps_draw_ratio
;
353 /* The number of clears since the last DCC usage analysis. */
354 unsigned num_slow_clears
;
358 struct pipe_surface base
;
360 /* These can vary with block-compressed textures. */
364 bool color_initialized
:1;
365 bool depth_initialized
:1;
367 /* Misc. color flags. */
368 bool color_is_int8
:1;
369 bool color_is_int10
:1;
370 bool dcc_incompatible
:1;
372 /* Color registers. */
373 unsigned cb_color_info
;
374 unsigned cb_color_view
;
375 unsigned cb_color_attrib
;
376 unsigned cb_color_attrib2
; /* GFX9 and later */
377 unsigned cb_color_attrib3
; /* GFX10 and later */
378 unsigned cb_dcc_control
; /* GFX8 and later */
379 unsigned spi_shader_col_format
:8; /* no blending, no alpha-to-coverage. */
380 unsigned spi_shader_col_format_alpha
:8; /* alpha-to-coverage */
381 unsigned spi_shader_col_format_blend
:8; /* blending without alpha. */
382 unsigned spi_shader_col_format_blend_alpha
:8; /* blending with alpha. */
385 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE */
386 uint64_t db_stencil_base
;
387 uint64_t db_htile_data_base
;
388 unsigned db_depth_info
;
390 unsigned db_z_info2
; /* GFX9 only */
391 unsigned db_depth_view
;
392 unsigned db_depth_size
;
393 unsigned db_depth_slice
;
394 unsigned db_stencil_info
;
395 unsigned db_stencil_info2
; /* GFX9 only */
396 unsigned db_htile_surface
;
399 struct si_mmio_counter
{
404 union si_mmio_counters
{
406 /* For global GPU load including SDMA. */
407 struct si_mmio_counter gpu
;
410 struct si_mmio_counter spi
;
411 struct si_mmio_counter gui
;
412 struct si_mmio_counter ta
;
413 struct si_mmio_counter gds
;
414 struct si_mmio_counter vgt
;
415 struct si_mmio_counter ia
;
416 struct si_mmio_counter sx
;
417 struct si_mmio_counter wd
;
418 struct si_mmio_counter bci
;
419 struct si_mmio_counter sc
;
420 struct si_mmio_counter pa
;
421 struct si_mmio_counter db
;
422 struct si_mmio_counter cp
;
423 struct si_mmio_counter cb
;
426 struct si_mmio_counter sdma
;
429 struct si_mmio_counter pfp
;
430 struct si_mmio_counter meq
;
431 struct si_mmio_counter me
;
432 struct si_mmio_counter surf_sync
;
433 struct si_mmio_counter cp_dma
;
434 struct si_mmio_counter scratch_ram
;
439 struct si_memory_object
{
440 struct pipe_memory_object b
;
441 struct pb_buffer
*buf
;
445 /* Saved CS data for debugging features. */
446 struct radeon_saved_cs
{
450 struct radeon_bo_list_item
*bo_list
;
455 struct pipe_screen b
;
456 struct radeon_winsys
*ws
;
457 struct disk_cache
*disk_shader_cache
;
459 struct radeon_info info
;
460 uint64_t debug_flags
;
461 char renderer_string
[183];
463 void (*make_texture_descriptor
)(
464 struct si_screen
*screen
,
465 struct si_texture
*tex
,
467 enum pipe_texture_target target
,
468 enum pipe_format pipe_format
,
469 const unsigned char state_swizzle
[4],
470 unsigned first_level
, unsigned last_level
,
471 unsigned first_layer
, unsigned last_layer
,
472 unsigned width
, unsigned height
, unsigned depth
,
474 uint32_t *fmask_state
);
476 unsigned pa_sc_raster_config
;
477 unsigned pa_sc_raster_config_1
;
478 unsigned se_tile_repeat
;
479 unsigned gs_table_depth
;
480 unsigned tess_offchip_block_dw_size
;
481 unsigned tess_offchip_ring_size
;
482 unsigned tess_factor_ring_size
;
483 unsigned vgt_hs_offchip_param
;
484 unsigned eqaa_force_coverage_samples
;
485 unsigned eqaa_force_z_samples
;
486 unsigned eqaa_force_color_samples
;
487 bool has_clear_state
;
488 bool has_distributed_tess
;
489 bool has_draw_indirect_multi
;
490 bool has_out_of_order_rast
;
491 bool assume_no_z_fights
;
492 bool commutative_blend_add
;
493 bool has_gfx9_scissor_bug
;
494 bool has_msaa_sample_loc_bug
;
495 bool has_ls_vgpr_init_bug
;
496 bool has_dcc_constant_encode
;
499 bool llvm_has_working_vgpr_indexing
;
502 #define OPT_BOOL(name, dflt, description) bool name:1;
503 #include "si_debug_options.h"
506 /* Whether shaders are monolithic (1-part) or separate (3-part). */
507 bool use_monolithic_shaders
;
509 bool has_rbplus
; /* if RB+ registers exist */
510 bool rbplus_allowed
; /* if RB+ is allowed */
511 bool dcc_msaa_allowed
;
512 bool cpdma_prefetch_writes_memory
;
514 struct slab_parent_pool pool_transfers
;
516 /* Texture filter settings. */
517 int force_aniso
; /* -1 = disabled */
519 /* Auxiliary context. Mainly used to initialize resources.
520 * It must be locked prior to using and flushed before unlocking. */
521 struct pipe_context
*aux_context
;
522 mtx_t aux_context_lock
;
524 /* This must be in the screen, because UE4 uses one context for
525 * compilation and another one for rendering.
527 unsigned num_compilations
;
528 /* Along with ST_DEBUG=precompile, this should show if applications
529 * are loading shaders on demand. This is a monotonic counter.
531 unsigned num_shaders_created
;
532 unsigned num_shader_cache_hits
;
534 /* GPU load thread. */
535 mtx_t gpu_load_mutex
;
536 thrd_t gpu_load_thread
;
537 union si_mmio_counters mmio_counters
;
538 volatile unsigned gpu_load_stop_thread
; /* bool */
540 /* Performance counters. */
541 struct si_perfcounters
*perfcounters
;
543 /* If pipe_screen wants to recompute and re-emit the framebuffer,
544 * sampler, and image states of all contexts, it should atomically
547 * Each context will compare this with its own last known value of
548 * the counter before drawing and re-emit the states accordingly.
550 unsigned dirty_tex_counter
;
551 unsigned dirty_buf_counter
;
553 /* Atomically increment this counter when an existing texture's
554 * metadata is enabled or disabled in a way that requires changing
555 * contexts' compressed texture binding masks.
557 unsigned compressed_colortex_counter
;
560 /* Context flags to set so that all writes from earlier jobs
561 * in the CP are seen by L2 clients.
565 /* Context flags to set so that all writes from earlier jobs
566 * that end in L2 are seen by CP.
571 mtx_t shader_parts_mutex
;
572 struct si_shader_part
*vs_prologs
;
573 struct si_shader_part
*tcs_epilogs
;
574 struct si_shader_part
*gs_prologs
;
575 struct si_shader_part
*ps_prologs
;
576 struct si_shader_part
*ps_epilogs
;
578 /* Shader cache in memory.
580 * Design & limitations:
581 * - The shader cache is per screen (= per process), never saved to
582 * disk, and skips redundant shader compilations from TGSI to bytecode.
583 * - It can only be used with one-variant-per-shader support, in which
584 * case only the main (typically middle) part of shaders is cached.
585 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
586 * variants of VS and TES are cached, so LS and ES aren't.
587 * - GS and CS aren't cached, but it's certainly possible to cache
590 mtx_t shader_cache_mutex
;
591 struct hash_table
*shader_cache
;
593 /* Shader compiler queue for multithreaded compilation. */
594 struct util_queue shader_compiler_queue
;
595 /* Use at most 3 normal compiler threads on quadcore and better.
596 * Hyperthreaded CPUs report the number of threads, but we want
597 * the number of cores. We only need this many threads for shader-db. */
598 struct ac_llvm_compiler compiler
[24]; /* used by the queue only */
600 struct util_queue shader_compiler_queue_low_priority
;
601 /* Use at most 2 low priority threads on quadcore and better.
602 * We want to minimize the impact on multithreaded Mesa. */
603 struct ac_llvm_compiler compiler_lowp
[10];
606 struct si_blend_color
{
607 struct pipe_blend_color state
;
611 struct si_sampler_view
{
612 struct pipe_sampler_view base
;
613 /* [0..7] = image descriptor
614 * [4..7] = buffer descriptor */
616 uint32_t fmask_state
[8];
617 const struct legacy_surf_level
*base_level_info
;
620 bool is_stencil_sampler
;
622 bool dcc_incompatible
;
625 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
627 struct si_sampler_state
{
632 uint32_t integer_val
[4];
633 uint32_t upgraded_depth_val
[4];
636 struct si_cs_shader_state
{
637 struct si_compute
*program
;
638 struct si_compute
*emitted_program
;
645 struct pipe_sampler_view
*views
[SI_NUM_SAMPLERS
];
646 struct si_sampler_state
*sampler_states
[SI_NUM_SAMPLERS
];
648 /* The i-th bit is set if that element is enabled (non-NULL resource). */
649 unsigned enabled_mask
;
650 uint32_t needs_depth_decompress_mask
;
651 uint32_t needs_color_decompress_mask
;
655 struct pipe_image_view views
[SI_NUM_IMAGES
];
656 uint32_t needs_color_decompress_mask
;
657 unsigned enabled_mask
;
660 struct si_framebuffer
{
661 struct pipe_framebuffer_state state
;
662 unsigned colorbuf_enabled_4bit
;
663 unsigned spi_shader_col_format
;
664 unsigned spi_shader_col_format_alpha
;
665 unsigned spi_shader_col_format_blend
;
666 unsigned spi_shader_col_format_blend_alpha
;
667 ubyte nr_samples
:5; /* at most 16xAA */
668 ubyte log_samples
:3; /* at most 4 = 16xAA */
669 ubyte nr_color_samples
; /* at most 8xAA */
670 ubyte compressed_cb_mask
;
671 ubyte uncompressed_cb_mask
;
673 ubyte color_is_int10
;
675 ubyte dcc_overwrite_combiner_watermark
;
678 bool CB_has_shader_readable_metadata
;
679 bool DB_has_shader_readable_metadata
;
680 bool all_DCC_pipe_aligned
;
684 /* This is the list we want to support. */
685 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH
,
686 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH
,
687 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH
,
690 struct si_signed_scissor
{
695 enum si_quant_mode quant_mode
;
698 struct si_viewports
{
699 struct pipe_viewport_state states
[SI_MAX_VIEWPORTS
];
700 struct si_signed_scissor as_scissor
[SI_MAX_VIEWPORTS
];
704 struct si_clip_state
{
705 struct pipe_clip_state state
;
709 struct si_streamout_target
{
710 struct pipe_stream_output_target b
;
712 /* The buffer where BUFFER_FILLED_SIZE is stored. */
713 struct si_resource
*buf_filled_size
;
714 unsigned buf_filled_size_offset
;
715 bool buf_filled_size_valid
;
717 unsigned stride_in_dw
;
720 struct si_streamout
{
723 unsigned enabled_mask
;
724 unsigned num_targets
;
725 struct si_streamout_target
*targets
[PIPE_MAX_SO_BUFFERS
];
727 unsigned append_bitmask
;
730 /* External state which comes from the vertex shader,
731 * it must be set explicitly when binding a shader. */
732 uint16_t *stride_in_dw
;
733 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
735 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
736 unsigned hw_enabled_mask
;
738 /* The state of VGT_STRMOUT_(CONFIG|EN). */
739 bool streamout_enabled
;
740 bool prims_gen_query_enabled
;
741 int num_prims_gen_queries
;
744 /* A shader state consists of the shader selector, which is a constant state
745 * object shared by multiple contexts and shouldn't be modified, and
746 * the current shader variant selected for this context.
748 struct si_shader_ctx_state
{
749 struct si_shader_selector
*cso
;
750 struct si_shader
*current
;
753 #define SI_NUM_VGT_PARAM_KEY_BITS 12
754 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
756 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
757 * Some fields are set by state-change calls, most are set by draw_vbo.
759 union si_vgt_param_key
{
761 #ifdef PIPE_ARCH_LITTLE_ENDIAN
763 unsigned uses_instancing
:1;
764 unsigned multi_instances_smaller_than_primgroup
:1;
765 unsigned primitive_restart
:1;
766 unsigned count_from_stream_output
:1;
767 unsigned line_stipple_enabled
:1;
768 unsigned uses_tess
:1;
769 unsigned tess_uses_prim_id
:1;
771 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
772 #else /* PIPE_ARCH_BIG_ENDIAN */
773 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
775 unsigned tess_uses_prim_id
:1;
776 unsigned uses_tess
:1;
777 unsigned line_stipple_enabled
:1;
778 unsigned count_from_stream_output
:1;
779 unsigned primitive_restart
:1;
780 unsigned multi_instances_smaller_than_primgroup
:1;
781 unsigned uses_instancing
:1;
788 #define SI_NUM_VGT_STAGES_KEY_BITS 2
789 #define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS)
791 /* The VGT_SHADER_STAGES key used to index the table of precomputed values.
792 * Some fields are set by state-change calls, most are set by draw_vbo.
794 union si_vgt_stages_key
{
796 #ifdef PIPE_ARCH_LITTLE_ENDIAN
799 unsigned _pad
:32 - SI_NUM_VGT_STAGES_KEY_BITS
;
800 #else /* PIPE_ARCH_BIG_ENDIAN */
801 unsigned _pad
:32 - SI_NUM_VGT_STAGES_KEY_BITS
;
809 struct si_texture_handle
813 struct pipe_sampler_view
*view
;
814 struct si_sampler_state sstate
;
817 struct si_image_handle
821 struct pipe_image_view view
;
825 struct pipe_reference reference
;
826 struct si_context
*ctx
;
827 struct radeon_saved_cs gfx
;
828 struct radeon_saved_cs compute
;
829 struct si_resource
*trace_buf
;
832 unsigned gfx_last_dw
;
833 unsigned compute_last_dw
;
838 struct si_sdma_upload
{
839 struct si_resource
*dst
;
840 struct si_resource
*src
;
847 struct pipe_context b
; /* base class */
849 enum radeon_family family
;
850 enum chip_class chip_class
;
852 struct radeon_winsys
*ws
;
853 struct radeon_winsys_ctx
*ctx
;
854 struct radeon_cmdbuf
*gfx_cs
; /* compute IB if graphics is disabled */
855 struct radeon_cmdbuf
*dma_cs
;
856 struct pipe_fence_handle
*last_gfx_fence
;
857 struct pipe_fence_handle
*last_sdma_fence
;
858 struct si_resource
*eop_bug_scratch
;
859 struct u_upload_mgr
*cached_gtt_allocator
;
860 struct threaded_context
*tc
;
861 struct u_suballocator
*allocator_zeroed_memory
;
862 struct slab_child_pool pool_transfers
;
863 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
864 struct pipe_device_reset_callback device_reset_callback
;
865 struct u_log_context
*log
;
866 void *query_result_shader
;
868 void (*emit_cache_flush
)(struct si_context
*ctx
);
870 struct blitter_context
*blitter
;
871 void *custom_dsa_flush
;
872 void *custom_blend_resolve
;
873 void *custom_blend_fmask_decompress
;
874 void *custom_blend_eliminate_fastclear
;
875 void *custom_blend_dcc_decompress
;
877 void *vs_blit_pos_layered
;
879 void *vs_blit_color_layered
;
880 void *vs_blit_texcoord
;
881 void *cs_clear_buffer
;
882 void *cs_copy_buffer
;
884 void *cs_copy_image_1d_array
;
885 void *cs_clear_render_target
;
886 void *cs_clear_render_target_1d_array
;
888 struct si_screen
*screen
;
889 struct pipe_debug_callback debug
;
890 struct ac_llvm_compiler compiler
; /* only non-threaded compilation */
891 struct si_shader_ctx_state fixed_func_tcs_shader
;
892 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
893 struct si_resource
*wait_mem_scratch
;
894 unsigned wait_mem_number
;
895 uint16_t prefetch_L2_mask
;
898 bool gfx_flush_in_progress
:1;
899 bool gfx_last_ib_is_busy
:1;
900 bool compute_is_busy
:1;
902 unsigned num_gfx_cs_flushes
;
903 unsigned initial_gfx_cs_size
;
904 unsigned last_dirty_tex_counter
;
905 unsigned last_dirty_buf_counter
;
906 unsigned last_compressed_colortex_counter
;
907 unsigned last_num_draw_calls
;
908 unsigned flags
; /* flush flags */
909 /* Current unaccounted memory usage. */
913 /* Compute-based primitive discard. */
914 unsigned prim_discard_vertex_count_threshold
;
915 struct pb_buffer
*gds
;
916 struct pb_buffer
*gds_oa
;
917 struct radeon_cmdbuf
*prim_discard_compute_cs
;
918 unsigned compute_gds_offset
;
919 struct si_shader
*compute_ib_last_shader
;
920 uint32_t compute_rewind_va
;
921 unsigned compute_num_prims_in_batch
;
922 bool preserve_prim_restart_gds_at_flush
;
923 /* index_ring is divided into 2 halves for doublebuffering. */
924 struct si_resource
*index_ring
;
925 unsigned index_ring_base
; /* offset of a per-IB portion */
926 unsigned index_ring_offset
; /* offset within a per-IB portion */
927 unsigned index_ring_size_per_ib
; /* max available size per IB */
928 bool prim_discard_compute_ib_initialized
;
929 /* For tracking the last execution barrier - it can be either
930 * a WRITE_DATA packet or a fence. */
931 uint32_t *last_pkt3_write_data
;
932 struct si_resource
*barrier_buf
;
933 unsigned barrier_buf_offset
;
934 struct pipe_fence_handle
*last_ib_barrier_fence
;
935 struct si_resource
*last_ib_barrier_buf
;
936 unsigned last_ib_barrier_buf_offset
;
938 /* Atoms (direct states). */
939 union si_state_atoms atoms
;
940 unsigned dirty_atoms
; /* mask */
941 /* PM4 states (precomputed immutable states) */
942 unsigned dirty_states
;
943 union si_state queued
;
944 union si_state emitted
;
946 /* Atom declarations. */
947 struct si_framebuffer framebuffer
;
948 unsigned sample_locs_num_samples
;
949 uint16_t sample_mask
;
950 unsigned last_cb_target_mask
;
951 struct si_blend_color blend_color
;
952 struct si_clip_state clip_state
;
953 struct si_shader_data shader_pointers
;
954 struct si_stencil_ref stencil_ref
;
955 struct pipe_scissor_state scissors
[SI_MAX_VIEWPORTS
];
956 struct si_streamout streamout
;
957 struct si_viewports viewports
;
958 unsigned num_window_rectangles
;
959 bool window_rectangles_include
;
960 struct pipe_scissor_state window_rectangles
[4];
962 /* Precomputed states. */
963 struct si_pm4_state
*init_config
;
964 struct si_pm4_state
*init_config_gs_rings
;
965 bool init_config_has_vgt_flush
;
966 struct si_pm4_state
*vgt_shader_config
[SI_NUM_VGT_STAGES_STATES
];
969 struct si_shader_ctx_state ps_shader
;
970 struct si_shader_ctx_state gs_shader
;
971 struct si_shader_ctx_state vs_shader
;
972 struct si_shader_ctx_state tcs_shader
;
973 struct si_shader_ctx_state tes_shader
;
974 struct si_shader_ctx_state cs_prim_discard_state
;
975 struct si_cs_shader_state cs_shader_state
;
977 /* shader information */
978 struct si_vertex_elements
*vertex_elements
;
979 unsigned sprite_coord_enable
;
980 unsigned cs_max_waves_per_sh
;
982 bool do_update_shaders
;
984 /* vertex buffer descriptors */
985 uint32_t *vb_descriptors_gpu_list
;
986 struct si_resource
*vb_descriptors_buffer
;
987 unsigned vb_descriptors_offset
;
989 /* shader descriptors */
990 struct si_descriptors descriptors
[SI_NUM_DESCS
];
991 unsigned descriptors_dirty
;
992 unsigned shader_pointers_dirty
;
993 unsigned shader_needs_decompress_mask
;
994 struct si_buffer_resources rw_buffers
;
995 struct si_buffer_resources const_and_shader_buffers
[SI_NUM_SHADERS
];
996 struct si_samplers samplers
[SI_NUM_SHADERS
];
997 struct si_images images
[SI_NUM_SHADERS
];
998 bool bo_list_add_all_resident_resources
;
999 bool bo_list_add_all_gfx_resources
;
1000 bool bo_list_add_all_compute_resources
;
1002 /* other shader resources */
1003 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on GFX7 */
1004 struct pipe_resource
*esgs_ring
;
1005 struct pipe_resource
*gsvs_ring
;
1006 struct pipe_resource
*tess_rings
;
1007 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
1008 struct si_resource
*border_color_buffer
;
1009 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
1010 unsigned border_color_count
;
1011 unsigned num_vs_blit_sgprs
;
1012 uint32_t vs_blit_sh_data
[SI_VS_BLIT_SGPRS_POS_TEXCOORD
];
1013 uint32_t cs_user_data
[4];
1015 /* Vertex and index buffers. */
1016 bool vertex_buffers_dirty
;
1017 bool vertex_buffer_pointer_dirty
;
1018 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
1019 uint16_t vertex_buffer_unaligned
; /* bitmask of not dword-aligned buffers */
1021 /* MSAA config state. */
1022 int ps_iter_samples
;
1023 bool ps_uses_fbfetch
;
1024 bool smoothing_enabled
;
1026 /* DB render state. */
1027 unsigned ps_db_shader_control
;
1028 unsigned dbcb_copy_sample
;
1029 bool dbcb_depth_copy_enabled
:1;
1030 bool dbcb_stencil_copy_enabled
:1;
1031 bool db_flush_depth_inplace
:1;
1032 bool db_flush_stencil_inplace
:1;
1033 bool db_depth_clear
:1;
1034 bool db_depth_disable_expclear
:1;
1035 bool db_stencil_clear
:1;
1036 bool db_stencil_disable_expclear
:1;
1037 bool occlusion_queries_disabled
:1;
1038 bool generate_mipmap_for_depth
:1;
1040 /* Emitted draw state. */
1041 bool gs_tri_strip_adj_fix
:1;
1043 bool prim_discard_cs_instancing
:1;
1045 int last_index_size
;
1046 int last_base_vertex
;
1047 int last_start_instance
;
1048 int last_instance_count
;
1050 int last_sh_base_reg
;
1051 int last_primitive_restart_en
;
1052 int last_restart_index
;
1054 int last_multi_vgt_param
;
1056 unsigned last_sc_line_stipple
;
1057 unsigned current_vs_state
;
1058 unsigned last_vs_state
;
1059 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
1061 /* Scratch buffer */
1062 struct si_resource
*scratch_buffer
;
1063 unsigned scratch_waves
;
1064 unsigned spi_tmpring_size
;
1066 struct si_resource
*compute_scratch_buffer
;
1068 /* Emitted derived tessellation state. */
1069 /* Local shader (VS), or HS if LS-HS are merged. */
1070 struct si_shader
*last_ls
;
1071 struct si_shader_selector
*last_tcs
;
1072 int last_num_tcs_input_cp
;
1073 int last_tes_sh_base
;
1074 bool last_tess_uses_primid
;
1075 unsigned last_num_patches
;
1076 int last_ls_hs_config
;
1080 struct si_saved_cs
*current_saved_cs
;
1081 uint64_t dmesg_timestamp
;
1082 unsigned apitrace_call_number
;
1085 bool need_check_render_feedback
;
1086 bool decompression_enabled
;
1087 bool dpbb_force_off
;
1088 bool vs_writes_viewport_index
;
1089 bool vs_disables_clipping_viewport
;
1091 /* Precomputed IA_MULTI_VGT_PARAM */
1092 union si_vgt_param_key ia_multi_vgt_param_key
;
1093 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
1095 /* Bindless descriptors. */
1096 struct si_descriptors bindless_descriptors
;
1097 struct util_idalloc bindless_used_slots
;
1098 unsigned num_bindless_descriptors
;
1099 bool bindless_descriptors_dirty
;
1100 bool graphics_bindless_pointer_dirty
;
1101 bool compute_bindless_pointer_dirty
;
1103 /* Allocated bindless handles */
1104 struct hash_table
*tex_handles
;
1105 struct hash_table
*img_handles
;
1107 /* Resident bindless handles */
1108 struct util_dynarray resident_tex_handles
;
1109 struct util_dynarray resident_img_handles
;
1111 /* Resident bindless handles which need decompression */
1112 struct util_dynarray resident_tex_needs_color_decompress
;
1113 struct util_dynarray resident_img_needs_color_decompress
;
1114 struct util_dynarray resident_tex_needs_depth_decompress
;
1116 /* Bindless state */
1117 bool uses_bindless_samplers
;
1118 bool uses_bindless_images
;
1120 /* MSAA sample locations.
1121 * The first index is the sample index.
1122 * The second index is the coordinate: X, Y. */
1130 struct pipe_resource
*sample_pos_buffer
;
1133 unsigned num_draw_calls
;
1134 unsigned num_decompress_calls
;
1135 unsigned num_mrt_draw_calls
;
1136 unsigned num_prim_restart_calls
;
1137 unsigned num_spill_draw_calls
;
1138 unsigned num_compute_calls
;
1139 unsigned num_spill_compute_calls
;
1140 unsigned num_dma_calls
;
1141 unsigned num_cp_dma_calls
;
1142 unsigned num_vs_flushes
;
1143 unsigned num_ps_flushes
;
1144 unsigned num_cs_flushes
;
1145 unsigned num_cb_cache_flushes
;
1146 unsigned num_db_cache_flushes
;
1147 unsigned num_L2_invalidates
;
1148 unsigned num_L2_writebacks
;
1149 unsigned num_resident_handles
;
1150 uint64_t num_alloc_tex_transfer_bytes
;
1151 unsigned last_tex_ps_draw_ratio
; /* for query */
1152 unsigned compute_num_verts_accepted
;
1153 unsigned compute_num_verts_rejected
;
1154 unsigned compute_num_verts_ineligible
; /* due to low vertex count */
1155 unsigned context_roll
;
1158 /* Maintain the list of active queries for pausing between IBs. */
1159 int num_occlusion_queries
;
1160 int num_perfect_occlusion_queries
;
1161 int num_pipeline_stat_queries
;
1162 struct list_head active_queries
;
1163 unsigned num_cs_dw_queries_suspend
;
1165 /* Render condition. */
1166 struct pipe_query
*render_cond
;
1167 unsigned render_cond_mode
;
1168 bool render_cond_invert
;
1169 bool render_cond_force_off
; /* for u_blitter */
1171 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1172 bool sdma_uploads_in_progress
;
1173 struct si_sdma_upload
*sdma_uploads
;
1174 unsigned num_sdma_uploads
;
1175 unsigned max_sdma_uploads
;
1177 /* Statistics gathering for the DCC enablement heuristic. It can't be
1178 * in si_texture because si_texture can be shared by multiple
1179 * contexts. This is for back buffers only. We shouldn't get too many
1182 * X11 DRI3 rotates among a finite set of back buffers. They should
1183 * all fit in this array. If they don't, separate DCC might never be
1184 * enabled by DCC stat gathering.
1187 struct si_texture
*tex
;
1188 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1189 struct pipe_query
*ps_stats
[3];
1190 /* If all slots are used and another slot is needed,
1191 * the least recently used slot is evicted based on this. */
1192 int64_t last_use_timestamp
;
1196 /* Copy one resource to another using async DMA. */
1197 void (*dma_copy
)(struct pipe_context
*ctx
,
1198 struct pipe_resource
*dst
,
1200 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
1201 struct pipe_resource
*src
,
1203 const struct pipe_box
*src_box
);
1205 struct si_tracked_regs tracked_regs
;
1209 void cik_init_sdma_functions(struct si_context
*sctx
);
1212 enum si_blitter_op
/* bitmask */
1214 SI_SAVE_TEXTURES
= 1,
1215 SI_SAVE_FRAMEBUFFER
= 2,
1216 SI_SAVE_FRAGMENT_STATE
= 4,
1217 SI_DISABLE_RENDER_COND
= 8,
1220 void si_blitter_begin(struct si_context
*sctx
, enum si_blitter_op op
);
1221 void si_blitter_end(struct si_context
*sctx
);
1222 void si_init_blit_functions(struct si_context
*sctx
);
1223 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
);
1224 void si_resource_copy_region(struct pipe_context
*ctx
,
1225 struct pipe_resource
*dst
,
1227 unsigned dstx
, unsigned dsty
, unsigned dstz
,
1228 struct pipe_resource
*src
,
1230 const struct pipe_box
*src_box
);
1231 void si_decompress_dcc(struct si_context
*sctx
, struct si_texture
*tex
);
1234 bool si_rings_is_buffer_referenced(struct si_context
*sctx
,
1235 struct pb_buffer
*buf
,
1236 enum radeon_bo_usage usage
);
1237 void *si_buffer_map_sync_with_rings(struct si_context
*sctx
,
1238 struct si_resource
*resource
,
1240 void si_init_resource_fields(struct si_screen
*sscreen
,
1241 struct si_resource
*res
,
1242 uint64_t size
, unsigned alignment
);
1243 bool si_alloc_resource(struct si_screen
*sscreen
,
1244 struct si_resource
*res
);
1245 struct pipe_resource
*pipe_aligned_buffer_create(struct pipe_screen
*screen
,
1246 unsigned flags
, unsigned usage
,
1247 unsigned size
, unsigned alignment
);
1248 struct si_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
,
1249 unsigned flags
, unsigned usage
,
1250 unsigned size
, unsigned alignment
);
1251 void si_replace_buffer_storage(struct pipe_context
*ctx
,
1252 struct pipe_resource
*dst
,
1253 struct pipe_resource
*src
);
1254 void si_init_screen_buffer_functions(struct si_screen
*sscreen
);
1255 void si_init_buffer_functions(struct si_context
*sctx
);
1258 enum pipe_format
si_simplify_cb_format(enum pipe_format format
);
1259 bool vi_alpha_is_on_msb(enum pipe_format format
);
1260 void vi_dcc_clear_level(struct si_context
*sctx
,
1261 struct si_texture
*tex
,
1262 unsigned level
, unsigned clear_value
);
1263 void si_init_clear_functions(struct si_context
*sctx
);
1265 /* si_compute_blit.c */
1266 unsigned si_get_flush_flags(struct si_context
*sctx
, enum si_coherency coher
,
1267 enum si_cache_policy cache_policy
);
1268 void si_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1269 uint64_t offset
, uint64_t size
, uint32_t *clear_value
,
1270 uint32_t clear_value_size
, enum si_coherency coher
,
1272 void si_copy_buffer(struct si_context
*sctx
,
1273 struct pipe_resource
*dst
, struct pipe_resource
*src
,
1274 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
);
1275 void si_compute_copy_image(struct si_context
*sctx
,
1276 struct pipe_resource
*dst
,
1278 struct pipe_resource
*src
,
1280 unsigned dstx
, unsigned dsty
, unsigned dstz
,
1281 const struct pipe_box
*src_box
);
1282 void si_compute_clear_render_target(struct pipe_context
*ctx
,
1283 struct pipe_surface
*dstsurf
,
1284 const union pipe_color_union
*color
,
1285 unsigned dstx
, unsigned dsty
,
1286 unsigned width
, unsigned height
,
1287 bool render_condition_enabled
);
1288 void si_retile_dcc(struct si_context
*sctx
, struct si_texture
*tex
);
1289 void si_init_compute_blit_functions(struct si_context
*sctx
);
1292 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1293 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1294 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1295 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1296 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1297 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1298 SI_CPDMA_SKIP_SYNC_AFTER | \
1299 SI_CPDMA_SKIP_SYNC_BEFORE | \
1300 SI_CPDMA_SKIP_GFX_SYNC | \
1301 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1303 void si_cp_dma_wait_for_idle(struct si_context
*sctx
);
1304 void si_cp_dma_clear_buffer(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
,
1305 struct pipe_resource
*dst
, uint64_t offset
,
1306 uint64_t size
, unsigned value
, unsigned user_flags
,
1307 enum si_coherency coher
, enum si_cache_policy cache_policy
);
1308 void si_cp_dma_copy_buffer(struct si_context
*sctx
,
1309 struct pipe_resource
*dst
, struct pipe_resource
*src
,
1310 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
1311 unsigned user_flags
, enum si_coherency coher
,
1312 enum si_cache_policy cache_policy
);
1313 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
1314 uint64_t offset
, unsigned size
);
1315 void cik_emit_prefetch_L2(struct si_context
*sctx
, bool vertex_stage_only
);
1316 void si_test_gds(struct si_context
*sctx
);
1317 void si_cp_write_data(struct si_context
*sctx
, struct si_resource
*buf
,
1318 unsigned offset
, unsigned size
, unsigned dst_sel
,
1319 unsigned engine
, const void *data
);
1320 void si_cp_copy_data(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
,
1321 unsigned dst_sel
, struct si_resource
*dst
, unsigned dst_offset
,
1322 unsigned src_sel
, struct si_resource
*src
, unsigned src_offset
);
1325 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_cmdbuf
*cs
,
1326 struct radeon_saved_cs
*saved
, bool get_buffer_list
);
1327 void si_clear_saved_cs(struct radeon_saved_cs
*saved
);
1328 void si_destroy_saved_cs(struct si_saved_cs
*scs
);
1329 void si_auto_log_cs(void *data
, struct u_log_context
*log
);
1330 void si_log_hw_flush(struct si_context
*sctx
);
1331 void si_log_draw_state(struct si_context
*sctx
, struct u_log_context
*log
);
1332 void si_log_compute_state(struct si_context
*sctx
, struct u_log_context
*log
);
1333 void si_init_debug_functions(struct si_context
*sctx
);
1334 void si_check_vm_faults(struct si_context
*sctx
,
1335 struct radeon_saved_cs
*saved
, enum ring_type ring
);
1336 bool si_replace_shader(unsigned num
, struct si_shader_binary
*binary
);
1339 void si_init_dma_functions(struct si_context
*sctx
);
1342 void si_dma_emit_timestamp(struct si_context
*sctx
, struct si_resource
*dst
,
1344 void si_sdma_clear_buffer(struct si_context
*sctx
, struct pipe_resource
*dst
,
1345 uint64_t offset
, uint64_t size
, unsigned clear_value
);
1346 void si_need_dma_space(struct si_context
*ctx
, unsigned num_dw
,
1347 struct si_resource
*dst
, struct si_resource
*src
);
1348 void si_flush_dma_cs(struct si_context
*ctx
, unsigned flags
,
1349 struct pipe_fence_handle
**fence
);
1350 void si_screen_clear_buffer(struct si_screen
*sscreen
, struct pipe_resource
*dst
,
1351 uint64_t offset
, uint64_t size
, unsigned value
);
1354 void si_cp_release_mem(struct si_context
*ctx
, struct radeon_cmdbuf
*cs
,
1355 unsigned event
, unsigned event_flags
,
1356 unsigned dst_sel
, unsigned int_sel
, unsigned data_sel
,
1357 struct si_resource
*buf
, uint64_t va
,
1358 uint32_t new_fence
, unsigned query_type
);
1359 unsigned si_cp_write_fence_dwords(struct si_screen
*screen
);
1360 void si_cp_wait_mem(struct si_context
*ctx
, struct radeon_cmdbuf
*cs
,
1361 uint64_t va
, uint32_t ref
, uint32_t mask
, unsigned flags
);
1362 void si_init_fence_functions(struct si_context
*ctx
);
1363 void si_init_screen_fence_functions(struct si_screen
*screen
);
1364 struct pipe_fence_handle
*si_create_fence(struct pipe_context
*ctx
,
1365 struct tc_unflushed_batch_token
*tc_token
);
1368 void si_init_screen_get_functions(struct si_screen
*sscreen
);
1371 void si_flush_gfx_cs(struct si_context
*ctx
, unsigned flags
,
1372 struct pipe_fence_handle
**fence
);
1373 void si_begin_new_gfx_cs(struct si_context
*ctx
);
1374 void si_need_gfx_cs_space(struct si_context
*ctx
);
1375 void si_unref_sdma_uploads(struct si_context
*sctx
);
1378 void si_gpu_load_kill_thread(struct si_screen
*sscreen
);
1379 uint64_t si_begin_counter(struct si_screen
*sscreen
, unsigned type
);
1380 unsigned si_end_counter(struct si_screen
*sscreen
, unsigned type
,
1384 void si_emit_initial_compute_regs(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
);
1385 unsigned si_get_compute_resource_limits(struct si_screen
*sscreen
,
1386 unsigned waves_per_threadgroup
,
1387 unsigned max_waves_per_sh
,
1388 unsigned threadgroups_per_cu
);
1389 void si_init_compute_functions(struct si_context
*sctx
);
1391 /* si_compute_prim_discard.c */
1392 enum si_prim_discard_outcome
{
1393 SI_PRIM_DISCARD_ENABLED
,
1394 SI_PRIM_DISCARD_DISABLED
,
1395 SI_PRIM_DISCARD_DRAW_SPLIT
,
1398 void si_build_prim_discard_compute_shader(struct si_shader_context
*ctx
);
1399 enum si_prim_discard_outcome
1400 si_prepare_prim_discard_or_split_draw(struct si_context
*sctx
,
1401 const struct pipe_draw_info
*info
,
1402 bool primitive_restart
);
1403 void si_compute_signal_gfx(struct si_context
*sctx
);
1404 void si_dispatch_prim_discard_cs_and_draw(struct si_context
*sctx
,
1405 const struct pipe_draw_info
*info
,
1406 unsigned index_size
,
1407 unsigned base_vertex
,
1408 uint64_t input_indexbuf_va
,
1409 unsigned input_indexbuf_max_elements
);
1410 void si_initialize_prim_discard_tunables(struct si_context
*sctx
);
1412 /* si_perfcounters.c */
1413 void si_init_perfcounters(struct si_screen
*screen
);
1414 void si_destroy_perfcounters(struct si_screen
*screen
);
1417 bool si_check_device_reset(struct si_context
*sctx
);
1420 void si_init_screen_query_functions(struct si_screen
*sscreen
);
1421 void si_init_query_functions(struct si_context
*sctx
);
1422 void si_suspend_queries(struct si_context
*sctx
);
1423 void si_resume_queries(struct si_context
*sctx
);
1425 /* si_shaderlib_tgsi.c */
1426 void *si_get_blitter_vs(struct si_context
*sctx
, enum blitter_attrib_type type
,
1427 unsigned num_layers
);
1428 void *si_create_fixed_func_tcs(struct si_context
*sctx
);
1429 void *si_create_dma_compute_shader(struct pipe_context
*ctx
,
1430 unsigned num_dwords_per_thread
,
1431 bool dst_stream_cache_policy
, bool is_copy
);
1432 void *si_create_copy_image_compute_shader(struct pipe_context
*ctx
);
1433 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context
*ctx
);
1434 void *si_clear_render_target_shader(struct pipe_context
*ctx
);
1435 void *si_clear_render_target_shader_1d_array(struct pipe_context
*ctx
);
1436 void *si_create_dcc_retile_cs(struct pipe_context
*ctx
);
1437 void *si_create_query_result_cs(struct si_context
*sctx
);
1440 void si_test_dma(struct si_screen
*sscreen
);
1442 /* si_test_clearbuffer.c */
1443 void si_test_dma_perf(struct si_screen
*sscreen
);
1446 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
1447 const struct pipe_video_codec
*templ
);
1449 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
1450 const struct pipe_video_buffer
*tmpl
);
1453 void si_update_vs_viewport_state(struct si_context
*ctx
);
1454 void si_init_viewport_functions(struct si_context
*ctx
);
1457 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
1458 struct si_texture
*dst
,
1459 unsigned dst_level
, unsigned dstx
,
1460 unsigned dsty
, unsigned dstz
,
1461 struct si_texture
*src
,
1463 const struct pipe_box
*src_box
);
1464 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
1465 struct si_texture
*tex
);
1466 void si_texture_discard_cmask(struct si_screen
*sscreen
,
1467 struct si_texture
*tex
);
1468 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1469 struct pipe_resource
*texture
);
1470 void si_print_texture_info(struct si_screen
*sscreen
,
1471 struct si_texture
*tex
, struct u_log_context
*log
);
1472 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1473 const struct pipe_resource
*templ
);
1474 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1475 enum pipe_format format2
);
1476 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1478 enum pipe_format view_format
);
1479 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
1480 struct pipe_resource
*tex
,
1482 enum pipe_format view_format
);
1483 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1484 struct pipe_resource
*texture
,
1485 const struct pipe_surface
*templ
,
1486 unsigned width0
, unsigned height0
,
1487 unsigned width
, unsigned height
);
1488 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
1489 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
1490 struct si_texture
*tex
);
1491 void vi_separate_dcc_start_query(struct si_context
*sctx
,
1492 struct si_texture
*tex
);
1493 void vi_separate_dcc_stop_query(struct si_context
*sctx
,
1494 struct si_texture
*tex
);
1495 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
1496 struct si_texture
*tex
);
1497 bool si_texture_disable_dcc(struct si_context
*sctx
,
1498 struct si_texture
*tex
);
1499 void si_init_screen_texture_functions(struct si_screen
*sscreen
);
1500 void si_init_context_texture_functions(struct si_context
*sctx
);
1507 static inline struct si_resource
*si_resource(struct pipe_resource
*r
)
1509 return (struct si_resource
*)r
;
1513 si_resource_reference(struct si_resource
**ptr
, struct si_resource
*res
)
1515 pipe_resource_reference((struct pipe_resource
**)ptr
,
1516 (struct pipe_resource
*)res
);
1520 si_texture_reference(struct si_texture
**ptr
, struct si_texture
*res
)
1522 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->buffer
.b
.b
);
1526 vi_dcc_enabled(struct si_texture
*tex
, unsigned level
)
1528 return tex
->dcc_offset
&& level
< tex
->surface
.num_dcc_levels
;
1531 static inline unsigned
1532 si_tile_mode_index(struct si_texture
*tex
, unsigned level
, bool stencil
)
1535 return tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
1537 return tex
->surface
.u
.legacy
.tiling_index
[level
];
1540 static inline unsigned
1541 si_get_minimum_num_gfx_cs_dwords(struct si_context
*sctx
)
1543 /* Don't count the needed CS space exactly and just use an upper bound.
1545 * Also reserve space for stopping queries at the end of IB, because
1546 * the number of active queries is unlimited in theory.
1548 return 2048 + sctx
->num_cs_dw_queries_suspend
;
1552 si_context_add_resource_size(struct si_context
*sctx
, struct pipe_resource
*r
)
1555 /* Add memory usage for need_gfx_cs_space */
1556 sctx
->vram
+= si_resource(r
)->vram_usage
;
1557 sctx
->gtt
+= si_resource(r
)->gart_usage
;
1562 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
1564 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
1565 sctx
->last_instance_count
= SI_INSTANCE_COUNT_UNKNOWN
;
1568 static inline unsigned
1569 si_get_atom_bit(struct si_context
*sctx
, struct si_atom
*atom
)
1571 return 1 << (atom
- sctx
->atoms
.array
);
1575 si_set_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
, bool dirty
)
1577 unsigned bit
= si_get_atom_bit(sctx
, atom
);
1580 sctx
->dirty_atoms
|= bit
;
1582 sctx
->dirty_atoms
&= ~bit
;
1586 si_is_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1588 return (sctx
->dirty_atoms
& si_get_atom_bit(sctx
, atom
)) != 0;
1592 si_mark_atom_dirty(struct si_context
*sctx
, struct si_atom
*atom
)
1594 si_set_atom_dirty(sctx
, atom
, true);
1597 static inline struct si_shader_ctx_state
*si_get_vs(struct si_context
*sctx
)
1599 if (sctx
->gs_shader
.cso
)
1600 return &sctx
->gs_shader
;
1601 if (sctx
->tes_shader
.cso
)
1602 return &sctx
->tes_shader
;
1604 return &sctx
->vs_shader
;
1607 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
1609 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1611 return vs
->cso
? &vs
->cso
->info
: NULL
;
1614 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
1616 if (sctx
->gs_shader
.cso
)
1617 return sctx
->gs_shader
.cso
->gs_copy_shader
;
1619 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
1620 return vs
->current
? vs
->current
: NULL
;
1623 static inline bool si_can_dump_shader(struct si_screen
*sscreen
,
1626 return sscreen
->debug_flags
& (1 << processor
);
1629 static inline bool si_get_strmout_en(struct si_context
*sctx
)
1631 return sctx
->streamout
.streamout_enabled
||
1632 sctx
->streamout
.prims_gen_query_enabled
;
1635 static inline unsigned
1636 si_optimal_tcc_alignment(struct si_context
*sctx
, unsigned upload_size
)
1638 unsigned alignment
, tcc_cache_line_size
;
1640 /* If the upload size is less than the cache line size (e.g. 16, 32),
1641 * the whole thing will fit into a cache line if we align it to its size.
1642 * The idea is that multiple small uploads can share a cache line.
1643 * If the upload size is greater, align it to the cache line size.
1645 alignment
= util_next_power_of_two(upload_size
);
1646 tcc_cache_line_size
= sctx
->screen
->info
.tcc_cache_line_size
;
1647 return MIN2(alignment
, tcc_cache_line_size
);
1651 si_saved_cs_reference(struct si_saved_cs
**dst
, struct si_saved_cs
*src
)
1653 if (pipe_reference(&(*dst
)->reference
, &src
->reference
))
1654 si_destroy_saved_cs(*dst
);
1660 si_make_CB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1661 bool shaders_read_metadata
, bool dcc_pipe_aligned
)
1663 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
|
1664 SI_CONTEXT_INV_VCACHE
;
1666 if (sctx
->chip_class
>= GFX9
) {
1667 /* Single-sample color is coherent with shaders on GFX9, but
1668 * L2 metadata must be flushed if shaders read metadata.
1671 if (num_samples
>= 2 ||
1672 (shaders_read_metadata
&& !dcc_pipe_aligned
))
1673 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1674 else if (shaders_read_metadata
)
1675 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1678 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1683 si_make_DB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
1684 bool include_stencil
, bool shaders_read_metadata
)
1686 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB
|
1687 SI_CONTEXT_INV_VCACHE
;
1689 if (sctx
->chip_class
>= GFX9
) {
1690 /* Single-sample depth (not stencil) is coherent with shaders
1691 * on GFX9, but L2 metadata must be flushed if shaders read
1694 if (num_samples
>= 2 || include_stencil
)
1695 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1696 else if (shaders_read_metadata
)
1697 sctx
->flags
|= SI_CONTEXT_INV_L2_METADATA
;
1700 sctx
->flags
|= SI_CONTEXT_INV_L2
;
1705 si_can_sample_zs(struct si_texture
*tex
, bool stencil_sampler
)
1707 return (stencil_sampler
&& tex
->can_sample_s
) ||
1708 (!stencil_sampler
&& tex
->can_sample_z
);
1712 si_htile_enabled(struct si_texture
*tex
, unsigned level
)
1714 return tex
->htile_offset
&& level
== 0;
1718 vi_tc_compat_htile_enabled(struct si_texture
*tex
, unsigned level
)
1720 assert(!tex
->tc_compatible_htile
|| tex
->htile_offset
);
1721 return tex
->tc_compatible_htile
&& level
== 0;
1724 static inline unsigned si_get_ps_iter_samples(struct si_context
*sctx
)
1726 if (sctx
->ps_uses_fbfetch
)
1727 return sctx
->framebuffer
.nr_color_samples
;
1729 return MIN2(sctx
->ps_iter_samples
, sctx
->framebuffer
.nr_color_samples
);
1732 static inline unsigned si_get_total_colormask(struct si_context
*sctx
)
1734 if (sctx
->queued
.named
.rasterizer
->rasterizer_discard
)
1737 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1741 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
1742 sctx
->queued
.named
.blend
->cb_target_mask
;
1744 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
1745 colormask
&= ps
->colors_written_4bit
;
1746 else if (!ps
->colors_written_4bit
)
1747 colormask
= 0; /* color0 writes all cbufs, but it's not written */
1752 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1753 (1 << PIPE_PRIM_LINE_LOOP) | \
1754 (1 << PIPE_PRIM_LINE_STRIP) | \
1755 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1756 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1758 static inline bool util_prim_is_lines(unsigned prim
)
1760 return ((1 << prim
) & UTIL_ALL_PRIM_LINE_MODES
) != 0;
1763 static inline bool util_prim_is_points_or_lines(unsigned prim
)
1765 return ((1 << prim
) & (UTIL_ALL_PRIM_LINE_MODES
|
1766 (1 << PIPE_PRIM_POINTS
))) != 0;
1770 * Return true if there is enough memory in VRAM and GTT for the buffers
1773 * \param vram VRAM memory size not added to the buffer list yet
1774 * \param gtt GTT memory size not added to the buffer list yet
1777 radeon_cs_memory_below_limit(struct si_screen
*screen
,
1778 struct radeon_cmdbuf
*cs
,
1779 uint64_t vram
, uint64_t gtt
)
1781 vram
+= cs
->used_vram
;
1782 gtt
+= cs
->used_gart
;
1784 /* Anything that goes above the VRAM size should go to GTT. */
1785 if (vram
> screen
->info
.vram_size
)
1786 gtt
+= vram
- screen
->info
.vram_size
;
1788 /* Now we just need to check if we have enough GTT. */
1789 return gtt
< screen
->info
.gart_size
* 0.7;
1793 * Add a buffer to the buffer list for the given command stream (CS).
1795 * All buffers used by a CS must be added to the list. This tells the kernel
1796 * driver which buffers are used by GPU commands. Other buffers can
1797 * be swapped out (not accessible) during execution.
1799 * The buffer list becomes empty after every context flush and must be
1802 static inline void radeon_add_to_buffer_list(struct si_context
*sctx
,
1803 struct radeon_cmdbuf
*cs
,
1804 struct si_resource
*bo
,
1805 enum radeon_bo_usage usage
,
1806 enum radeon_bo_priority priority
)
1809 sctx
->ws
->cs_add_buffer(
1811 (enum radeon_bo_usage
)(usage
| RADEON_USAGE_SYNCHRONIZED
),
1812 bo
->domains
, priority
);
1816 * Same as above, but also checks memory usage and flushes the context
1819 * When this SHOULD NOT be used:
1821 * - if si_context_add_resource_size has been called for the buffer
1822 * followed by *_need_cs_space for checking the memory usage
1824 * - if si_need_dma_space has been called for the buffer
1826 * - when emitting state packets and draw packets (because preceding packets
1827 * can't be re-emitted at that point)
1829 * - if shader resource "enabled_mask" is not up-to-date or there is
1830 * a different constraint disallowing a context flush
1833 radeon_add_to_gfx_buffer_list_check_mem(struct si_context
*sctx
,
1834 struct si_resource
*bo
,
1835 enum radeon_bo_usage usage
,
1836 enum radeon_bo_priority priority
,
1840 !radeon_cs_memory_below_limit(sctx
->screen
, sctx
->gfx_cs
,
1841 sctx
->vram
+ bo
->vram_usage
,
1842 sctx
->gtt
+ bo
->gart_usage
))
1843 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1845 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, bo
, usage
, priority
);
1848 static inline bool si_compute_prim_discard_enabled(struct si_context
*sctx
)
1850 return sctx
->prim_discard_vertex_count_threshold
!= UINT_MAX
;
1853 #define PRINT_ERR(fmt, args...) \
1854 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)