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gallium: add pipe_grid_info::last_block
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
34
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
37 #else
38 #define SI_BIG_ENDIAN 0
39 #endif
40
41 #define ATI_VENDOR_ID 0x1002
42
43 #define SI_NOT_QUERY 0xffffffff
44
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
56
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
61
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
69 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
70 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
71 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
72 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
73 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
74 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
75 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
76 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
77 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
78 * a CB or DB flush. */
79 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
80 /* Framebuffer caches. */
81 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
82 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
83 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
84 /* Engine synchronization. */
85 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
86 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
87 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
88 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
89 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
90
91 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
92 #define SI_PREFETCH_LS (1 << 1)
93 #define SI_PREFETCH_HS (1 << 2)
94 #define SI_PREFETCH_ES (1 << 3)
95 #define SI_PREFETCH_GS (1 << 4)
96 #define SI_PREFETCH_VS (1 << 5)
97 #define SI_PREFETCH_PS (1 << 6)
98
99 #define SI_MAX_BORDER_COLORS 4096
100 #define SI_MAX_VIEWPORTS 16
101 #define SIX_BITS 0x3F
102 #define SI_MAP_BUFFER_ALIGNMENT 64
103 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
104
105 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
106 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
107 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
108 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
109 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
110 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
111 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
112 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
113 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
114 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
115
116 enum si_clear_code
117 {
118 DCC_CLEAR_COLOR_0000 = 0x00000000,
119 DCC_CLEAR_COLOR_0001 = 0x40404040,
120 DCC_CLEAR_COLOR_1110 = 0x80808080,
121 DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
122 DCC_CLEAR_COLOR_REG = 0x20202020,
123 DCC_UNCOMPRESSED = 0xFFFFFFFF,
124 };
125
126 /* Debug flags. */
127 enum {
128 /* Shader logging options: */
129 DBG_VS = PIPE_SHADER_VERTEX,
130 DBG_PS = PIPE_SHADER_FRAGMENT,
131 DBG_GS = PIPE_SHADER_GEOMETRY,
132 DBG_TCS = PIPE_SHADER_TESS_CTRL,
133 DBG_TES = PIPE_SHADER_TESS_EVAL,
134 DBG_CS = PIPE_SHADER_COMPUTE,
135 DBG_NO_IR,
136 DBG_NO_TGSI,
137 DBG_NO_ASM,
138 DBG_PREOPT_IR,
139
140 /* Shader compiler options the shader cache should be aware of: */
141 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
142 DBG_UNSAFE_MATH,
143 DBG_SI_SCHED,
144 DBG_GISEL,
145
146 /* Shader compiler options (with no effect on the shader cache): */
147 DBG_CHECK_IR,
148 DBG_NIR,
149 DBG_MONOLITHIC_SHADERS,
150 DBG_NO_OPT_VARIANT,
151
152 /* Information logging options: */
153 DBG_INFO,
154 DBG_TEX,
155 DBG_COMPUTE,
156 DBG_VM,
157
158 /* Driver options: */
159 DBG_FORCE_DMA,
160 DBG_NO_ASYNC_DMA,
161 DBG_NO_WC,
162 DBG_CHECK_VM,
163 DBG_RESERVE_VMID,
164 DBG_ZERO_VRAM,
165
166 /* 3D engine options: */
167 DBG_SWITCH_ON_EOP,
168 DBG_NO_OUT_OF_ORDER,
169 DBG_NO_DPBB,
170 DBG_NO_DFSM,
171 DBG_DPBB,
172 DBG_DFSM,
173 DBG_NO_HYPERZ,
174 DBG_NO_RB_PLUS,
175 DBG_NO_2D_TILING,
176 DBG_NO_TILING,
177 DBG_NO_DCC,
178 DBG_NO_DCC_CLEAR,
179 DBG_NO_DCC_FB,
180 DBG_NO_DCC_MSAA,
181 DBG_NO_FMASK,
182
183 /* Tests: */
184 DBG_TEST_DMA,
185 DBG_TEST_VMFAULT_CP,
186 DBG_TEST_VMFAULT_SDMA,
187 DBG_TEST_VMFAULT_SHADER,
188 DBG_TEST_DMA_PERF,
189 DBG_TEST_GDS,
190 DBG_TEST_GDS_MM,
191 DBG_TEST_GDS_OA_MM,
192 };
193
194 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
195 #define DBG(name) (1ull << DBG_##name)
196
197 enum si_cache_policy {
198 L2_BYPASS,
199 L2_STREAM, /* same as SLC=1 */
200 L2_LRU, /* same as SLC=0 */
201 };
202
203 enum si_coherency {
204 SI_COHERENCY_NONE, /* no cache flushes needed */
205 SI_COHERENCY_SHADER,
206 SI_COHERENCY_CB_META,
207 SI_COHERENCY_CP,
208 };
209
210 struct si_compute;
211 struct hash_table;
212 struct u_suballocator;
213
214 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
215 * at the moment.
216 */
217 struct si_resource {
218 struct threaded_resource b;
219
220 /* Winsys objects. */
221 struct pb_buffer *buf;
222 uint64_t gpu_address;
223 /* Memory usage if the buffer placement is optimal. */
224 uint64_t vram_usage;
225 uint64_t gart_usage;
226
227 /* Resource properties. */
228 uint64_t bo_size;
229 unsigned bo_alignment;
230 enum radeon_bo_domain domains;
231 enum radeon_bo_flag flags;
232 unsigned bind_history;
233 int max_forced_staging_uploads;
234
235 /* The buffer range which is initialized (with a write transfer,
236 * streamout, DMA, or as a random access target). The rest of
237 * the buffer is considered invalid and can be mapped unsynchronized.
238 *
239 * This allows unsychronized mapping of a buffer range which hasn't
240 * been used yet. It's for applications which forget to use
241 * the unsynchronized map flag and expect the driver to figure it out.
242 */
243 struct util_range valid_buffer_range;
244
245 /* For buffers only. This indicates that a write operation has been
246 * performed by TC L2, but the cache hasn't been flushed.
247 * Any hw block which doesn't use or bypasses TC L2 should check this
248 * flag and flush the cache before using the buffer.
249 *
250 * For example, TC L2 must be flushed if a buffer which has been
251 * modified by a shader store instruction is about to be used as
252 * an index buffer. The reason is that VGT DMA index fetching doesn't
253 * use TC L2.
254 */
255 bool TC_L2_dirty;
256
257 /* Whether this resource is referenced by bindless handles. */
258 bool texture_handle_allocated;
259 bool image_handle_allocated;
260
261 /* Whether the resource has been exported via resource_get_handle. */
262 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
263 };
264
265 struct si_transfer {
266 struct threaded_transfer b;
267 struct si_resource *staging;
268 unsigned offset;
269 };
270
271 struct si_texture {
272 struct si_resource buffer;
273
274 struct radeon_surf surface;
275 uint64_t size;
276 struct si_texture *flushed_depth_texture;
277
278 /* Colorbuffer compression and fast clear. */
279 uint64_t fmask_offset;
280 uint64_t cmask_offset;
281 uint64_t cmask_base_address_reg;
282 struct si_resource *cmask_buffer;
283 uint64_t dcc_offset; /* 0 = disabled */
284 unsigned cb_color_info; /* fast clear enable bit */
285 unsigned color_clear_value[2];
286 unsigned last_msaa_resolve_target_micro_mode;
287 unsigned num_level0_transfers;
288
289 /* Depth buffer compression and fast clear. */
290 uint64_t htile_offset;
291 float depth_clear_value;
292 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
293 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
294 enum pipe_format db_render_format:16;
295 uint8_t stencil_clear_value;
296 bool tc_compatible_htile:1;
297 bool depth_cleared:1; /* if it was cleared at least once */
298 bool stencil_cleared:1; /* if it was cleared at least once */
299 bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
300 bool is_depth:1;
301 bool db_compatible:1;
302 bool can_sample_z:1;
303 bool can_sample_s:1;
304
305 /* We need to track DCC dirtiness, because st/dri usually calls
306 * flush_resource twice per frame (not a bug) and we don't wanna
307 * decompress DCC twice. Also, the dirty tracking must be done even
308 * if DCC isn't used, because it's required by the DCC usage analysis
309 * for a possible future enablement.
310 */
311 bool separate_dcc_dirty:1;
312 /* Statistics gathering for the DCC enablement heuristic. */
313 bool dcc_gather_statistics:1;
314 /* Counter that should be non-zero if the texture is bound to a
315 * framebuffer.
316 */
317 unsigned framebuffers_bound;
318 /* Whether the texture is a displayable back buffer and needs DCC
319 * decompression, which is expensive. Therefore, it's enabled only
320 * if statistics suggest that it will pay off and it's allocated
321 * separately. It can't be bound as a sampler by apps. Limited to
322 * target == 2D and last_level == 0. If enabled, dcc_offset contains
323 * the absolute GPUVM address, not the relative one.
324 */
325 struct si_resource *dcc_separate_buffer;
326 /* When DCC is temporarily disabled, the separate buffer is here. */
327 struct si_resource *last_dcc_separate_buffer;
328 /* Estimate of how much this color buffer is written to in units of
329 * full-screen draws: ps_invocations / (width * height)
330 * Shader kills, late Z, and blending with trivial discards make it
331 * inaccurate (we need to count CB updates, not PS invocations).
332 */
333 unsigned ps_draw_ratio;
334 /* The number of clears since the last DCC usage analysis. */
335 unsigned num_slow_clears;
336 };
337
338 struct si_surface {
339 struct pipe_surface base;
340
341 /* These can vary with block-compressed textures. */
342 uint16_t width0;
343 uint16_t height0;
344
345 bool color_initialized:1;
346 bool depth_initialized:1;
347
348 /* Misc. color flags. */
349 bool color_is_int8:1;
350 bool color_is_int10:1;
351 bool dcc_incompatible:1;
352
353 /* Color registers. */
354 unsigned cb_color_info;
355 unsigned cb_color_view;
356 unsigned cb_color_attrib;
357 unsigned cb_color_attrib2; /* GFX9 and later */
358 unsigned cb_dcc_control; /* VI and later */
359 unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */
360 unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
361 unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
362 unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
363
364 /* DB registers. */
365 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
366 uint64_t db_stencil_base;
367 uint64_t db_htile_data_base;
368 unsigned db_depth_info;
369 unsigned db_z_info;
370 unsigned db_z_info2; /* GFX9+ */
371 unsigned db_depth_view;
372 unsigned db_depth_size;
373 unsigned db_depth_slice;
374 unsigned db_stencil_info;
375 unsigned db_stencil_info2; /* GFX9+ */
376 unsigned db_htile_surface;
377 };
378
379 struct si_mmio_counter {
380 unsigned busy;
381 unsigned idle;
382 };
383
384 union si_mmio_counters {
385 struct {
386 /* For global GPU load including SDMA. */
387 struct si_mmio_counter gpu;
388
389 /* GRBM_STATUS */
390 struct si_mmio_counter spi;
391 struct si_mmio_counter gui;
392 struct si_mmio_counter ta;
393 struct si_mmio_counter gds;
394 struct si_mmio_counter vgt;
395 struct si_mmio_counter ia;
396 struct si_mmio_counter sx;
397 struct si_mmio_counter wd;
398 struct si_mmio_counter bci;
399 struct si_mmio_counter sc;
400 struct si_mmio_counter pa;
401 struct si_mmio_counter db;
402 struct si_mmio_counter cp;
403 struct si_mmio_counter cb;
404
405 /* SRBM_STATUS2 */
406 struct si_mmio_counter sdma;
407
408 /* CP_STAT */
409 struct si_mmio_counter pfp;
410 struct si_mmio_counter meq;
411 struct si_mmio_counter me;
412 struct si_mmio_counter surf_sync;
413 struct si_mmio_counter cp_dma;
414 struct si_mmio_counter scratch_ram;
415 } named;
416 unsigned array[0];
417 };
418
419 struct si_memory_object {
420 struct pipe_memory_object b;
421 struct pb_buffer *buf;
422 uint32_t stride;
423 };
424
425 /* Saved CS data for debugging features. */
426 struct radeon_saved_cs {
427 uint32_t *ib;
428 unsigned num_dw;
429
430 struct radeon_bo_list_item *bo_list;
431 unsigned bo_count;
432 };
433
434 struct si_screen {
435 struct pipe_screen b;
436 struct radeon_winsys *ws;
437 struct disk_cache *disk_shader_cache;
438
439 struct radeon_info info;
440 uint64_t debug_flags;
441 char renderer_string[183];
442
443 unsigned pa_sc_raster_config;
444 unsigned pa_sc_raster_config_1;
445 unsigned se_tile_repeat;
446 unsigned gs_table_depth;
447 unsigned tess_offchip_block_dw_size;
448 unsigned tess_offchip_ring_size;
449 unsigned tess_factor_ring_size;
450 unsigned vgt_hs_offchip_param;
451 unsigned eqaa_force_coverage_samples;
452 unsigned eqaa_force_z_samples;
453 unsigned eqaa_force_color_samples;
454 bool has_clear_state;
455 bool has_distributed_tess;
456 bool has_draw_indirect_multi;
457 bool has_out_of_order_rast;
458 bool assume_no_z_fights;
459 bool commutative_blend_add;
460 bool clear_db_cache_before_clear;
461 bool has_msaa_sample_loc_bug;
462 bool has_ls_vgpr_init_bug;
463 bool has_dcc_constant_encode;
464 bool dpbb_allowed;
465 bool dfsm_allowed;
466 bool llvm_has_working_vgpr_indexing;
467
468 /* Whether shaders are monolithic (1-part) or separate (3-part). */
469 bool use_monolithic_shaders;
470 bool record_llvm_ir;
471 bool has_rbplus; /* if RB+ registers exist */
472 bool rbplus_allowed; /* if RB+ is allowed */
473 bool dcc_msaa_allowed;
474 bool cpdma_prefetch_writes_memory;
475
476 struct slab_parent_pool pool_transfers;
477
478 /* Texture filter settings. */
479 int force_aniso; /* -1 = disabled */
480
481 /* Auxiliary context. Mainly used to initialize resources.
482 * It must be locked prior to using and flushed before unlocking. */
483 struct pipe_context *aux_context;
484 mtx_t aux_context_lock;
485
486 /* This must be in the screen, because UE4 uses one context for
487 * compilation and another one for rendering.
488 */
489 unsigned num_compilations;
490 /* Along with ST_DEBUG=precompile, this should show if applications
491 * are loading shaders on demand. This is a monotonic counter.
492 */
493 unsigned num_shaders_created;
494 unsigned num_shader_cache_hits;
495
496 /* GPU load thread. */
497 mtx_t gpu_load_mutex;
498 thrd_t gpu_load_thread;
499 union si_mmio_counters mmio_counters;
500 volatile unsigned gpu_load_stop_thread; /* bool */
501
502 /* Performance counters. */
503 struct si_perfcounters *perfcounters;
504
505 /* If pipe_screen wants to recompute and re-emit the framebuffer,
506 * sampler, and image states of all contexts, it should atomically
507 * increment this.
508 *
509 * Each context will compare this with its own last known value of
510 * the counter before drawing and re-emit the states accordingly.
511 */
512 unsigned dirty_tex_counter;
513
514 /* Atomically increment this counter when an existing texture's
515 * metadata is enabled or disabled in a way that requires changing
516 * contexts' compressed texture binding masks.
517 */
518 unsigned compressed_colortex_counter;
519
520 struct {
521 /* Context flags to set so that all writes from earlier jobs
522 * in the CP are seen by L2 clients.
523 */
524 unsigned cp_to_L2;
525
526 /* Context flags to set so that all writes from earlier jobs
527 * that end in L2 are seen by CP.
528 */
529 unsigned L2_to_cp;
530 } barrier_flags;
531
532 mtx_t shader_parts_mutex;
533 struct si_shader_part *vs_prologs;
534 struct si_shader_part *tcs_epilogs;
535 struct si_shader_part *gs_prologs;
536 struct si_shader_part *ps_prologs;
537 struct si_shader_part *ps_epilogs;
538
539 /* Shader cache in memory.
540 *
541 * Design & limitations:
542 * - The shader cache is per screen (= per process), never saved to
543 * disk, and skips redundant shader compilations from TGSI to bytecode.
544 * - It can only be used with one-variant-per-shader support, in which
545 * case only the main (typically middle) part of shaders is cached.
546 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
547 * variants of VS and TES are cached, so LS and ES aren't.
548 * - GS and CS aren't cached, but it's certainly possible to cache
549 * those as well.
550 */
551 mtx_t shader_cache_mutex;
552 struct hash_table *shader_cache;
553
554 /* Shader compiler queue for multithreaded compilation. */
555 struct util_queue shader_compiler_queue;
556 /* Use at most 3 normal compiler threads on quadcore and better.
557 * Hyperthreaded CPUs report the number of threads, but we want
558 * the number of cores. We only need this many threads for shader-db. */
559 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
560
561 struct util_queue shader_compiler_queue_low_priority;
562 /* Use at most 2 low priority threads on quadcore and better.
563 * We want to minimize the impact on multithreaded Mesa. */
564 struct ac_llvm_compiler compiler_lowp[10];
565 };
566
567 struct si_blend_color {
568 struct pipe_blend_color state;
569 bool any_nonzeros;
570 };
571
572 struct si_sampler_view {
573 struct pipe_sampler_view base;
574 /* [0..7] = image descriptor
575 * [4..7] = buffer descriptor */
576 uint32_t state[8];
577 uint32_t fmask_state[8];
578 const struct legacy_surf_level *base_level_info;
579 ubyte base_level;
580 ubyte block_width;
581 bool is_stencil_sampler;
582 bool is_integer;
583 bool dcc_incompatible;
584 };
585
586 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
587
588 struct si_sampler_state {
589 #ifdef DEBUG
590 unsigned magic;
591 #endif
592 uint32_t val[4];
593 uint32_t integer_val[4];
594 uint32_t upgraded_depth_val[4];
595 };
596
597 struct si_cs_shader_state {
598 struct si_compute *program;
599 struct si_compute *emitted_program;
600 unsigned offset;
601 bool initialized;
602 bool uses_scratch;
603 };
604
605 struct si_samplers {
606 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
607 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
608
609 /* The i-th bit is set if that element is enabled (non-NULL resource). */
610 unsigned enabled_mask;
611 uint32_t needs_depth_decompress_mask;
612 uint32_t needs_color_decompress_mask;
613 };
614
615 struct si_images {
616 struct pipe_image_view views[SI_NUM_IMAGES];
617 uint32_t needs_color_decompress_mask;
618 unsigned enabled_mask;
619 };
620
621 struct si_framebuffer {
622 struct pipe_framebuffer_state state;
623 unsigned colorbuf_enabled_4bit;
624 unsigned spi_shader_col_format;
625 unsigned spi_shader_col_format_alpha;
626 unsigned spi_shader_col_format_blend;
627 unsigned spi_shader_col_format_blend_alpha;
628 ubyte nr_samples:5; /* at most 16xAA */
629 ubyte log_samples:3; /* at most 4 = 16xAA */
630 ubyte nr_color_samples; /* at most 8xAA */
631 ubyte compressed_cb_mask;
632 ubyte uncompressed_cb_mask;
633 ubyte color_is_int8;
634 ubyte color_is_int10;
635 ubyte dirty_cbufs;
636 ubyte dcc_overwrite_combiner_watermark;
637 bool dirty_zsbuf;
638 bool any_dst_linear;
639 bool CB_has_shader_readable_metadata;
640 bool DB_has_shader_readable_metadata;
641 };
642
643 enum si_quant_mode {
644 /* This is the list we want to support. */
645 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
646 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
647 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
648 };
649
650 struct si_signed_scissor {
651 int minx;
652 int miny;
653 int maxx;
654 int maxy;
655 enum si_quant_mode quant_mode;
656 };
657
658 struct si_scissors {
659 unsigned dirty_mask;
660 struct pipe_scissor_state states[SI_MAX_VIEWPORTS];
661 };
662
663 struct si_viewports {
664 unsigned dirty_mask;
665 unsigned depth_range_dirty_mask;
666 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
667 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
668 };
669
670 struct si_clip_state {
671 struct pipe_clip_state state;
672 bool any_nonzeros;
673 };
674
675 struct si_streamout_target {
676 struct pipe_stream_output_target b;
677
678 /* The buffer where BUFFER_FILLED_SIZE is stored. */
679 struct si_resource *buf_filled_size;
680 unsigned buf_filled_size_offset;
681 bool buf_filled_size_valid;
682
683 unsigned stride_in_dw;
684 };
685
686 struct si_streamout {
687 bool begin_emitted;
688
689 unsigned enabled_mask;
690 unsigned num_targets;
691 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
692
693 unsigned append_bitmask;
694 bool suspended;
695
696 /* External state which comes from the vertex shader,
697 * it must be set explicitly when binding a shader. */
698 uint16_t *stride_in_dw;
699 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
700
701 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
702 unsigned hw_enabled_mask;
703
704 /* The state of VGT_STRMOUT_(CONFIG|EN). */
705 bool streamout_enabled;
706 bool prims_gen_query_enabled;
707 int num_prims_gen_queries;
708 };
709
710 /* A shader state consists of the shader selector, which is a constant state
711 * object shared by multiple contexts and shouldn't be modified, and
712 * the current shader variant selected for this context.
713 */
714 struct si_shader_ctx_state {
715 struct si_shader_selector *cso;
716 struct si_shader *current;
717 };
718
719 #define SI_NUM_VGT_PARAM_KEY_BITS 12
720 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
721
722 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
723 * Some fields are set by state-change calls, most are set by draw_vbo.
724 */
725 union si_vgt_param_key {
726 struct {
727 #ifdef PIPE_ARCH_LITTLE_ENDIAN
728 unsigned prim:4;
729 unsigned uses_instancing:1;
730 unsigned multi_instances_smaller_than_primgroup:1;
731 unsigned primitive_restart:1;
732 unsigned count_from_stream_output:1;
733 unsigned line_stipple_enabled:1;
734 unsigned uses_tess:1;
735 unsigned tess_uses_prim_id:1;
736 unsigned uses_gs:1;
737 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
738 #else /* PIPE_ARCH_BIG_ENDIAN */
739 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
740 unsigned uses_gs:1;
741 unsigned tess_uses_prim_id:1;
742 unsigned uses_tess:1;
743 unsigned line_stipple_enabled:1;
744 unsigned count_from_stream_output:1;
745 unsigned primitive_restart:1;
746 unsigned multi_instances_smaller_than_primgroup:1;
747 unsigned uses_instancing:1;
748 unsigned prim:4;
749 #endif
750 } u;
751 uint32_t index;
752 };
753
754 struct si_texture_handle
755 {
756 unsigned desc_slot;
757 bool desc_dirty;
758 struct pipe_sampler_view *view;
759 struct si_sampler_state sstate;
760 };
761
762 struct si_image_handle
763 {
764 unsigned desc_slot;
765 bool desc_dirty;
766 struct pipe_image_view view;
767 };
768
769 struct si_saved_cs {
770 struct pipe_reference reference;
771 struct si_context *ctx;
772 struct radeon_saved_cs gfx;
773 struct si_resource *trace_buf;
774 unsigned trace_id;
775
776 unsigned gfx_last_dw;
777 bool flushed;
778 int64_t time_flush;
779 };
780
781 struct si_sdma_upload {
782 struct si_resource *dst;
783 struct si_resource *src;
784 unsigned src_offset;
785 unsigned dst_offset;
786 unsigned size;
787 };
788
789 struct si_context {
790 struct pipe_context b; /* base class */
791
792 enum radeon_family family;
793 enum chip_class chip_class;
794
795 struct radeon_winsys *ws;
796 struct radeon_winsys_ctx *ctx;
797 struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
798 struct radeon_cmdbuf *dma_cs;
799 struct pipe_fence_handle *last_gfx_fence;
800 struct pipe_fence_handle *last_sdma_fence;
801 struct si_resource *eop_bug_scratch;
802 struct u_upload_mgr *cached_gtt_allocator;
803 struct threaded_context *tc;
804 struct u_suballocator *allocator_zeroed_memory;
805 struct slab_child_pool pool_transfers;
806 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
807 struct pipe_device_reset_callback device_reset_callback;
808 struct u_log_context *log;
809 void *query_result_shader;
810 struct blitter_context *blitter;
811 void *custom_dsa_flush;
812 void *custom_blend_resolve;
813 void *custom_blend_fmask_decompress;
814 void *custom_blend_eliminate_fastclear;
815 void *custom_blend_dcc_decompress;
816 void *vs_blit_pos;
817 void *vs_blit_pos_layered;
818 void *vs_blit_color;
819 void *vs_blit_color_layered;
820 void *vs_blit_texcoord;
821 void *cs_clear_buffer;
822 void *cs_copy_buffer;
823 void *cs_copy_image;
824 void *cs_copy_image_1d_array;
825 void *cs_clear_render_target;
826 void *cs_clear_render_target_1d_array;
827 struct si_screen *screen;
828 struct pipe_debug_callback debug;
829 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
830 struct si_shader_ctx_state fixed_func_tcs_shader;
831 struct si_resource *wait_mem_scratch;
832 unsigned wait_mem_number;
833 uint16_t prefetch_L2_mask;
834
835 bool has_graphics;
836 bool gfx_flush_in_progress:1;
837 bool gfx_last_ib_is_busy:1;
838 bool compute_is_busy:1;
839
840 unsigned num_gfx_cs_flushes;
841 unsigned initial_gfx_cs_size;
842 unsigned gpu_reset_counter;
843 unsigned last_dirty_tex_counter;
844 unsigned last_compressed_colortex_counter;
845 unsigned last_num_draw_calls;
846 unsigned flags; /* flush flags */
847 /* Current unaccounted memory usage. */
848 uint64_t vram;
849 uint64_t gtt;
850
851 /* Atoms (direct states). */
852 union si_state_atoms atoms;
853 unsigned dirty_atoms; /* mask */
854 /* PM4 states (precomputed immutable states) */
855 unsigned dirty_states;
856 union si_state queued;
857 union si_state emitted;
858
859 /* Atom declarations. */
860 struct si_framebuffer framebuffer;
861 unsigned sample_locs_num_samples;
862 uint16_t sample_mask;
863 unsigned last_cb_target_mask;
864 struct si_blend_color blend_color;
865 struct si_clip_state clip_state;
866 struct si_shader_data shader_pointers;
867 struct si_stencil_ref stencil_ref;
868 struct si_scissors scissors;
869 struct si_streamout streamout;
870 struct si_viewports viewports;
871 unsigned num_window_rectangles;
872 bool window_rectangles_include;
873 struct pipe_scissor_state window_rectangles[4];
874
875 /* Precomputed states. */
876 struct si_pm4_state *init_config;
877 struct si_pm4_state *init_config_gs_rings;
878 bool init_config_has_vgt_flush;
879 struct si_pm4_state *vgt_shader_config[4];
880
881 /* shaders */
882 struct si_shader_ctx_state ps_shader;
883 struct si_shader_ctx_state gs_shader;
884 struct si_shader_ctx_state vs_shader;
885 struct si_shader_ctx_state tcs_shader;
886 struct si_shader_ctx_state tes_shader;
887 struct si_cs_shader_state cs_shader_state;
888
889 /* shader information */
890 struct si_vertex_elements *vertex_elements;
891 unsigned sprite_coord_enable;
892 unsigned cs_max_waves_per_sh;
893 bool flatshade;
894 bool do_update_shaders;
895
896 /* vertex buffer descriptors */
897 uint32_t *vb_descriptors_gpu_list;
898 struct si_resource *vb_descriptors_buffer;
899 unsigned vb_descriptors_offset;
900
901 /* shader descriptors */
902 struct si_descriptors descriptors[SI_NUM_DESCS];
903 unsigned descriptors_dirty;
904 unsigned shader_pointers_dirty;
905 unsigned shader_needs_decompress_mask;
906 struct si_buffer_resources rw_buffers;
907 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
908 struct si_samplers samplers[SI_NUM_SHADERS];
909 struct si_images images[SI_NUM_SHADERS];
910
911 /* other shader resources */
912 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
913 struct pipe_resource *esgs_ring;
914 struct pipe_resource *gsvs_ring;
915 struct pipe_resource *tess_rings;
916 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
917 struct si_resource *border_color_buffer;
918 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
919 unsigned border_color_count;
920 unsigned num_vs_blit_sgprs;
921 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
922 uint32_t cs_user_data[4];
923
924 /* Vertex and index buffers. */
925 bool vertex_buffers_dirty;
926 bool vertex_buffer_pointer_dirty;
927 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
928
929 /* MSAA config state. */
930 int ps_iter_samples;
931 bool ps_uses_fbfetch;
932 bool smoothing_enabled;
933
934 /* DB render state. */
935 unsigned ps_db_shader_control;
936 unsigned dbcb_copy_sample;
937 bool dbcb_depth_copy_enabled:1;
938 bool dbcb_stencil_copy_enabled:1;
939 bool db_flush_depth_inplace:1;
940 bool db_flush_stencil_inplace:1;
941 bool db_depth_clear:1;
942 bool db_depth_disable_expclear:1;
943 bool db_stencil_clear:1;
944 bool db_stencil_disable_expclear:1;
945 bool occlusion_queries_disabled:1;
946 bool generate_mipmap_for_depth:1;
947
948 /* Emitted draw state. */
949 bool gs_tri_strip_adj_fix:1;
950 bool ls_vgpr_fix:1;
951 int last_index_size;
952 int last_base_vertex;
953 int last_start_instance;
954 int last_instance_count;
955 int last_drawid;
956 int last_sh_base_reg;
957 int last_primitive_restart_en;
958 int last_restart_index;
959 int last_prim;
960 int last_multi_vgt_param;
961 int last_rast_prim;
962 unsigned last_sc_line_stipple;
963 unsigned current_vs_state;
964 unsigned last_vs_state;
965 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
966
967 /* Scratch buffer */
968 struct si_resource *scratch_buffer;
969 unsigned scratch_waves;
970 unsigned spi_tmpring_size;
971
972 struct si_resource *compute_scratch_buffer;
973
974 /* Emitted derived tessellation state. */
975 /* Local shader (VS), or HS if LS-HS are merged. */
976 struct si_shader *last_ls;
977 struct si_shader_selector *last_tcs;
978 int last_num_tcs_input_cp;
979 int last_tes_sh_base;
980 bool last_tess_uses_primid;
981 unsigned last_num_patches;
982 int last_ls_hs_config;
983
984 /* Debug state. */
985 bool is_debug;
986 struct si_saved_cs *current_saved_cs;
987 uint64_t dmesg_timestamp;
988 unsigned apitrace_call_number;
989
990 /* Other state */
991 bool need_check_render_feedback;
992 bool decompression_enabled;
993 bool dpbb_force_off;
994 bool vs_writes_viewport_index;
995 bool vs_disables_clipping_viewport;
996
997 /* Precomputed IA_MULTI_VGT_PARAM */
998 union si_vgt_param_key ia_multi_vgt_param_key;
999 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1000
1001 /* Bindless descriptors. */
1002 struct si_descriptors bindless_descriptors;
1003 struct util_idalloc bindless_used_slots;
1004 unsigned num_bindless_descriptors;
1005 bool bindless_descriptors_dirty;
1006 bool graphics_bindless_pointer_dirty;
1007 bool compute_bindless_pointer_dirty;
1008
1009 /* Allocated bindless handles */
1010 struct hash_table *tex_handles;
1011 struct hash_table *img_handles;
1012
1013 /* Resident bindless handles */
1014 struct util_dynarray resident_tex_handles;
1015 struct util_dynarray resident_img_handles;
1016
1017 /* Resident bindless handles which need decompression */
1018 struct util_dynarray resident_tex_needs_color_decompress;
1019 struct util_dynarray resident_img_needs_color_decompress;
1020 struct util_dynarray resident_tex_needs_depth_decompress;
1021
1022 /* Bindless state */
1023 bool uses_bindless_samplers;
1024 bool uses_bindless_images;
1025
1026 /* MSAA sample locations.
1027 * The first index is the sample index.
1028 * The second index is the coordinate: X, Y. */
1029 struct {
1030 float x1[1][2];
1031 float x2[2][2];
1032 float x4[4][2];
1033 float x8[8][2];
1034 float x16[16][2];
1035 } sample_positions;
1036 struct pipe_resource *sample_pos_buffer;
1037
1038 /* Misc stats. */
1039 unsigned num_draw_calls;
1040 unsigned num_decompress_calls;
1041 unsigned num_mrt_draw_calls;
1042 unsigned num_prim_restart_calls;
1043 unsigned num_spill_draw_calls;
1044 unsigned num_compute_calls;
1045 unsigned num_spill_compute_calls;
1046 unsigned num_dma_calls;
1047 unsigned num_cp_dma_calls;
1048 unsigned num_vs_flushes;
1049 unsigned num_ps_flushes;
1050 unsigned num_cs_flushes;
1051 unsigned num_cb_cache_flushes;
1052 unsigned num_db_cache_flushes;
1053 unsigned num_L2_invalidates;
1054 unsigned num_L2_writebacks;
1055 unsigned num_resident_handles;
1056 uint64_t num_alloc_tex_transfer_bytes;
1057 unsigned last_tex_ps_draw_ratio; /* for query */
1058 unsigned context_roll_counter;
1059
1060 /* Queries. */
1061 /* Maintain the list of active queries for pausing between IBs. */
1062 int num_occlusion_queries;
1063 int num_perfect_occlusion_queries;
1064 struct list_head active_queries;
1065 unsigned num_cs_dw_queries_suspend;
1066
1067 /* Render condition. */
1068 struct pipe_query *render_cond;
1069 unsigned render_cond_mode;
1070 bool render_cond_invert;
1071 bool render_cond_force_off; /* for u_blitter */
1072
1073 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1074 bool sdma_uploads_in_progress;
1075 struct si_sdma_upload *sdma_uploads;
1076 unsigned num_sdma_uploads;
1077 unsigned max_sdma_uploads;
1078
1079 /* Statistics gathering for the DCC enablement heuristic. It can't be
1080 * in si_texture because si_texture can be shared by multiple
1081 * contexts. This is for back buffers only. We shouldn't get too many
1082 * of those.
1083 *
1084 * X11 DRI3 rotates among a finite set of back buffers. They should
1085 * all fit in this array. If they don't, separate DCC might never be
1086 * enabled by DCC stat gathering.
1087 */
1088 struct {
1089 struct si_texture *tex;
1090 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1091 struct pipe_query *ps_stats[3];
1092 /* If all slots are used and another slot is needed,
1093 * the least recently used slot is evicted based on this. */
1094 int64_t last_use_timestamp;
1095 bool query_active;
1096 } dcc_stats[5];
1097
1098 /* Copy one resource to another using async DMA. */
1099 void (*dma_copy)(struct pipe_context *ctx,
1100 struct pipe_resource *dst,
1101 unsigned dst_level,
1102 unsigned dst_x, unsigned dst_y, unsigned dst_z,
1103 struct pipe_resource *src,
1104 unsigned src_level,
1105 const struct pipe_box *src_box);
1106
1107 struct si_tracked_regs tracked_regs;
1108 };
1109
1110 /* cik_sdma.c */
1111 void cik_init_sdma_functions(struct si_context *sctx);
1112
1113 /* si_blit.c */
1114 enum si_blitter_op /* bitmask */
1115 {
1116 SI_SAVE_TEXTURES = 1,
1117 SI_SAVE_FRAMEBUFFER = 2,
1118 SI_SAVE_FRAGMENT_STATE = 4,
1119 SI_DISABLE_RENDER_COND = 8,
1120 };
1121
1122 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1123 void si_blitter_end(struct si_context *sctx);
1124 void si_init_blit_functions(struct si_context *sctx);
1125 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1126 void si_resource_copy_region(struct pipe_context *ctx,
1127 struct pipe_resource *dst,
1128 unsigned dst_level,
1129 unsigned dstx, unsigned dsty, unsigned dstz,
1130 struct pipe_resource *src,
1131 unsigned src_level,
1132 const struct pipe_box *src_box);
1133 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1134 void si_blit_decompress_depth(struct pipe_context *ctx,
1135 struct si_texture *texture,
1136 struct si_texture *staging,
1137 unsigned first_level, unsigned last_level,
1138 unsigned first_layer, unsigned last_layer,
1139 unsigned first_sample, unsigned last_sample);
1140
1141 /* si_buffer.c */
1142 bool si_rings_is_buffer_referenced(struct si_context *sctx,
1143 struct pb_buffer *buf,
1144 enum radeon_bo_usage usage);
1145 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
1146 struct si_resource *resource,
1147 unsigned usage);
1148 void si_init_resource_fields(struct si_screen *sscreen,
1149 struct si_resource *res,
1150 uint64_t size, unsigned alignment);
1151 bool si_alloc_resource(struct si_screen *sscreen,
1152 struct si_resource *res);
1153 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
1154 unsigned flags, unsigned usage,
1155 unsigned size, unsigned alignment);
1156 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen,
1157 unsigned flags, unsigned usage,
1158 unsigned size, unsigned alignment);
1159 void si_replace_buffer_storage(struct pipe_context *ctx,
1160 struct pipe_resource *dst,
1161 struct pipe_resource *src);
1162 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1163 void si_init_buffer_functions(struct si_context *sctx);
1164
1165 /* si_clear.c */
1166 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1167 bool vi_alpha_is_on_msb(enum pipe_format format);
1168 void vi_dcc_clear_level(struct si_context *sctx,
1169 struct si_texture *tex,
1170 unsigned level, unsigned clear_value);
1171 void si_init_clear_functions(struct si_context *sctx);
1172
1173 /* si_compute_blit.c */
1174 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1175 enum si_cache_policy cache_policy);
1176 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1177 uint64_t offset, uint64_t size, uint32_t *clear_value,
1178 uint32_t clear_value_size, enum si_coherency coher);
1179 void si_copy_buffer(struct si_context *sctx,
1180 struct pipe_resource *dst, struct pipe_resource *src,
1181 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1182 void si_compute_copy_image(struct si_context *sctx,
1183 struct pipe_resource *dst,
1184 unsigned dst_level,
1185 struct pipe_resource *src,
1186 unsigned src_level,
1187 unsigned dstx, unsigned dsty, unsigned dstz,
1188 const struct pipe_box *src_box);
1189 void si_compute_clear_render_target(struct pipe_context *ctx,
1190 struct pipe_surface *dstsurf,
1191 const union pipe_color_union *color,
1192 unsigned dstx, unsigned dsty,
1193 unsigned width, unsigned height,
1194 bool render_condition_enabled);
1195 void si_init_compute_blit_functions(struct si_context *sctx);
1196
1197 /* si_cp_dma.c */
1198 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1199 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1200 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1201 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1202 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1203 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1204 SI_CPDMA_SKIP_SYNC_AFTER | \
1205 SI_CPDMA_SKIP_SYNC_BEFORE | \
1206 SI_CPDMA_SKIP_GFX_SYNC | \
1207 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1208
1209 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1210 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1211 struct pipe_resource *dst, uint64_t offset,
1212 uint64_t size, unsigned value, unsigned user_flags,
1213 enum si_coherency coher, enum si_cache_policy cache_policy);
1214 void si_cp_dma_copy_buffer(struct si_context *sctx,
1215 struct pipe_resource *dst, struct pipe_resource *src,
1216 uint64_t dst_offset, uint64_t src_offset, unsigned size,
1217 unsigned user_flags, enum si_coherency coher,
1218 enum si_cache_policy cache_policy);
1219 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
1220 uint64_t offset, unsigned size);
1221 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1222 void si_test_gds(struct si_context *sctx);
1223 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf,
1224 unsigned offset, unsigned size, unsigned dst_sel,
1225 unsigned engine, const void *data);
1226
1227 /* si_debug.c */
1228 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
1229 struct radeon_saved_cs *saved, bool get_buffer_list);
1230 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1231 void si_destroy_saved_cs(struct si_saved_cs *scs);
1232 void si_auto_log_cs(void *data, struct u_log_context *log);
1233 void si_log_hw_flush(struct si_context *sctx);
1234 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1235 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1236 void si_init_debug_functions(struct si_context *sctx);
1237 void si_check_vm_faults(struct si_context *sctx,
1238 struct radeon_saved_cs *saved, enum ring_type ring);
1239 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
1240
1241 /* si_dma.c */
1242 void si_init_dma_functions(struct si_context *sctx);
1243
1244 /* si_dma_cs.c */
1245 void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst,
1246 uint64_t offset);
1247 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1248 uint64_t offset, uint64_t size, unsigned clear_value);
1249 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
1250 struct si_resource *dst, struct si_resource *src);
1251 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
1252 struct pipe_fence_handle **fence);
1253 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
1254 uint64_t offset, uint64_t size, unsigned value);
1255
1256 /* si_fence.c */
1257 void si_cp_release_mem(struct si_context *ctx,
1258 unsigned event, unsigned event_flags,
1259 unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1260 struct si_resource *buf, uint64_t va,
1261 uint32_t new_fence, unsigned query_type);
1262 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1263 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1264 uint64_t va, uint32_t ref, uint32_t mask, unsigned flags);
1265 void si_init_fence_functions(struct si_context *ctx);
1266 void si_init_screen_fence_functions(struct si_screen *screen);
1267 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1268 struct tc_unflushed_batch_token *tc_token);
1269
1270 /* si_get.c */
1271 void si_init_screen_get_functions(struct si_screen *sscreen);
1272
1273 /* si_gfx_cs.c */
1274 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
1275 struct pipe_fence_handle **fence);
1276 void si_begin_new_gfx_cs(struct si_context *ctx);
1277 void si_need_gfx_cs_space(struct si_context *ctx);
1278 void si_unref_sdma_uploads(struct si_context *sctx);
1279
1280 /* si_gpu_load.c */
1281 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1282 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1283 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
1284 uint64_t begin);
1285
1286 /* si_compute.c */
1287 void si_init_compute_functions(struct si_context *sctx);
1288
1289 /* si_perfcounters.c */
1290 void si_init_perfcounters(struct si_screen *screen);
1291 void si_destroy_perfcounters(struct si_screen *screen);
1292
1293 /* si_pipe.c */
1294 bool si_check_device_reset(struct si_context *sctx);
1295
1296 /* si_query.c */
1297 void si_init_screen_query_functions(struct si_screen *sscreen);
1298 void si_init_query_functions(struct si_context *sctx);
1299 void si_suspend_queries(struct si_context *sctx);
1300 void si_resume_queries(struct si_context *sctx);
1301
1302 /* si_shaderlib_tgsi.c */
1303 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1304 unsigned num_layers);
1305 void *si_create_fixed_func_tcs(struct si_context *sctx);
1306 void *si_create_dma_compute_shader(struct pipe_context *ctx,
1307 unsigned num_dwords_per_thread,
1308 bool dst_stream_cache_policy, bool is_copy);
1309 void *si_create_copy_image_compute_shader(struct pipe_context *ctx);
1310 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx);
1311 void *si_clear_render_target_shader(struct pipe_context *ctx);
1312 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
1313 void *si_create_query_result_cs(struct si_context *sctx);
1314
1315 /* si_test_dma.c */
1316 void si_test_dma(struct si_screen *sscreen);
1317
1318 /* si_test_clearbuffer.c */
1319 void si_test_dma_perf(struct si_screen *sscreen);
1320
1321 /* si_uvd.c */
1322 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1323 const struct pipe_video_codec *templ);
1324
1325 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1326 const struct pipe_video_buffer *tmpl);
1327
1328 /* si_viewport.c */
1329 void si_update_vs_viewport_state(struct si_context *ctx);
1330 void si_init_viewport_functions(struct si_context *ctx);
1331
1332 /* si_texture.c */
1333 bool si_prepare_for_dma_blit(struct si_context *sctx,
1334 struct si_texture *dst,
1335 unsigned dst_level, unsigned dstx,
1336 unsigned dsty, unsigned dstz,
1337 struct si_texture *src,
1338 unsigned src_level,
1339 const struct pipe_box *src_box);
1340 void si_eliminate_fast_color_clear(struct si_context *sctx,
1341 struct si_texture *tex);
1342 void si_texture_discard_cmask(struct si_screen *sscreen,
1343 struct si_texture *tex);
1344 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1345 struct pipe_resource *texture,
1346 struct si_texture **staging);
1347 void si_print_texture_info(struct si_screen *sscreen,
1348 struct si_texture *tex, struct u_log_context *log);
1349 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1350 const struct pipe_resource *templ);
1351 bool vi_dcc_formats_compatible(enum pipe_format format1,
1352 enum pipe_format format2);
1353 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1354 unsigned level,
1355 enum pipe_format view_format);
1356 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1357 struct pipe_resource *tex,
1358 unsigned level,
1359 enum pipe_format view_format);
1360 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1361 struct pipe_resource *texture,
1362 const struct pipe_surface *templ,
1363 unsigned width0, unsigned height0,
1364 unsigned width, unsigned height);
1365 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1366 void vi_separate_dcc_try_enable(struct si_context *sctx,
1367 struct si_texture *tex);
1368 void vi_separate_dcc_start_query(struct si_context *sctx,
1369 struct si_texture *tex);
1370 void vi_separate_dcc_stop_query(struct si_context *sctx,
1371 struct si_texture *tex);
1372 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1373 struct si_texture *tex);
1374 bool si_texture_disable_dcc(struct si_context *sctx,
1375 struct si_texture *tex);
1376 void si_init_screen_texture_functions(struct si_screen *sscreen);
1377 void si_init_context_texture_functions(struct si_context *sctx);
1378
1379
1380 /*
1381 * common helpers
1382 */
1383
1384 static inline struct si_resource *si_resource(struct pipe_resource *r)
1385 {
1386 return (struct si_resource*)r;
1387 }
1388
1389 static inline void
1390 si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1391 {
1392 pipe_resource_reference((struct pipe_resource **)ptr,
1393 (struct pipe_resource *)res);
1394 }
1395
1396 static inline void
1397 si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1398 {
1399 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1400 }
1401
1402 static inline bool
1403 vi_dcc_enabled(struct si_texture *tex, unsigned level)
1404 {
1405 return tex->dcc_offset && level < tex->surface.num_dcc_levels;
1406 }
1407
1408 static inline unsigned
1409 si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1410 {
1411 if (stencil)
1412 return tex->surface.u.legacy.stencil_tiling_index[level];
1413 else
1414 return tex->surface.u.legacy.tiling_index[level];
1415 }
1416
1417 static inline void
1418 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1419 {
1420 if (r) {
1421 /* Add memory usage for need_gfx_cs_space */
1422 sctx->vram += si_resource(r)->vram_usage;
1423 sctx->gtt += si_resource(r)->gart_usage;
1424 }
1425 }
1426
1427 static inline void
1428 si_invalidate_draw_sh_constants(struct si_context *sctx)
1429 {
1430 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1431 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1432 }
1433
1434 static inline unsigned
1435 si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1436 {
1437 return 1 << (atom - sctx->atoms.array);
1438 }
1439
1440 static inline void
1441 si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1442 {
1443 unsigned bit = si_get_atom_bit(sctx, atom);
1444
1445 if (dirty)
1446 sctx->dirty_atoms |= bit;
1447 else
1448 sctx->dirty_atoms &= ~bit;
1449 }
1450
1451 static inline bool
1452 si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1453 {
1454 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1455 }
1456
1457 static inline void
1458 si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1459 {
1460 si_set_atom_dirty(sctx, atom, true);
1461 }
1462
1463 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1464 {
1465 if (sctx->gs_shader.cso)
1466 return &sctx->gs_shader;
1467 if (sctx->tes_shader.cso)
1468 return &sctx->tes_shader;
1469
1470 return &sctx->vs_shader;
1471 }
1472
1473 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1474 {
1475 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1476
1477 return vs->cso ? &vs->cso->info : NULL;
1478 }
1479
1480 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1481 {
1482 if (sctx->gs_shader.cso)
1483 return sctx->gs_shader.cso->gs_copy_shader;
1484
1485 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1486 return vs->current ? vs->current : NULL;
1487 }
1488
1489 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1490 unsigned processor)
1491 {
1492 return sscreen->debug_flags & (1 << processor);
1493 }
1494
1495 static inline bool si_get_strmout_en(struct si_context *sctx)
1496 {
1497 return sctx->streamout.streamout_enabled ||
1498 sctx->streamout.prims_gen_query_enabled;
1499 }
1500
1501 static inline unsigned
1502 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1503 {
1504 unsigned alignment, tcc_cache_line_size;
1505
1506 /* If the upload size is less than the cache line size (e.g. 16, 32),
1507 * the whole thing will fit into a cache line if we align it to its size.
1508 * The idea is that multiple small uploads can share a cache line.
1509 * If the upload size is greater, align it to the cache line size.
1510 */
1511 alignment = util_next_power_of_two(upload_size);
1512 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1513 return MIN2(alignment, tcc_cache_line_size);
1514 }
1515
1516 static inline void
1517 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1518 {
1519 if (pipe_reference(&(*dst)->reference, &src->reference))
1520 si_destroy_saved_cs(*dst);
1521
1522 *dst = src;
1523 }
1524
1525 static inline void
1526 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1527 bool shaders_read_metadata)
1528 {
1529 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1530 SI_CONTEXT_INV_VMEM_L1;
1531
1532 if (sctx->chip_class >= GFX9) {
1533 /* Single-sample color is coherent with shaders on GFX9, but
1534 * L2 metadata must be flushed if shaders read metadata.
1535 * (DCC, CMASK).
1536 */
1537 if (num_samples >= 2)
1538 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1539 else if (shaders_read_metadata)
1540 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1541 } else {
1542 /* SI-CI-VI */
1543 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1544 }
1545 }
1546
1547 static inline void
1548 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1549 bool include_stencil, bool shaders_read_metadata)
1550 {
1551 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1552 SI_CONTEXT_INV_VMEM_L1;
1553
1554 if (sctx->chip_class >= GFX9) {
1555 /* Single-sample depth (not stencil) is coherent with shaders
1556 * on GFX9, but L2 metadata must be flushed if shaders read
1557 * metadata.
1558 */
1559 if (num_samples >= 2 || include_stencil)
1560 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1561 else if (shaders_read_metadata)
1562 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1563 } else {
1564 /* SI-CI-VI */
1565 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1566 }
1567 }
1568
1569 static inline bool
1570 si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1571 {
1572 return (stencil_sampler && tex->can_sample_s) ||
1573 (!stencil_sampler && tex->can_sample_z);
1574 }
1575
1576 static inline bool
1577 si_htile_enabled(struct si_texture *tex, unsigned level)
1578 {
1579 return tex->htile_offset && level == 0;
1580 }
1581
1582 static inline bool
1583 vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level)
1584 {
1585 assert(!tex->tc_compatible_htile || tex->htile_offset);
1586 return tex->tc_compatible_htile && level == 0;
1587 }
1588
1589 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1590 {
1591 if (sctx->ps_uses_fbfetch)
1592 return sctx->framebuffer.nr_color_samples;
1593
1594 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1595 }
1596
1597 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1598 {
1599 if (sctx->queued.named.rasterizer->rasterizer_discard)
1600 return 0;
1601
1602 struct si_shader_selector *ps = sctx->ps_shader.cso;
1603 if (!ps)
1604 return 0;
1605
1606 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1607 sctx->queued.named.blend->cb_target_mask;
1608
1609 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1610 colormask &= ps->colors_written_4bit;
1611 else if (!ps->colors_written_4bit)
1612 colormask = 0; /* color0 writes all cbufs, but it's not written */
1613
1614 return colormask;
1615 }
1616
1617 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1618 (1 << PIPE_PRIM_LINE_LOOP) | \
1619 (1 << PIPE_PRIM_LINE_STRIP) | \
1620 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1621 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1622
1623 static inline bool util_prim_is_lines(unsigned prim)
1624 {
1625 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1626 }
1627
1628 static inline bool util_prim_is_points_or_lines(unsigned prim)
1629 {
1630 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES |
1631 (1 << PIPE_PRIM_POINTS))) != 0;
1632 }
1633
1634 /**
1635 * Return true if there is enough memory in VRAM and GTT for the buffers
1636 * added so far.
1637 *
1638 * \param vram VRAM memory size not added to the buffer list yet
1639 * \param gtt GTT memory size not added to the buffer list yet
1640 */
1641 static inline bool
1642 radeon_cs_memory_below_limit(struct si_screen *screen,
1643 struct radeon_cmdbuf *cs,
1644 uint64_t vram, uint64_t gtt)
1645 {
1646 vram += cs->used_vram;
1647 gtt += cs->used_gart;
1648
1649 /* Anything that goes above the VRAM size should go to GTT. */
1650 if (vram > screen->info.vram_size)
1651 gtt += vram - screen->info.vram_size;
1652
1653 /* Now we just need to check if we have enough GTT. */
1654 return gtt < screen->info.gart_size * 0.7;
1655 }
1656
1657 /**
1658 * Add a buffer to the buffer list for the given command stream (CS).
1659 *
1660 * All buffers used by a CS must be added to the list. This tells the kernel
1661 * driver which buffers are used by GPU commands. Other buffers can
1662 * be swapped out (not accessible) during execution.
1663 *
1664 * The buffer list becomes empty after every context flush and must be
1665 * rebuilt.
1666 */
1667 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1668 struct radeon_cmdbuf *cs,
1669 struct si_resource *bo,
1670 enum radeon_bo_usage usage,
1671 enum radeon_bo_priority priority)
1672 {
1673 assert(usage);
1674 sctx->ws->cs_add_buffer(
1675 cs, bo->buf,
1676 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1677 bo->domains, priority);
1678 }
1679
1680 /**
1681 * Same as above, but also checks memory usage and flushes the context
1682 * accordingly.
1683 *
1684 * When this SHOULD NOT be used:
1685 *
1686 * - if si_context_add_resource_size has been called for the buffer
1687 * followed by *_need_cs_space for checking the memory usage
1688 *
1689 * - if si_need_dma_space has been called for the buffer
1690 *
1691 * - when emitting state packets and draw packets (because preceding packets
1692 * can't be re-emitted at that point)
1693 *
1694 * - if shader resource "enabled_mask" is not up-to-date or there is
1695 * a different constraint disallowing a context flush
1696 */
1697 static inline void
1698 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1699 struct si_resource *bo,
1700 enum radeon_bo_usage usage,
1701 enum radeon_bo_priority priority,
1702 bool check_mem)
1703 {
1704 if (check_mem &&
1705 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1706 sctx->vram + bo->vram_usage,
1707 sctx->gtt + bo->gart_usage))
1708 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1709
1710 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority);
1711 }
1712
1713 #define PRINT_ERR(fmt, args...) \
1714 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1715
1716 #endif