src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef SI_PIPE_H
  27 #define SI_PIPE_H
  28
  29 #include "si_shader.h"
  30
  31 #include "util/u_dynarray.h"
  32
  33 #ifdef PIPE_ARCH_BIG_ENDIAN
  34 #define SI_BIG_ENDIAN 1
  35 #else
  36 #define SI_BIG_ENDIAN 0
  37 #endif
  38
  39 /* The base vertex and primitive restart can be any number, but we must pick
  40  * one which will mean "unknown" for the purpose of state tracking and
  41  * the number shouldn't be a commonly-used one. */
  42 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  43 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  44 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  45 #define SI_GS_PER_ES 128
  46 /* Alignment for optimal CP DMA performance. */
  47 #define SI_CPDMA_ALIGNMENT      32
  48
  49 /* Instruction cache. */
  50 #define SI_CONTEXT_INV_ICACHE           (R600_CONTEXT_PRIVATE_FLAG << 0)
  51 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  52 #define SI_CONTEXT_INV_SMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 1)
  53 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  54 #define SI_CONTEXT_INV_VMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 2)
  55 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  56 #define SI_CONTEXT_INV_GLOBAL_L2        (R600_CONTEXT_PRIVATE_FLAG << 3)
  57 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  58  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
  59 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2  (R600_CONTEXT_PRIVATE_FLAG << 4)
  60 /* gaps */
  61 /* Framebuffer caches. */
  62 #define SI_CONTEXT_FLUSH_AND_INV_DB     (R600_CONTEXT_PRIVATE_FLAG << 7)
  63 #define SI_CONTEXT_FLUSH_AND_INV_CB     (R600_CONTEXT_PRIVATE_FLAG << 8)
  64 /* Engine synchronization. */
  65 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 9)
  66 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 10)
  67 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 11)
  68 #define SI_CONTEXT_VGT_FLUSH            (R600_CONTEXT_PRIVATE_FLAG << 12)
  69 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (R600_CONTEXT_PRIVATE_FLAG << 13)
  70
  71 #define SI_PREFETCH_VBO_DESCRIPTORS     (1 << 0)
  72 #define SI_PREFETCH_LS                  (1 << 1)
  73 #define SI_PREFETCH_HS                  (1 << 2)
  74 #define SI_PREFETCH_ES                  (1 << 3)
  75 #define SI_PREFETCH_GS                  (1 << 4)
  76 #define SI_PREFETCH_VS                  (1 << 5)
  77 #define SI_PREFETCH_PS                  (1 << 6)
  78
  79 #define SI_MAX_BORDER_COLORS    4096
  80 #define SIX_BITS                0x3F
  81
  82 struct si_compute;
  83 struct hash_table;
  84 struct u_suballocator;
  85
  86 struct si_screen {
  87         struct r600_common_screen       b;
  88         unsigned                        gs_table_depth;
  89         unsigned                        tess_offchip_block_dw_size;
  90         bool                            has_distributed_tess;
  91         bool                            has_draw_indirect_multi;
  92         bool                            has_ds_bpermute;
  93         bool                            has_msaa_sample_loc_bug;
  94         bool                            llvm_has_working_vgpr_indexing;
  95
  96         /* Whether shaders are monolithic (1-part) or separate (3-part). */
  97         bool                            use_monolithic_shaders;
  98         bool                            record_llvm_ir;
  99
 100         mtx_t                   shader_parts_mutex;
 101         struct si_shader_part           *vs_prologs;
 102         struct si_shader_part           *tcs_epilogs;
 103         struct si_shader_part           *gs_prologs;
 104         struct si_shader_part           *ps_prologs;
 105         struct si_shader_part           *ps_epilogs;
 106
 107         /* Shader cache in memory.
 108          *
 109          * Design & limitations:
 110          * - The shader cache is per screen (= per process), never saved to
 111          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 112          * - It can only be used with one-variant-per-shader support, in which
 113          *   case only the main (typically middle) part of shaders is cached.
 114          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 115          *   variants of VS and TES are cached, so LS and ES aren't.
 116          * - GS and CS aren't cached, but it's certainly possible to cache
 117          *   those as well.
 118          */
 119         mtx_t                   shader_cache_mutex;
 120         struct hash_table               *shader_cache;
 121
 122         /* Shader compiler queue for multithreaded compilation. */
 123         struct util_queue               shader_compiler_queue;
 124         /* Use at most 3 normal compiler threads on quadcore and better.
 125          * Hyperthreaded CPUs report the number of threads, but we want
 126          * the number of cores. */
 127         LLVMTargetMachineRef            tm[3]; /* used by the queue only */
 128
 129         struct util_queue               shader_compiler_queue_low_priority;
 130         /* Use at most 2 low priority threads on quadcore and better.
 131          * We want to minimize the impact on multithreaded Mesa. */
 132         LLVMTargetMachineRef            tm_low_priority[2]; /* at most 2 threads */
 133 };
 134
 135 struct si_blend_color {
 136         struct r600_atom                atom;
 137         struct pipe_blend_color         state;
 138         bool                            any_nonzeros;
 139 };
 140
 141 struct si_sampler_view {
 142         struct pipe_sampler_view        base;
 143         /* [0..7] = image descriptor
 144          * [4..7] = buffer descriptor */
 145         uint32_t                        state[8];
 146         uint32_t                        fmask_state[8];
 147         const struct legacy_surf_level  *base_level_info;
 148         ubyte                           base_level;
 149         ubyte                           block_width;
 150         bool is_stencil_sampler;
 151         bool dcc_incompatible;
 152 };
 153
 154 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
 155
 156 struct si_sampler_state {
 157 #ifdef DEBUG
 158         unsigned                        magic;
 159 #endif
 160         uint32_t                        val[4];
 161 };
 162
 163 struct si_cs_shader_state {
 164         struct si_compute               *program;
 165         struct si_compute               *emitted_program;
 166         unsigned                        offset;
 167         bool                            initialized;
 168         bool                            uses_scratch;
 169 };
 170
 171 struct si_textures_info {
 172         struct si_sampler_views         views;
 173         uint32_t                        needs_depth_decompress_mask;
 174         uint32_t                        needs_color_decompress_mask;
 175 };
 176
 177 struct si_images_info {
 178         struct pipe_image_view          views[SI_NUM_IMAGES];
 179         uint32_t                        needs_color_decompress_mask;
 180         unsigned                        enabled_mask;
 181 };
 182
 183 struct si_framebuffer {
 184         struct r600_atom                atom;
 185         struct pipe_framebuffer_state   state;
 186         unsigned                        colorbuf_enabled_4bit;
 187         unsigned                        spi_shader_col_format;
 188         unsigned                        spi_shader_col_format_alpha;
 189         unsigned                        spi_shader_col_format_blend;
 190         unsigned                        spi_shader_col_format_blend_alpha;
 191         ubyte                           nr_samples:5; /* at most 16xAA */
 192         ubyte                           log_samples:3; /* at most 4 = 16xAA */
 193         ubyte                           compressed_cb_mask;
 194         ubyte                           color_is_int8;
 195         ubyte                           color_is_int10;
 196         ubyte                           dirty_cbufs;
 197         bool                            dirty_zsbuf;
 198         bool                            any_dst_linear;
 199 };
 200
 201 struct si_clip_state {
 202         struct r600_atom                atom;
 203         struct pipe_clip_state          state;
 204         bool                            any_nonzeros;
 205 };
 206
 207 struct si_sample_locs {
 208         struct r600_atom        atom;
 209         unsigned                nr_samples;
 210 };
 211
 212 struct si_sample_mask {
 213         struct r600_atom        atom;
 214         uint16_t                sample_mask;
 215 };
 216
 217 /* A shader state consists of the shader selector, which is a constant state
 218  * object shared by multiple contexts and shouldn't be modified, and
 219  * the current shader variant selected for this context.
 220  */
 221 struct si_shader_ctx_state {
 222         struct si_shader_selector       *cso;
 223         struct si_shader                *current;
 224 };
 225
 226 #define SI_NUM_VGT_PARAM_KEY_BITS 12
 227 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
 228
 229 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
 230  * Some fields are set by state-change calls, most are set by draw_vbo.
 231  */
 232 union si_vgt_param_key {
 233         struct {
 234                 unsigned prim:4;
 235                 unsigned uses_instancing:1;
 236                 unsigned multi_instances_smaller_than_primgroup:1;
 237                 unsigned primitive_restart:1;
 238                 unsigned count_from_stream_output:1;
 239                 unsigned line_stipple_enabled:1;
 240                 unsigned uses_tess:1;
 241                 unsigned tess_uses_prim_id:1;
 242                 unsigned uses_gs:1;
 243                 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
 244         } u;
 245         uint32_t index;
 246 };
 247
 248 struct si_bindless_descriptor
 249 {
 250         struct pb_slab_entry            entry;
 251         struct r600_resource            *buffer;
 252         unsigned                        offset;
 253         uint32_t                        desc_list[16];
 254         bool                            dirty;
 255 };
 256
 257 struct si_texture_handle
 258 {
 259         struct si_bindless_descriptor   *desc;
 260         struct pipe_sampler_view        *view;
 261         struct si_sampler_state         sstate;
 262 };
 263
 264 struct si_image_handle
 265 {
 266         struct si_bindless_descriptor   *desc;
 267         struct pipe_image_view          view;
 268 };
 269
 270 struct si_context {
 271         struct r600_common_context      b;
 272         struct blitter_context          *blitter;
 273         void                            *custom_dsa_flush;
 274         void                            *custom_blend_resolve;
 275         void                            *custom_blend_fmask_decompress;
 276         void                            *custom_blend_eliminate_fastclear;
 277         void                            *custom_blend_dcc_decompress;
 278         struct si_screen                *screen;
 279         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 280         struct si_shader_ctx_state      fixed_func_tcs_shader;
 281         struct r600_resource            *wait_mem_scratch;
 282         unsigned                        wait_mem_number;
 283
 284         struct radeon_winsys_cs         *ce_ib;
 285         struct radeon_winsys_cs         *ce_preamble_ib;
 286         struct r600_resource            *ce_ram_saved_buffer;
 287         struct u_suballocator           *ce_suballocator;
 288         unsigned                        ce_ram_saved_offset;
 289         uint16_t                        total_ce_ram_allocated;
 290         uint16_t                        prefetch_L2_mask;
 291         bool                            ce_need_synchronization:1;
 292
 293         bool                            gfx_flush_in_progress:1;
 294         bool                            compute_is_busy:1;
 295
 296         /* Atoms (direct states). */
 297         union si_state_atoms            atoms;
 298         unsigned                        dirty_atoms; /* mask */
 299         /* PM4 states (precomputed immutable states) */
 300         unsigned                        dirty_states;
 301         union si_state                  queued;
 302         union si_state                  emitted;
 303
 304         /* Atom declarations. */
 305         struct si_framebuffer           framebuffer;
 306         struct si_sample_locs           msaa_sample_locs;
 307         struct r600_atom                db_render_state;
 308         struct r600_atom                msaa_config;
 309         struct si_sample_mask           sample_mask;
 310         struct r600_atom                cb_render_state;
 311         unsigned                        last_cb_target_mask;
 312         struct si_blend_color           blend_color;
 313         struct r600_atom                clip_regs;
 314         struct si_clip_state            clip_state;
 315         struct si_shader_data           shader_pointers;
 316         struct si_stencil_ref           stencil_ref;
 317         struct r600_atom                spi_map;
 318
 319         /* Precomputed states. */
 320         struct si_pm4_state             *init_config;
 321         struct si_pm4_state             *init_config_gs_rings;
 322         bool                            init_config_has_vgt_flush;
 323         struct si_pm4_state             *vgt_shader_config[4];
 324
 325         /* shaders */
 326         struct si_shader_ctx_state      ps_shader;
 327         struct si_shader_ctx_state      gs_shader;
 328         struct si_shader_ctx_state      vs_shader;
 329         struct si_shader_ctx_state      tcs_shader;
 330         struct si_shader_ctx_state      tes_shader;
 331         struct si_cs_shader_state       cs_shader_state;
 332
 333         /* shader information */
 334         struct si_vertex_elements       *vertex_elements;
 335         unsigned                        sprite_coord_enable;
 336         bool                            flatshade;
 337         bool                            do_update_shaders;
 338
 339         /* shader descriptors */
 340         struct si_descriptors           vertex_buffers;
 341         struct si_descriptors           descriptors[SI_NUM_DESCS];
 342         unsigned                        descriptors_dirty;
 343         unsigned                        shader_pointers_dirty;
 344         unsigned                        shader_needs_decompress_mask;
 345         struct si_buffer_resources      rw_buffers;
 346         struct si_buffer_resources      const_and_shader_buffers[SI_NUM_SHADERS];
 347         struct si_textures_info         samplers[SI_NUM_SHADERS];
 348         struct si_images_info           images[SI_NUM_SHADERS];
 349
 350         /* other shader resources */
 351         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 352         struct pipe_resource            *esgs_ring;
 353         struct pipe_resource            *gsvs_ring;
 354         struct pipe_resource            *tf_ring;
 355         struct pipe_resource            *tess_offchip_ring;
 356         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 357         struct r600_resource            *border_color_buffer;
 358         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 359         unsigned                        border_color_count;
 360
 361         /* Vertex and index buffers. */
 362         bool                            vertex_buffers_dirty;
 363         bool                            vertex_buffer_pointer_dirty;
 364         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 365
 366         /* MSAA config state. */
 367         int                             ps_iter_samples;
 368         bool                            smoothing_enabled;
 369
 370         /* DB render state. */
 371         unsigned                ps_db_shader_control;
 372         unsigned                dbcb_copy_sample;
 373         bool                    dbcb_depth_copy_enabled:1;
 374         bool                    dbcb_stencil_copy_enabled:1;
 375         bool                    db_flush_depth_inplace:1;
 376         bool                    db_flush_stencil_inplace:1;
 377         bool                    db_depth_clear:1;
 378         bool                    db_depth_disable_expclear:1;
 379         bool                    db_stencil_clear:1;
 380         bool                    db_stencil_disable_expclear:1;
 381         bool                    occlusion_queries_disabled:1;
 382         bool                    generate_mipmap_for_depth:1;
 383
 384         /* Emitted draw state. */
 385         bool                    gs_tri_strip_adj_fix:1;
 386         int                     last_index_size;
 387         int                     last_base_vertex;
 388         int                     last_start_instance;
 389         int                     last_drawid;
 390         int                     last_sh_base_reg;
 391         int                     last_primitive_restart_en;
 392         int                     last_restart_index;
 393         int                     last_gs_out_prim;
 394         int                     last_prim;
 395         int                     last_multi_vgt_param;
 396         int                     last_rast_prim;
 397         unsigned                last_sc_line_stipple;
 398         unsigned                current_vs_state;
 399         unsigned                last_vs_state;
 400         enum pipe_prim_type     current_rast_prim; /* primitive type after TES, GS */
 401
 402         /* Scratch buffer */
 403         struct r600_atom        scratch_state;
 404         struct r600_resource    *scratch_buffer;
 405         unsigned                scratch_waves;
 406         unsigned                spi_tmpring_size;
 407
 408         struct r600_resource    *compute_scratch_buffer;
 409
 410         /* Emitted derived tessellation state. */
 411         /* Local shader (VS), or HS if LS-HS are merged. */
 412         struct si_shader        *last_ls;
 413         struct si_shader_selector *last_tcs;
 414         int                     last_num_tcs_input_cp;
 415         int                     last_tes_sh_base;
 416         bool                    last_tess_uses_primid;
 417         unsigned                last_num_patches;
 418
 419         /* Debug state. */
 420         bool                    is_debug;
 421         struct radeon_saved_cs  last_gfx;
 422         struct radeon_saved_cs  last_ce;
 423         struct r600_resource    *last_trace_buf;
 424         struct r600_resource    *trace_buf;
 425         unsigned                trace_id;
 426         uint64_t                dmesg_timestamp;
 427         unsigned                apitrace_call_number;
 428
 429         /* Other state */
 430         bool need_check_render_feedback;
 431         bool                    decompression_enabled;
 432
 433         /* Precomputed IA_MULTI_VGT_PARAM */
 434         union si_vgt_param_key  ia_multi_vgt_param_key;
 435         unsigned                ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
 436
 437         /* Slab allocator for bindless descriptors. */
 438         struct pb_slabs         bindless_descriptor_slabs;
 439
 440         /* Bindless descriptors. */
 441         struct util_dynarray    bindless_descriptors;
 442         bool                    bindless_descriptors_dirty;
 443
 444         /* Allocated bindless handles */
 445         struct hash_table       *tex_handles;
 446         struct hash_table       *img_handles;
 447
 448         /* Resident bindless handles */
 449         struct util_dynarray    resident_tex_handles;
 450         struct util_dynarray    resident_img_handles;
 451
 452         /* Resident bindless handles which need decompression */
 453         struct util_dynarray    resident_tex_needs_color_decompress;
 454         struct util_dynarray    resident_img_needs_color_decompress;
 455         struct util_dynarray    resident_tex_needs_depth_decompress;
 456
 457         /* Bindless state */
 458         bool                    uses_bindless_samplers;
 459         bool                    uses_bindless_images;
 460 };
 461
 462 /* cik_sdma.c */
 463 void cik_init_sdma_functions(struct si_context *sctx);
 464
 465 /* si_blit.c */
 466 void si_init_blit_functions(struct si_context *sctx);
 467 void si_decompress_graphics_textures(struct si_context *sctx);
 468 void si_decompress_compute_textures(struct si_context *sctx);
 469 void si_resource_copy_region(struct pipe_context *ctx,
 470                              struct pipe_resource *dst,
 471                              unsigned dst_level,
 472                              unsigned dstx, unsigned dsty, unsigned dstz,
 473                              struct pipe_resource *src,
 474                              unsigned src_level,
 475                              const struct pipe_box *src_box);
 476
 477 /* si_cp_dma.c */
 478 #define SI_CPDMA_SKIP_CHECK_CS_SPACE    (1 << 0) /* don't call need_cs_space */
 479 #define SI_CPDMA_SKIP_SYNC_AFTER        (1 << 1) /* don't wait for DMA after the copy */
 480 #define SI_CPDMA_SKIP_SYNC_BEFORE       (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
 481 #define SI_CPDMA_SKIP_GFX_SYNC          (1 << 3) /* don't flush caches and don't wait for PS/CS */
 482 #define SI_CPDMA_SKIP_BO_LIST_UPDATE    (1 << 4) /* don't update the BO list */
 483 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
 484                            SI_CPDMA_SKIP_SYNC_AFTER | \
 485                            SI_CPDMA_SKIP_SYNC_BEFORE | \
 486                            SI_CPDMA_SKIP_GFX_SYNC | \
 487                            SI_CPDMA_SKIP_BO_LIST_UPDATE)
 488
 489 void si_copy_buffer(struct si_context *sctx,
 490                     struct pipe_resource *dst, struct pipe_resource *src,
 491                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 492                     unsigned user_flags);
 493 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 494                               uint64_t offset, unsigned size);
 495 void cik_emit_prefetch_L2(struct si_context *sctx);
 496 void si_init_cp_dma_functions(struct si_context *sctx);
 497
 498 /* si_debug.c */
 499 void si_init_debug_functions(struct si_context *sctx);
 500 void si_check_vm_faults(struct r600_common_context *ctx,
 501                         struct radeon_saved_cs *saved, enum ring_type ring);
 502 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
 503
 504 /* si_dma.c */
 505 void si_init_dma_functions(struct si_context *sctx);
 506
 507 /* si_hw_context.c */
 508 void si_context_gfx_flush(void *context, unsigned flags,
 509                           struct pipe_fence_handle **fence);
 510 void si_begin_new_cs(struct si_context *ctx);
 511 void si_need_cs_space(struct si_context *ctx);
 512
 513 /* si_compute.c */
 514 void si_init_compute_functions(struct si_context *sctx);
 515
 516 /* si_perfcounters.c */
 517 void si_init_perfcounters(struct si_screen *screen);
 518
 519 /* si_uvd.c */
 520 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 521                                                const struct pipe_video_codec *templ);
 522
 523 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 524                                                  const struct pipe_video_buffer *tmpl);
 525
 526 /*
 527  * common helpers
 528  */
 529
 530 static inline void
 531 si_invalidate_draw_sh_constants(struct si_context *sctx)
 532 {
 533         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 534 }
 535
 536 static inline void
 537 si_set_atom_dirty(struct si_context *sctx,
 538                   struct r600_atom *atom, bool dirty)
 539 {
 540         unsigned bit = 1 << atom->id;
 541
 542         if (dirty)
 543                 sctx->dirty_atoms |= bit;
 544         else
 545                 sctx->dirty_atoms &= ~bit;
 546 }
 547
 548 static inline bool
 549 si_is_atom_dirty(struct si_context *sctx,
 550                   struct r600_atom *atom)
 551 {
 552         unsigned bit = 1 << atom->id;
 553
 554         return sctx->dirty_atoms & bit;
 555 }
 556
 557 static inline void
 558 si_mark_atom_dirty(struct si_context *sctx,
 559                    struct r600_atom *atom)
 560 {
 561         si_set_atom_dirty(sctx, atom, true);
 562 }
 563
 564 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
 565 {
 566         if (sctx->gs_shader.cso)
 567                 return &sctx->gs_shader;
 568         if (sctx->tes_shader.cso)
 569                 return &sctx->tes_shader;
 570
 571         return &sctx->vs_shader;
 572 }
 573
 574 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 575 {
 576         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 577
 578         return vs->cso ? &vs->cso->info : NULL;
 579 }
 580
 581 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 582 {
 583         if (sctx->gs_shader.cso)
 584                 return sctx->gs_shader.cso->gs_copy_shader;
 585
 586         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 587         return vs->current ? vs->current : NULL;
 588 }
 589
 590 static inline unsigned
 591 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
 592 {
 593         unsigned alignment, tcc_cache_line_size;
 594
 595         /* If the upload size is less than the cache line size (e.g. 16, 32),
 596          * the whole thing will fit into a cache line if we align it to its size.
 597          * The idea is that multiple small uploads can share a cache line.
 598          * If the upload size is greater, align it to the cache line size.
 599          */
 600         alignment = util_next_power_of_two(upload_size);
 601         tcc_cache_line_size = sctx->screen->b.info.tcc_cache_line_size;
 602         return MIN2(alignment, tcc_cache_line_size);
 603 }
 604
 605 #endif