2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "si_shader.h"
31 #ifdef PIPE_ARCH_BIG_ENDIAN
32 #define SI_BIG_ENDIAN 1
34 #define SI_BIG_ENDIAN 0
37 /* The base vertex and primitive restart can be any number, but we must pick
38 * one which will mean "unknown" for the purpose of state tracking and
39 * the number shouldn't be a commonly-used one. */
40 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
41 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
42 #define SI_NUM_SMOOTH_AA_SAMPLES 8
43 #define SI_GS_PER_ES 128
44 /* Alignment for optimal CP DMA performance. */
45 #define SI_CPDMA_ALIGNMENT 32
47 /* Instruction cache. */
48 #define SI_CONTEXT_INV_ICACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
49 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
50 #define SI_CONTEXT_INV_SMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 1)
51 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
52 #define SI_CONTEXT_INV_VMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 2)
53 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
54 #define SI_CONTEXT_INV_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 3)
55 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
56 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
57 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 4)
59 /* Framebuffer caches. */
60 #define SI_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 7)
61 #define SI_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 8)
62 /* Engine synchronization. */
63 #define SI_CONTEXT_VS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 9)
64 #define SI_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 10)
65 #define SI_CONTEXT_CS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 11)
66 #define SI_CONTEXT_VGT_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 12)
67 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (R600_CONTEXT_PRIVATE_FLAG << 13)
69 #define SI_MAX_BORDER_COLORS 4096
74 struct u_suballocator
;
77 struct r600_common_screen b
;
78 unsigned gs_table_depth
;
79 unsigned tess_offchip_block_dw_size
;
80 bool has_distributed_tess
;
81 bool has_draw_indirect_multi
;
83 bool has_msaa_sample_loc_bug
;
85 /* Whether shaders are monolithic (1-part) or separate (3-part). */
86 bool use_monolithic_shaders
;
89 mtx_t shader_parts_mutex
;
90 struct si_shader_part
*vs_prologs
;
91 struct si_shader_part
*tcs_epilogs
;
92 struct si_shader_part
*gs_prologs
;
93 struct si_shader_part
*ps_prologs
;
94 struct si_shader_part
*ps_epilogs
;
96 /* Shader cache in memory.
98 * Design & limitations:
99 * - The shader cache is per screen (= per process), never saved to
100 * disk, and skips redundant shader compilations from TGSI to bytecode.
101 * - It can only be used with one-variant-per-shader support, in which
102 * case only the main (typically middle) part of shaders is cached.
103 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
104 * variants of VS and TES are cached, so LS and ES aren't.
105 * - GS and CS aren't cached, but it's certainly possible to cache
108 mtx_t shader_cache_mutex
;
109 struct hash_table
*shader_cache
;
111 /* Shader compiler queue for multithreaded compilation. */
112 struct util_queue shader_compiler_queue
;
113 LLVMTargetMachineRef tm
[4]; /* used by the queue only */
115 struct util_queue shader_compiler_queue_low_priority
;
116 LLVMTargetMachineRef tm_low_priority
[4];
119 struct si_blend_color
{
120 struct r600_atom atom
;
121 struct pipe_blend_color state
;
124 struct si_sampler_view
{
125 struct pipe_sampler_view base
;
126 /* [0..7] = image descriptor
127 * [4..7] = buffer descriptor */
129 uint32_t fmask_state
[8];
130 const struct legacy_surf_level
*base_level_info
;
132 unsigned block_width
;
133 bool is_stencil_sampler
;
134 bool dcc_incompatible
;
137 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
139 struct si_sampler_state
{
146 struct si_cs_shader_state
{
147 struct si_compute
*program
;
148 struct si_compute
*emitted_program
;
154 struct si_textures_info
{
155 struct si_sampler_views views
;
156 uint32_t needs_depth_decompress_mask
;
157 uint32_t needs_color_decompress_mask
;
160 struct si_images_info
{
161 struct pipe_image_view views
[SI_NUM_IMAGES
];
162 uint32_t needs_color_decompress_mask
;
163 unsigned enabled_mask
;
166 struct si_framebuffer
{
167 struct r600_atom atom
;
168 struct pipe_framebuffer_state state
;
170 unsigned log_samples
;
171 unsigned compressed_cb_mask
;
172 unsigned colorbuf_enabled_4bit
;
173 unsigned spi_shader_col_format
;
174 unsigned spi_shader_col_format_alpha
;
175 unsigned spi_shader_col_format_blend
;
176 unsigned spi_shader_col_format_blend_alpha
;
177 unsigned color_is_int8
;
178 unsigned color_is_int10
;
179 unsigned dirty_cbufs
;
182 bool do_update_surf_dirtiness
;
185 struct si_clip_state
{
186 struct r600_atom atom
;
187 struct pipe_clip_state state
;
190 struct si_sample_locs
{
191 struct r600_atom atom
;
195 struct si_sample_mask
{
196 struct r600_atom atom
;
197 uint16_t sample_mask
;
200 /* A shader state consists of the shader selector, which is a constant state
201 * object shared by multiple contexts and shouldn't be modified, and
202 * the current shader variant selected for this context.
204 struct si_shader_ctx_state
{
205 struct si_shader_selector
*cso
;
206 struct si_shader
*current
;
209 #define SI_NUM_VGT_PARAM_KEY_BITS 12
210 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
212 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
213 * Some fields are set by state-change calls, most are set by draw_vbo.
215 union si_vgt_param_key
{
218 unsigned uses_instancing
:1;
219 unsigned multi_instances_smaller_than_primgroup
:1;
220 unsigned primitive_restart
:1;
221 unsigned count_from_stream_output
:1;
222 unsigned line_stipple_enabled
:1;
223 unsigned uses_tess
:1;
224 unsigned tess_uses_prim_id
:1;
226 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
232 struct r600_common_context b
;
233 struct blitter_context
*blitter
;
234 void *custom_dsa_flush
;
235 void *custom_blend_resolve
;
236 void *custom_blend_fmask_decompress
;
237 void *custom_blend_eliminate_fastclear
;
238 void *custom_blend_dcc_decompress
;
239 struct si_screen
*screen
;
241 struct radeon_winsys_cs
*ce_ib
;
242 struct radeon_winsys_cs
*ce_preamble_ib
;
243 struct r600_resource
*ce_ram_saved_buffer
;
244 unsigned ce_ram_saved_offset
;
245 unsigned total_ce_ram_allocated
;
246 bool ce_need_synchronization
;
247 struct u_suballocator
*ce_suballocator
;
249 struct si_shader_ctx_state fixed_func_tcs_shader
;
250 LLVMTargetMachineRef tm
; /* only non-threaded compilation */
251 bool gfx_flush_in_progress
;
252 bool compute_is_busy
;
254 /* Atoms (direct states). */
255 union si_state_atoms atoms
;
256 unsigned dirty_atoms
; /* mask */
257 /* PM4 states (precomputed immutable states) */
258 unsigned dirty_states
;
259 union si_state queued
;
260 union si_state emitted
;
262 /* Atom declarations. */
263 struct r600_atom prefetch_L2
;
264 struct si_framebuffer framebuffer
;
265 struct si_sample_locs msaa_sample_locs
;
266 struct r600_atom db_render_state
;
267 struct r600_atom msaa_config
;
268 struct si_sample_mask sample_mask
;
269 struct r600_atom cb_render_state
;
270 unsigned last_cb_target_mask
;
271 struct si_blend_color blend_color
;
272 struct r600_atom clip_regs
;
273 struct si_clip_state clip_state
;
274 struct si_shader_data shader_userdata
;
275 struct si_stencil_ref stencil_ref
;
276 struct r600_atom spi_map
;
278 /* Precomputed states. */
279 struct si_pm4_state
*init_config
;
280 struct si_pm4_state
*init_config_gs_rings
;
281 bool init_config_has_vgt_flush
;
282 struct si_pm4_state
*vgt_shader_config
[4];
285 struct si_shader_ctx_state ps_shader
;
286 struct si_shader_ctx_state gs_shader
;
287 struct si_shader_ctx_state vs_shader
;
288 struct si_shader_ctx_state tcs_shader
;
289 struct si_shader_ctx_state tes_shader
;
290 struct si_cs_shader_state cs_shader_state
;
292 /* shader information */
293 struct si_vertex_element
*vertex_elements
;
294 unsigned sprite_coord_enable
;
296 bool do_update_shaders
;
298 /* shader descriptors */
299 struct si_descriptors vertex_buffers
;
300 struct si_descriptors descriptors
[SI_NUM_DESCS
];
301 unsigned descriptors_dirty
;
302 unsigned shader_pointers_dirty
;
303 unsigned shader_needs_decompress_mask
;
304 struct si_buffer_resources rw_buffers
;
305 struct si_buffer_resources const_and_shader_buffers
[SI_NUM_SHADERS
];
306 struct si_textures_info samplers
[SI_NUM_SHADERS
];
307 struct si_images_info images
[SI_NUM_SHADERS
];
309 /* other shader resources */
310 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on CIK */
311 struct pipe_resource
*esgs_ring
;
312 struct pipe_resource
*gsvs_ring
;
313 struct pipe_resource
*tf_ring
;
314 struct pipe_resource
*tess_offchip_ring
;
315 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
316 struct r600_resource
*border_color_buffer
;
317 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
318 unsigned border_color_count
;
320 /* Vertex and index buffers. */
321 bool vertex_buffers_dirty
;
322 bool vertex_buffer_pointer_dirty
;
323 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
325 /* MSAA config state. */
327 bool smoothing_enabled
;
329 /* DB render state. */
330 bool dbcb_depth_copy_enabled
;
331 bool dbcb_stencil_copy_enabled
;
332 unsigned dbcb_copy_sample
;
333 bool db_flush_depth_inplace
;
334 bool db_flush_stencil_inplace
;
336 bool db_depth_disable_expclear
;
337 bool db_stencil_clear
;
338 bool db_stencil_disable_expclear
;
339 unsigned ps_db_shader_control
;
340 bool occlusion_queries_disabled
;
342 /* Emitted draw state. */
344 int last_base_vertex
;
345 int last_start_instance
;
347 int last_sh_base_reg
;
348 int last_primitive_restart_en
;
349 int last_restart_index
;
350 int last_gs_out_prim
;
352 int last_multi_vgt_param
;
354 unsigned last_sc_line_stipple
;
355 unsigned current_vs_state
;
356 unsigned last_vs_state
;
357 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
358 bool gs_tri_strip_adj_fix
;
361 struct r600_atom scratch_state
;
362 struct r600_resource
*scratch_buffer
;
363 unsigned scratch_waves
;
364 unsigned spi_tmpring_size
;
366 struct r600_resource
*compute_scratch_buffer
;
368 /* Emitted derived tessellation state. */
369 /* Local shader (VS), or HS if LS-HS are merged. */
370 struct si_shader
*last_ls
;
371 struct si_shader_selector
*last_tcs
;
372 int last_num_tcs_input_cp
;
373 int last_tes_sh_base
;
374 bool last_tess_uses_primid
;
375 unsigned last_num_patches
;
379 struct radeon_saved_cs last_gfx
;
380 struct r600_resource
*last_trace_buf
;
381 struct r600_resource
*trace_buf
;
383 uint64_t dmesg_timestamp
;
384 unsigned apitrace_call_number
;
387 bool need_check_render_feedback
;
388 bool decompression_enabled
;
390 /* Precomputed IA_MULTI_VGT_PARAM */
391 union si_vgt_param_key ia_multi_vgt_param_key
;
392 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
396 void cik_init_sdma_functions(struct si_context
*sctx
);
399 void si_init_blit_functions(struct si_context
*sctx
);
400 void si_decompress_graphics_textures(struct si_context
*sctx
);
401 void si_decompress_compute_textures(struct si_context
*sctx
);
402 void si_resource_copy_region(struct pipe_context
*ctx
,
403 struct pipe_resource
*dst
,
405 unsigned dstx
, unsigned dsty
, unsigned dstz
,
406 struct pipe_resource
*src
,
408 const struct pipe_box
*src_box
);
411 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
412 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
413 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
414 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
415 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
416 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
417 SI_CPDMA_SKIP_SYNC_AFTER | \
418 SI_CPDMA_SKIP_SYNC_BEFORE | \
419 SI_CPDMA_SKIP_GFX_SYNC | \
420 SI_CPDMA_SKIP_BO_LIST_UPDATE)
422 void si_copy_buffer(struct si_context
*sctx
,
423 struct pipe_resource
*dst
, struct pipe_resource
*src
,
424 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
425 unsigned user_flags
);
426 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
427 uint64_t offset
, unsigned size
);
428 void si_init_cp_dma_functions(struct si_context
*sctx
);
431 void si_init_debug_functions(struct si_context
*sctx
);
432 void si_check_vm_faults(struct r600_common_context
*ctx
,
433 struct radeon_saved_cs
*saved
, enum ring_type ring
);
434 bool si_replace_shader(unsigned num
, struct ac_shader_binary
*binary
);
437 void si_init_dma_functions(struct si_context
*sctx
);
439 /* si_hw_context.c */
440 void si_context_gfx_flush(void *context
, unsigned flags
,
441 struct pipe_fence_handle
**fence
);
442 void si_begin_new_cs(struct si_context
*ctx
);
443 void si_need_cs_space(struct si_context
*ctx
);
446 void si_init_compute_functions(struct si_context
*sctx
);
448 /* si_perfcounters.c */
449 void si_init_perfcounters(struct si_screen
*screen
);
452 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
453 const struct pipe_video_codec
*templ
);
455 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
456 const struct pipe_video_buffer
*tmpl
);
463 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
465 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
469 si_set_atom_dirty(struct si_context
*sctx
,
470 struct r600_atom
*atom
, bool dirty
)
472 unsigned bit
= 1 << atom
->id
;
475 sctx
->dirty_atoms
|= bit
;
477 sctx
->dirty_atoms
&= ~bit
;
481 si_is_atom_dirty(struct si_context
*sctx
,
482 struct r600_atom
*atom
)
484 unsigned bit
= 1 << atom
->id
;
486 return sctx
->dirty_atoms
& bit
;
490 si_mark_atom_dirty(struct si_context
*sctx
,
491 struct r600_atom
*atom
)
493 si_set_atom_dirty(sctx
, atom
, true);
496 static inline struct si_shader_ctx_state
*si_get_vs(struct si_context
*sctx
)
498 if (sctx
->gs_shader
.cso
)
499 return &sctx
->gs_shader
;
500 if (sctx
->tes_shader
.cso
)
501 return &sctx
->tes_shader
;
503 return &sctx
->vs_shader
;
506 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
508 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
510 return vs
->cso
? &vs
->cso
->info
: NULL
;
513 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
515 if (sctx
->gs_shader
.cso
)
516 return sctx
->gs_shader
.cso
->gs_copy_shader
;
518 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
519 return vs
->current
? vs
->current
: NULL
;
522 static inline unsigned
523 si_optimal_tcc_alignment(struct si_context
*sctx
, unsigned upload_size
)
525 unsigned alignment
, tcc_cache_line_size
;
527 /* If the upload size is less than the cache line size (e.g. 16, 32),
528 * the whole thing will fit into a cache line if we align it to its size.
529 * The idea is that multiple small uploads can share a cache line.
530 * If the upload size is greater, align it to the cache line size.
532 alignment
= util_next_power_of_two(upload_size
);
533 tcc_cache_line_size
= sctx
->screen
->b
.info
.tcc_cache_line_size
;
534 return MIN2(alignment
, tcc_cache_line_size
);