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radeonsi: fix a crash if ps_shader.cso is NULL in si_get_total_colormask
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29
30 #include "util/u_dynarray.h"
31 #include "util/u_idalloc.h"
32
33 #ifdef PIPE_ARCH_BIG_ENDIAN
34 #define SI_BIG_ENDIAN 1
35 #else
36 #define SI_BIG_ENDIAN 0
37 #endif
38
39 #define ATI_VENDOR_ID 0x1002
40
41 #define SI_NOT_QUERY 0xffffffff
42
43 /* The base vertex and primitive restart can be any number, but we must pick
44 * one which will mean "unknown" for the purpose of state tracking and
45 * the number shouldn't be a commonly-used one. */
46 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
47 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
48 #define SI_NUM_SMOOTH_AA_SAMPLES 8
49 #define SI_GS_PER_ES 128
50 /* Alignment for optimal CP DMA performance. */
51 #define SI_CPDMA_ALIGNMENT 32
52
53 /* Pipeline & streamout query controls. */
54 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
55 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
56 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
57 /* Instruction cache. */
58 #define SI_CONTEXT_INV_ICACHE (1 << 3)
59 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
60 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
61 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
62 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
63 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
64 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
65 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
66 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
67 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
68 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
69 * a CB or DB flush. */
70 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
71 /* Framebuffer caches. */
72 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
73 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
74 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
75 /* Engine synchronization. */
76 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
77 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
78 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
79 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
80 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
81
82 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
83 #define SI_PREFETCH_LS (1 << 1)
84 #define SI_PREFETCH_HS (1 << 2)
85 #define SI_PREFETCH_ES (1 << 3)
86 #define SI_PREFETCH_GS (1 << 4)
87 #define SI_PREFETCH_VS (1 << 5)
88 #define SI_PREFETCH_PS (1 << 6)
89
90 #define SI_MAX_BORDER_COLORS 4096
91 #define SI_MAX_VIEWPORTS 16
92 #define SIX_BITS 0x3F
93 #define SI_MAP_BUFFER_ALIGNMENT 64
94 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
95
96 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
97 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
98 #define SI_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
99 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
100 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
101 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
102 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
103
104 /* Debug flags. */
105 enum {
106 /* Shader logging options: */
107 DBG_VS = PIPE_SHADER_VERTEX,
108 DBG_PS = PIPE_SHADER_FRAGMENT,
109 DBG_GS = PIPE_SHADER_GEOMETRY,
110 DBG_TCS = PIPE_SHADER_TESS_CTRL,
111 DBG_TES = PIPE_SHADER_TESS_EVAL,
112 DBG_CS = PIPE_SHADER_COMPUTE,
113 DBG_NO_IR,
114 DBG_NO_TGSI,
115 DBG_NO_ASM,
116 DBG_PREOPT_IR,
117
118 /* Shader compiler options the shader cache should be aware of: */
119 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
120 DBG_UNSAFE_MATH,
121 DBG_SI_SCHED,
122
123 /* Shader compiler options (with no effect on the shader cache): */
124 DBG_CHECK_IR,
125 DBG_NIR,
126 DBG_MONOLITHIC_SHADERS,
127 DBG_NO_OPT_VARIANT,
128
129 /* Information logging options: */
130 DBG_INFO,
131 DBG_TEX,
132 DBG_COMPUTE,
133 DBG_VM,
134
135 /* Driver options: */
136 DBG_FORCE_DMA,
137 DBG_NO_ASYNC_DMA,
138 DBG_NO_WC,
139 DBG_CHECK_VM,
140 DBG_RESERVE_VMID,
141
142 /* 3D engine options: */
143 DBG_SWITCH_ON_EOP,
144 DBG_NO_OUT_OF_ORDER,
145 DBG_NO_DPBB,
146 DBG_NO_DFSM,
147 DBG_DPBB,
148 DBG_DFSM,
149 DBG_NO_HYPERZ,
150 DBG_NO_RB_PLUS,
151 DBG_NO_2D_TILING,
152 DBG_NO_TILING,
153 DBG_NO_DCC,
154 DBG_NO_DCC_CLEAR,
155 DBG_NO_DCC_FB,
156 DBG_NO_DCC_MSAA,
157 DBG_DCC_MSAA,
158 DBG_NO_FMASK,
159
160 /* Tests: */
161 DBG_TEST_DMA,
162 DBG_TEST_VMFAULT_CP,
163 DBG_TEST_VMFAULT_SDMA,
164 DBG_TEST_VMFAULT_SHADER,
165 };
166
167 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
168 #define DBG(name) (1ull << DBG_##name)
169
170 struct si_compute;
171 struct hash_table;
172 struct u_suballocator;
173
174 struct si_screen {
175 struct pipe_screen b;
176 struct radeon_winsys *ws;
177 struct disk_cache *disk_shader_cache;
178
179 struct radeon_info info;
180 uint64_t debug_flags;
181 char renderer_string[100];
182
183 unsigned gs_table_depth;
184 unsigned tess_offchip_block_dw_size;
185 unsigned tess_offchip_ring_size;
186 unsigned tess_factor_ring_size;
187 unsigned vgt_hs_offchip_param;
188 bool has_clear_state;
189 bool has_distributed_tess;
190 bool has_draw_indirect_multi;
191 bool has_out_of_order_rast;
192 bool assume_no_z_fights;
193 bool commutative_blend_add;
194 bool clear_db_cache_before_clear;
195 bool has_msaa_sample_loc_bug;
196 bool has_ls_vgpr_init_bug;
197 bool dpbb_allowed;
198 bool dfsm_allowed;
199 bool llvm_has_working_vgpr_indexing;
200
201 /* Whether shaders are monolithic (1-part) or separate (3-part). */
202 bool use_monolithic_shaders;
203 bool record_llvm_ir;
204 bool has_rbplus; /* if RB+ registers exist */
205 bool rbplus_allowed; /* if RB+ is allowed */
206 bool dcc_msaa_allowed;
207 bool cpdma_prefetch_writes_memory;
208
209 struct slab_parent_pool pool_transfers;
210
211 /* Texture filter settings. */
212 int force_aniso; /* -1 = disabled */
213
214 /* Auxiliary context. Mainly used to initialize resources.
215 * It must be locked prior to using and flushed before unlocking. */
216 struct pipe_context *aux_context;
217 mtx_t aux_context_lock;
218
219 /* This must be in the screen, because UE4 uses one context for
220 * compilation and another one for rendering.
221 */
222 unsigned num_compilations;
223 /* Along with ST_DEBUG=precompile, this should show if applications
224 * are loading shaders on demand. This is a monotonic counter.
225 */
226 unsigned num_shaders_created;
227 unsigned num_shader_cache_hits;
228
229 /* GPU load thread. */
230 mtx_t gpu_load_mutex;
231 thrd_t gpu_load_thread;
232 union si_mmio_counters mmio_counters;
233 volatile unsigned gpu_load_stop_thread; /* bool */
234
235 /* Performance counters. */
236 struct si_perfcounters *perfcounters;
237
238 /* If pipe_screen wants to recompute and re-emit the framebuffer,
239 * sampler, and image states of all contexts, it should atomically
240 * increment this.
241 *
242 * Each context will compare this with its own last known value of
243 * the counter before drawing and re-emit the states accordingly.
244 */
245 unsigned dirty_tex_counter;
246
247 /* Atomically increment this counter when an existing texture's
248 * metadata is enabled or disabled in a way that requires changing
249 * contexts' compressed texture binding masks.
250 */
251 unsigned compressed_colortex_counter;
252
253 struct {
254 /* Context flags to set so that all writes from earlier jobs
255 * in the CP are seen by L2 clients.
256 */
257 unsigned cp_to_L2;
258
259 /* Context flags to set so that all writes from earlier jobs
260 * that end in L2 are seen by CP.
261 */
262 unsigned L2_to_cp;
263 } barrier_flags;
264
265 mtx_t shader_parts_mutex;
266 struct si_shader_part *vs_prologs;
267 struct si_shader_part *tcs_epilogs;
268 struct si_shader_part *gs_prologs;
269 struct si_shader_part *ps_prologs;
270 struct si_shader_part *ps_epilogs;
271
272 /* Shader cache in memory.
273 *
274 * Design & limitations:
275 * - The shader cache is per screen (= per process), never saved to
276 * disk, and skips redundant shader compilations from TGSI to bytecode.
277 * - It can only be used with one-variant-per-shader support, in which
278 * case only the main (typically middle) part of shaders is cached.
279 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
280 * variants of VS and TES are cached, so LS and ES aren't.
281 * - GS and CS aren't cached, but it's certainly possible to cache
282 * those as well.
283 */
284 mtx_t shader_cache_mutex;
285 struct hash_table *shader_cache;
286
287 /* Shader compiler queue for multithreaded compilation. */
288 struct util_queue shader_compiler_queue;
289 /* Use at most 3 normal compiler threads on quadcore and better.
290 * Hyperthreaded CPUs report the number of threads, but we want
291 * the number of cores. */
292 LLVMTargetMachineRef tm[3]; /* used by the queue only */
293
294 struct util_queue shader_compiler_queue_low_priority;
295 /* Use at most 2 low priority threads on quadcore and better.
296 * We want to minimize the impact on multithreaded Mesa. */
297 LLVMTargetMachineRef tm_low_priority[2]; /* at most 2 threads */
298 };
299
300 struct si_blend_color {
301 struct r600_atom atom;
302 struct pipe_blend_color state;
303 bool any_nonzeros;
304 };
305
306 struct si_sampler_view {
307 struct pipe_sampler_view base;
308 /* [0..7] = image descriptor
309 * [4..7] = buffer descriptor */
310 uint32_t state[8];
311 uint32_t fmask_state[8];
312 const struct legacy_surf_level *base_level_info;
313 ubyte base_level;
314 ubyte block_width;
315 bool is_stencil_sampler;
316 bool is_integer;
317 bool dcc_incompatible;
318 };
319
320 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
321
322 struct si_sampler_state {
323 #ifdef DEBUG
324 unsigned magic;
325 #endif
326 uint32_t val[4];
327 uint32_t integer_val[4];
328 uint32_t upgraded_depth_val[4];
329 };
330
331 struct si_cs_shader_state {
332 struct si_compute *program;
333 struct si_compute *emitted_program;
334 unsigned offset;
335 bool initialized;
336 bool uses_scratch;
337 };
338
339 struct si_samplers {
340 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
341 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
342
343 /* The i-th bit is set if that element is enabled (non-NULL resource). */
344 unsigned enabled_mask;
345 uint32_t needs_depth_decompress_mask;
346 uint32_t needs_color_decompress_mask;
347 };
348
349 struct si_images {
350 struct pipe_image_view views[SI_NUM_IMAGES];
351 uint32_t needs_color_decompress_mask;
352 unsigned enabled_mask;
353 };
354
355 struct si_framebuffer {
356 struct r600_atom atom;
357 struct pipe_framebuffer_state state;
358 unsigned colorbuf_enabled_4bit;
359 unsigned spi_shader_col_format;
360 unsigned spi_shader_col_format_alpha;
361 unsigned spi_shader_col_format_blend;
362 unsigned spi_shader_col_format_blend_alpha;
363 ubyte nr_samples:5; /* at most 16xAA */
364 ubyte log_samples:3; /* at most 4 = 16xAA */
365 ubyte compressed_cb_mask;
366 ubyte uncompressed_cb_mask;
367 ubyte color_is_int8;
368 ubyte color_is_int10;
369 ubyte dirty_cbufs;
370 bool dirty_zsbuf;
371 bool any_dst_linear;
372 bool CB_has_shader_readable_metadata;
373 bool DB_has_shader_readable_metadata;
374 };
375
376 struct si_signed_scissor {
377 int minx;
378 int miny;
379 int maxx;
380 int maxy;
381 };
382
383 struct si_scissors {
384 struct r600_atom atom;
385 unsigned dirty_mask;
386 struct pipe_scissor_state states[SI_MAX_VIEWPORTS];
387 };
388
389 struct si_viewports {
390 struct r600_atom atom;
391 unsigned dirty_mask;
392 unsigned depth_range_dirty_mask;
393 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
394 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
395 };
396
397 struct si_clip_state {
398 struct r600_atom atom;
399 struct pipe_clip_state state;
400 bool any_nonzeros;
401 };
402
403 struct si_sample_locs {
404 struct r600_atom atom;
405 unsigned nr_samples;
406 };
407
408 struct si_sample_mask {
409 struct r600_atom atom;
410 uint16_t sample_mask;
411 };
412
413 struct si_streamout_target {
414 struct pipe_stream_output_target b;
415
416 /* The buffer where BUFFER_FILLED_SIZE is stored. */
417 struct r600_resource *buf_filled_size;
418 unsigned buf_filled_size_offset;
419 bool buf_filled_size_valid;
420
421 unsigned stride_in_dw;
422 };
423
424 struct si_streamout {
425 struct r600_atom begin_atom;
426 bool begin_emitted;
427
428 unsigned enabled_mask;
429 unsigned num_targets;
430 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
431
432 unsigned append_bitmask;
433 bool suspended;
434
435 /* External state which comes from the vertex shader,
436 * it must be set explicitly when binding a shader. */
437 uint16_t *stride_in_dw;
438 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
439
440 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
441 unsigned hw_enabled_mask;
442
443 /* The state of VGT_STRMOUT_(CONFIG|EN). */
444 struct r600_atom enable_atom;
445 bool streamout_enabled;
446 bool prims_gen_query_enabled;
447 int num_prims_gen_queries;
448 };
449
450 /* A shader state consists of the shader selector, which is a constant state
451 * object shared by multiple contexts and shouldn't be modified, and
452 * the current shader variant selected for this context.
453 */
454 struct si_shader_ctx_state {
455 struct si_shader_selector *cso;
456 struct si_shader *current;
457 };
458
459 #define SI_NUM_VGT_PARAM_KEY_BITS 12
460 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
461
462 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
463 * Some fields are set by state-change calls, most are set by draw_vbo.
464 */
465 union si_vgt_param_key {
466 struct {
467 unsigned prim:4;
468 unsigned uses_instancing:1;
469 unsigned multi_instances_smaller_than_primgroup:1;
470 unsigned primitive_restart:1;
471 unsigned count_from_stream_output:1;
472 unsigned line_stipple_enabled:1;
473 unsigned uses_tess:1;
474 unsigned tess_uses_prim_id:1;
475 unsigned uses_gs:1;
476 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
477 } u;
478 uint32_t index;
479 };
480
481 struct si_texture_handle
482 {
483 unsigned desc_slot;
484 bool desc_dirty;
485 struct pipe_sampler_view *view;
486 struct si_sampler_state sstate;
487 };
488
489 struct si_image_handle
490 {
491 unsigned desc_slot;
492 bool desc_dirty;
493 struct pipe_image_view view;
494 };
495
496 struct si_saved_cs {
497 struct pipe_reference reference;
498 struct si_context *ctx;
499 struct radeon_saved_cs gfx;
500 struct r600_resource *trace_buf;
501 unsigned trace_id;
502
503 unsigned gfx_last_dw;
504 bool flushed;
505 int64_t time_flush;
506 };
507
508 struct si_context {
509 struct pipe_context b; /* base class */
510
511 enum radeon_family family;
512 enum chip_class chip_class;
513
514 struct radeon_winsys *ws;
515 struct radeon_winsys_ctx *ctx;
516 struct radeon_winsys_cs *gfx_cs;
517 struct radeon_winsys_cs *dma_cs;
518 struct pipe_fence_handle *last_gfx_fence;
519 struct pipe_fence_handle *last_sdma_fence;
520 struct r600_resource *eop_bug_scratch;
521 struct u_upload_mgr *cached_gtt_allocator;
522 struct threaded_context *tc;
523 struct u_suballocator *allocator_zeroed_memory;
524 struct slab_child_pool pool_transfers;
525 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
526 struct pipe_device_reset_callback device_reset_callback;
527 struct u_log_context *log;
528 void *query_result_shader;
529 struct blitter_context *blitter;
530 void *custom_dsa_flush;
531 void *custom_blend_resolve;
532 void *custom_blend_fmask_decompress;
533 void *custom_blend_eliminate_fastclear;
534 void *custom_blend_dcc_decompress;
535 void *vs_blit_pos;
536 void *vs_blit_pos_layered;
537 void *vs_blit_color;
538 void *vs_blit_color_layered;
539 void *vs_blit_texcoord;
540 struct si_screen *screen;
541 struct pipe_debug_callback debug;
542 LLVMTargetMachineRef tm; /* only non-threaded compilation */
543 struct si_shader_ctx_state fixed_func_tcs_shader;
544 struct r600_resource *wait_mem_scratch;
545 unsigned wait_mem_number;
546 uint16_t prefetch_L2_mask;
547
548 bool gfx_flush_in_progress:1;
549 bool compute_is_busy:1;
550
551 unsigned num_gfx_cs_flushes;
552 unsigned initial_gfx_cs_size;
553 unsigned gpu_reset_counter;
554 unsigned last_dirty_tex_counter;
555 unsigned last_compressed_colortex_counter;
556 unsigned last_num_draw_calls;
557 unsigned flags; /* flush flags */
558 /* Current unaccounted memory usage. */
559 uint64_t vram;
560 uint64_t gtt;
561
562 /* Atoms (direct states). */
563 union si_state_atoms atoms;
564 unsigned dirty_atoms; /* mask */
565 /* PM4 states (precomputed immutable states) */
566 unsigned dirty_states;
567 union si_state queued;
568 union si_state emitted;
569
570 /* Atom declarations. */
571 struct si_framebuffer framebuffer;
572 struct si_sample_locs msaa_sample_locs;
573 struct r600_atom db_render_state;
574 struct r600_atom dpbb_state;
575 struct r600_atom msaa_config;
576 struct si_sample_mask sample_mask;
577 struct r600_atom cb_render_state;
578 unsigned last_cb_target_mask;
579 struct si_blend_color blend_color;
580 struct r600_atom clip_regs;
581 struct si_clip_state clip_state;
582 struct si_shader_data shader_pointers;
583 struct si_stencil_ref stencil_ref;
584 struct r600_atom spi_map;
585 struct si_scissors scissors;
586 struct si_streamout streamout;
587 struct si_viewports viewports;
588
589 /* Precomputed states. */
590 struct si_pm4_state *init_config;
591 struct si_pm4_state *init_config_gs_rings;
592 bool init_config_has_vgt_flush;
593 struct si_pm4_state *vgt_shader_config[4];
594
595 /* shaders */
596 struct si_shader_ctx_state ps_shader;
597 struct si_shader_ctx_state gs_shader;
598 struct si_shader_ctx_state vs_shader;
599 struct si_shader_ctx_state tcs_shader;
600 struct si_shader_ctx_state tes_shader;
601 struct si_cs_shader_state cs_shader_state;
602
603 /* shader information */
604 struct si_vertex_elements *vertex_elements;
605 unsigned sprite_coord_enable;
606 bool flatshade;
607 bool do_update_shaders;
608
609 /* vertex buffer descriptors */
610 uint32_t *vb_descriptors_gpu_list;
611 struct r600_resource *vb_descriptors_buffer;
612 unsigned vb_descriptors_offset;
613
614 /* shader descriptors */
615 struct si_descriptors descriptors[SI_NUM_DESCS];
616 unsigned descriptors_dirty;
617 unsigned shader_pointers_dirty;
618 unsigned shader_needs_decompress_mask;
619 struct si_buffer_resources rw_buffers;
620 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
621 struct si_samplers samplers[SI_NUM_SHADERS];
622 struct si_images images[SI_NUM_SHADERS];
623
624 /* other shader resources */
625 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
626 struct pipe_resource *esgs_ring;
627 struct pipe_resource *gsvs_ring;
628 struct pipe_resource *tess_rings;
629 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
630 struct r600_resource *border_color_buffer;
631 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
632 unsigned border_color_count;
633 unsigned num_vs_blit_sgprs;
634 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
635
636 /* Vertex and index buffers. */
637 bool vertex_buffers_dirty;
638 bool vertex_buffer_pointer_dirty;
639 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
640
641 /* MSAA config state. */
642 int ps_iter_samples;
643 bool ps_uses_fbfetch;
644 bool smoothing_enabled;
645
646 /* DB render state. */
647 unsigned ps_db_shader_control;
648 unsigned dbcb_copy_sample;
649 bool dbcb_depth_copy_enabled:1;
650 bool dbcb_stencil_copy_enabled:1;
651 bool db_flush_depth_inplace:1;
652 bool db_flush_stencil_inplace:1;
653 bool db_depth_clear:1;
654 bool db_depth_disable_expclear:1;
655 bool db_stencil_clear:1;
656 bool db_stencil_disable_expclear:1;
657 bool occlusion_queries_disabled:1;
658 bool generate_mipmap_for_depth:1;
659
660 /* Emitted draw state. */
661 bool gs_tri_strip_adj_fix:1;
662 bool ls_vgpr_fix:1;
663 int last_index_size;
664 int last_base_vertex;
665 int last_start_instance;
666 int last_drawid;
667 int last_sh_base_reg;
668 int last_primitive_restart_en;
669 int last_restart_index;
670 int last_gs_out_prim;
671 int last_prim;
672 int last_multi_vgt_param;
673 int last_rast_prim;
674 unsigned last_sc_line_stipple;
675 unsigned current_vs_state;
676 unsigned last_vs_state;
677 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
678
679 /* Scratch buffer */
680 struct r600_atom scratch_state;
681 struct r600_resource *scratch_buffer;
682 unsigned scratch_waves;
683 unsigned spi_tmpring_size;
684
685 struct r600_resource *compute_scratch_buffer;
686
687 /* Emitted derived tessellation state. */
688 /* Local shader (VS), or HS if LS-HS are merged. */
689 struct si_shader *last_ls;
690 struct si_shader_selector *last_tcs;
691 int last_num_tcs_input_cp;
692 int last_tes_sh_base;
693 bool last_tess_uses_primid;
694 unsigned last_num_patches;
695
696 /* Debug state. */
697 bool is_debug;
698 struct si_saved_cs *current_saved_cs;
699 uint64_t dmesg_timestamp;
700 unsigned apitrace_call_number;
701
702 /* Other state */
703 bool need_check_render_feedback;
704 bool decompression_enabled;
705
706 bool vs_writes_viewport_index;
707 bool vs_disables_clipping_viewport;
708
709 /* Precomputed IA_MULTI_VGT_PARAM */
710 union si_vgt_param_key ia_multi_vgt_param_key;
711 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
712
713 /* Bindless descriptors. */
714 struct si_descriptors bindless_descriptors;
715 struct util_idalloc bindless_used_slots;
716 unsigned num_bindless_descriptors;
717 bool bindless_descriptors_dirty;
718 bool graphics_bindless_pointer_dirty;
719 bool compute_bindless_pointer_dirty;
720
721 /* Allocated bindless handles */
722 struct hash_table *tex_handles;
723 struct hash_table *img_handles;
724
725 /* Resident bindless handles */
726 struct util_dynarray resident_tex_handles;
727 struct util_dynarray resident_img_handles;
728
729 /* Resident bindless handles which need decompression */
730 struct util_dynarray resident_tex_needs_color_decompress;
731 struct util_dynarray resident_img_needs_color_decompress;
732 struct util_dynarray resident_tex_needs_depth_decompress;
733
734 /* Bindless state */
735 bool uses_bindless_samplers;
736 bool uses_bindless_images;
737
738 /* MSAA sample locations.
739 * The first index is the sample index.
740 * The second index is the coordinate: X, Y. */
741 float sample_locations_1x[1][2];
742 float sample_locations_2x[2][2];
743 float sample_locations_4x[4][2];
744 float sample_locations_8x[8][2];
745 float sample_locations_16x[16][2];
746
747 /* Misc stats. */
748 unsigned num_draw_calls;
749 unsigned num_decompress_calls;
750 unsigned num_mrt_draw_calls;
751 unsigned num_prim_restart_calls;
752 unsigned num_spill_draw_calls;
753 unsigned num_compute_calls;
754 unsigned num_spill_compute_calls;
755 unsigned num_dma_calls;
756 unsigned num_cp_dma_calls;
757 unsigned num_vs_flushes;
758 unsigned num_ps_flushes;
759 unsigned num_cs_flushes;
760 unsigned num_cb_cache_flushes;
761 unsigned num_db_cache_flushes;
762 unsigned num_L2_invalidates;
763 unsigned num_L2_writebacks;
764 unsigned num_resident_handles;
765 uint64_t num_alloc_tex_transfer_bytes;
766 unsigned last_tex_ps_draw_ratio; /* for query */
767
768 /* Queries. */
769 /* Maintain the list of active queries for pausing between IBs. */
770 int num_occlusion_queries;
771 int num_perfect_occlusion_queries;
772 struct list_head active_queries;
773 unsigned num_cs_dw_queries_suspend;
774
775 /* Render condition. */
776 struct r600_atom render_cond_atom;
777 struct pipe_query *render_cond;
778 unsigned render_cond_mode;
779 bool render_cond_invert;
780 bool render_cond_force_off; /* for u_blitter */
781
782 /* Statistics gathering for the DCC enablement heuristic. It can't be
783 * in r600_texture because r600_texture can be shared by multiple
784 * contexts. This is for back buffers only. We shouldn't get too many
785 * of those.
786 *
787 * X11 DRI3 rotates among a finite set of back buffers. They should
788 * all fit in this array. If they don't, separate DCC might never be
789 * enabled by DCC stat gathering.
790 */
791 struct {
792 struct r600_texture *tex;
793 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
794 struct pipe_query *ps_stats[3];
795 /* If all slots are used and another slot is needed,
796 * the least recently used slot is evicted based on this. */
797 int64_t last_use_timestamp;
798 bool query_active;
799 } dcc_stats[5];
800
801 /* Copy one resource to another using async DMA. */
802 void (*dma_copy)(struct pipe_context *ctx,
803 struct pipe_resource *dst,
804 unsigned dst_level,
805 unsigned dst_x, unsigned dst_y, unsigned dst_z,
806 struct pipe_resource *src,
807 unsigned src_level,
808 const struct pipe_box *src_box);
809
810 void (*dma_clear_buffer)(struct si_context *sctx, struct pipe_resource *dst,
811 uint64_t offset, uint64_t size, unsigned value);
812 };
813
814 /* cik_sdma.c */
815 void cik_init_sdma_functions(struct si_context *sctx);
816
817 /* si_blit.c */
818 enum si_blitter_op /* bitmask */
819 {
820 SI_SAVE_TEXTURES = 1,
821 SI_SAVE_FRAMEBUFFER = 2,
822 SI_SAVE_FRAGMENT_STATE = 4,
823 SI_DISABLE_RENDER_COND = 8,
824 };
825
826 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
827 void si_blitter_end(struct si_context *sctx);
828 void si_init_blit_functions(struct si_context *sctx);
829 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
830 void si_resource_copy_region(struct pipe_context *ctx,
831 struct pipe_resource *dst,
832 unsigned dst_level,
833 unsigned dstx, unsigned dsty, unsigned dstz,
834 struct pipe_resource *src,
835 unsigned src_level,
836 const struct pipe_box *src_box);
837 void si_decompress_dcc(struct si_context *sctx, struct r600_texture *rtex);
838 void si_blit_decompress_depth(struct pipe_context *ctx,
839 struct r600_texture *texture,
840 struct r600_texture *staging,
841 unsigned first_level, unsigned last_level,
842 unsigned first_layer, unsigned last_layer,
843 unsigned first_sample, unsigned last_sample);
844
845 /* si_buffer.c */
846 bool si_rings_is_buffer_referenced(struct si_context *sctx,
847 struct pb_buffer *buf,
848 enum radeon_bo_usage usage);
849 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
850 struct r600_resource *resource,
851 unsigned usage);
852 void si_init_resource_fields(struct si_screen *sscreen,
853 struct r600_resource *res,
854 uint64_t size, unsigned alignment);
855 bool si_alloc_resource(struct si_screen *sscreen,
856 struct r600_resource *res);
857 struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
858 unsigned flags,
859 unsigned usage,
860 unsigned size,
861 unsigned alignment);
862 void si_replace_buffer_storage(struct pipe_context *ctx,
863 struct pipe_resource *dst,
864 struct pipe_resource *src);
865 void si_init_screen_buffer_functions(struct si_screen *sscreen);
866 void si_init_buffer_functions(struct si_context *sctx);
867
868 /* si_clear.c */
869 void vi_dcc_clear_level(struct si_context *sctx,
870 struct r600_texture *rtex,
871 unsigned level, unsigned clear_value);
872 void si_init_clear_functions(struct si_context *sctx);
873
874 /* si_cp_dma.c */
875 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
876 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
877 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
878 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
879 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
880 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
881 SI_CPDMA_SKIP_SYNC_AFTER | \
882 SI_CPDMA_SKIP_SYNC_BEFORE | \
883 SI_CPDMA_SKIP_GFX_SYNC | \
884 SI_CPDMA_SKIP_BO_LIST_UPDATE)
885
886 enum si_coherency {
887 SI_COHERENCY_NONE, /* no cache flushes needed */
888 SI_COHERENCY_SHADER,
889 SI_COHERENCY_CB_META,
890 };
891
892 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
893 uint64_t offset, uint64_t size, unsigned value,
894 enum si_coherency coher);
895 void si_copy_buffer(struct si_context *sctx,
896 struct pipe_resource *dst, struct pipe_resource *src,
897 uint64_t dst_offset, uint64_t src_offset, unsigned size,
898 unsigned user_flags);
899 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
900 uint64_t offset, unsigned size);
901 void cik_emit_prefetch_L2(struct si_context *sctx);
902 void si_init_cp_dma_functions(struct si_context *sctx);
903
904 /* si_debug.c */
905 void si_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
906 struct radeon_saved_cs *saved, bool get_buffer_list);
907 void si_clear_saved_cs(struct radeon_saved_cs *saved);
908 void si_destroy_saved_cs(struct si_saved_cs *scs);
909 void si_auto_log_cs(void *data, struct u_log_context *log);
910 void si_log_hw_flush(struct si_context *sctx);
911 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
912 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
913 void si_init_debug_functions(struct si_context *sctx);
914 void si_check_vm_faults(struct si_context *sctx,
915 struct radeon_saved_cs *saved, enum ring_type ring);
916 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
917
918 /* si_dma.c */
919 void si_init_dma_functions(struct si_context *sctx);
920
921 /* si_dma_cs.c */
922 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
923 struct r600_resource *dst, struct r600_resource *src);
924 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
925 struct pipe_fence_handle **fence);
926 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
927 uint64_t offset, uint64_t size, unsigned value);
928
929 /* si_fence.c */
930 void si_gfx_write_event_eop(struct si_context *ctx,
931 unsigned event, unsigned event_flags,
932 unsigned data_sel,
933 struct r600_resource *buf, uint64_t va,
934 uint32_t new_fence, unsigned query_type);
935 unsigned si_gfx_write_fence_dwords(struct si_screen *screen);
936 void si_gfx_wait_fence(struct si_context *ctx,
937 uint64_t va, uint32_t ref, uint32_t mask);
938 void si_init_fence_functions(struct si_context *ctx);
939 void si_init_screen_fence_functions(struct si_screen *screen);
940 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
941 struct tc_unflushed_batch_token *tc_token);
942
943 /* si_get.c */
944 const char *si_get_family_name(const struct si_screen *sscreen);
945 void si_init_screen_get_functions(struct si_screen *sscreen);
946
947 /* si_gfx_cs.c */
948 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
949 struct pipe_fence_handle **fence);
950 void si_begin_new_gfx_cs(struct si_context *ctx);
951 void si_need_gfx_cs_space(struct si_context *ctx);
952
953 /* r600_gpu_load.c */
954 void si_gpu_load_kill_thread(struct si_screen *sscreen);
955 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
956 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
957 uint64_t begin);
958
959 /* si_compute.c */
960 void si_init_compute_functions(struct si_context *sctx);
961
962 /* si_perfcounters.c */
963 void si_init_perfcounters(struct si_screen *screen);
964
965 /* si_pipe.c */
966 bool si_check_device_reset(struct si_context *sctx);
967
968 /* si_query.c */
969 void si_init_screen_query_functions(struct si_screen *sscreen);
970 void si_init_query_functions(struct si_context *sctx);
971 void si_suspend_queries(struct si_context *sctx);
972 void si_resume_queries(struct si_context *sctx);
973
974 /* si_test_dma.c */
975 void si_test_dma(struct si_screen *sscreen);
976
977 /* si_uvd.c */
978 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
979 const struct pipe_video_codec *templ);
980
981 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
982 const struct pipe_video_buffer *tmpl);
983
984 /* si_viewport.c */
985 void si_update_vs_viewport_state(struct si_context *ctx);
986 void si_init_viewport_functions(struct si_context *ctx);
987
988 /* r600_texture.c */
989 bool si_prepare_for_dma_blit(struct si_context *sctx,
990 struct r600_texture *rdst,
991 unsigned dst_level, unsigned dstx,
992 unsigned dsty, unsigned dstz,
993 struct r600_texture *rsrc,
994 unsigned src_level,
995 const struct pipe_box *src_box);
996 void si_texture_get_fmask_info(struct si_screen *sscreen,
997 struct r600_texture *rtex,
998 unsigned nr_samples,
999 struct r600_fmask_info *out);
1000 void si_texture_get_cmask_info(struct si_screen *sscreen,
1001 struct r600_texture *rtex,
1002 struct r600_cmask_info *out);
1003 void si_eliminate_fast_color_clear(struct si_context *sctx,
1004 struct r600_texture *rtex);
1005 void si_texture_discard_cmask(struct si_screen *sscreen,
1006 struct r600_texture *rtex);
1007 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1008 struct pipe_resource *texture,
1009 struct r600_texture **staging);
1010 void si_print_texture_info(struct si_screen *sscreen,
1011 struct r600_texture *rtex, struct u_log_context *log);
1012 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1013 const struct pipe_resource *templ);
1014 bool vi_dcc_formats_compatible(enum pipe_format format1,
1015 enum pipe_format format2);
1016 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1017 unsigned level,
1018 enum pipe_format view_format);
1019 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1020 struct pipe_resource *tex,
1021 unsigned level,
1022 enum pipe_format view_format);
1023 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1024 struct pipe_resource *texture,
1025 const struct pipe_surface *templ,
1026 unsigned width0, unsigned height0,
1027 unsigned width, unsigned height);
1028 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1029 void vi_separate_dcc_try_enable(struct si_context *sctx,
1030 struct r600_texture *tex);
1031 void vi_separate_dcc_start_query(struct si_context *sctx,
1032 struct r600_texture *tex);
1033 void vi_separate_dcc_stop_query(struct si_context *sctx,
1034 struct r600_texture *tex);
1035 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1036 struct r600_texture *tex);
1037 bool si_texture_disable_dcc(struct si_context *sctx,
1038 struct r600_texture *rtex);
1039 void si_init_screen_texture_functions(struct si_screen *sscreen);
1040 void si_init_context_texture_functions(struct si_context *sctx);
1041
1042
1043 /*
1044 * common helpers
1045 */
1046
1047 static inline void
1048 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1049 {
1050 struct r600_resource *res = (struct r600_resource *)r;
1051
1052 if (res) {
1053 /* Add memory usage for need_gfx_cs_space */
1054 sctx->vram += res->vram_usage;
1055 sctx->gtt += res->gart_usage;
1056 }
1057 }
1058
1059 static inline void
1060 si_invalidate_draw_sh_constants(struct si_context *sctx)
1061 {
1062 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1063 }
1064
1065 static inline void
1066 si_set_atom_dirty(struct si_context *sctx,
1067 struct r600_atom *atom, bool dirty)
1068 {
1069 unsigned bit = 1 << atom->id;
1070
1071 if (dirty)
1072 sctx->dirty_atoms |= bit;
1073 else
1074 sctx->dirty_atoms &= ~bit;
1075 }
1076
1077 static inline bool
1078 si_is_atom_dirty(struct si_context *sctx,
1079 struct r600_atom *atom)
1080 {
1081 unsigned bit = 1 << atom->id;
1082
1083 return sctx->dirty_atoms & bit;
1084 }
1085
1086 static inline void
1087 si_mark_atom_dirty(struct si_context *sctx,
1088 struct r600_atom *atom)
1089 {
1090 si_set_atom_dirty(sctx, atom, true);
1091 }
1092
1093 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1094 {
1095 if (sctx->gs_shader.cso)
1096 return &sctx->gs_shader;
1097 if (sctx->tes_shader.cso)
1098 return &sctx->tes_shader;
1099
1100 return &sctx->vs_shader;
1101 }
1102
1103 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1104 {
1105 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1106
1107 return vs->cso ? &vs->cso->info : NULL;
1108 }
1109
1110 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1111 {
1112 if (sctx->gs_shader.cso)
1113 return sctx->gs_shader.cso->gs_copy_shader;
1114
1115 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1116 return vs->current ? vs->current : NULL;
1117 }
1118
1119 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1120 unsigned processor)
1121 {
1122 return sscreen->debug_flags & (1 << processor);
1123 }
1124
1125 static inline bool si_extra_shader_checks(struct si_screen *sscreen,
1126 unsigned processor)
1127 {
1128 return (sscreen->debug_flags & DBG(CHECK_IR)) ||
1129 si_can_dump_shader(sscreen, processor);
1130 }
1131
1132 static inline bool si_get_strmout_en(struct si_context *sctx)
1133 {
1134 return sctx->streamout.streamout_enabled ||
1135 sctx->streamout.prims_gen_query_enabled;
1136 }
1137
1138 static inline unsigned
1139 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1140 {
1141 unsigned alignment, tcc_cache_line_size;
1142
1143 /* If the upload size is less than the cache line size (e.g. 16, 32),
1144 * the whole thing will fit into a cache line if we align it to its size.
1145 * The idea is that multiple small uploads can share a cache line.
1146 * If the upload size is greater, align it to the cache line size.
1147 */
1148 alignment = util_next_power_of_two(upload_size);
1149 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1150 return MIN2(alignment, tcc_cache_line_size);
1151 }
1152
1153 static inline void
1154 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1155 {
1156 if (pipe_reference(&(*dst)->reference, &src->reference))
1157 si_destroy_saved_cs(*dst);
1158
1159 *dst = src;
1160 }
1161
1162 static inline void
1163 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1164 bool shaders_read_metadata)
1165 {
1166 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1167 SI_CONTEXT_INV_VMEM_L1;
1168
1169 if (sctx->chip_class >= GFX9) {
1170 /* Single-sample color is coherent with shaders on GFX9, but
1171 * L2 metadata must be flushed if shaders read metadata.
1172 * (DCC, CMASK).
1173 */
1174 if (num_samples >= 2)
1175 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1176 else if (shaders_read_metadata)
1177 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1178 } else {
1179 /* SI-CI-VI */
1180 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1181 }
1182 }
1183
1184 static inline void
1185 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1186 bool include_stencil, bool shaders_read_metadata)
1187 {
1188 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1189 SI_CONTEXT_INV_VMEM_L1;
1190
1191 if (sctx->chip_class >= GFX9) {
1192 /* Single-sample depth (not stencil) is coherent with shaders
1193 * on GFX9, but L2 metadata must be flushed if shaders read
1194 * metadata.
1195 */
1196 if (num_samples >= 2 || include_stencil)
1197 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1198 else if (shaders_read_metadata)
1199 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1200 } else {
1201 /* SI-CI-VI */
1202 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1203 }
1204 }
1205
1206 static inline bool
1207 si_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
1208 {
1209 return (stencil_sampler && tex->can_sample_s) ||
1210 (!stencil_sampler && tex->can_sample_z);
1211 }
1212
1213 static inline bool
1214 si_htile_enabled(struct r600_texture *tex, unsigned level)
1215 {
1216 return tex->htile_offset && level == 0;
1217 }
1218
1219 static inline bool
1220 vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level)
1221 {
1222 assert(!tex->tc_compatible_htile || tex->htile_offset);
1223 return tex->tc_compatible_htile && level == 0;
1224 }
1225
1226 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1227 {
1228 if (sctx->ps_uses_fbfetch)
1229 return sctx->framebuffer.nr_samples;
1230
1231 return sctx->ps_iter_samples;
1232 }
1233
1234 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1235 {
1236 if (sctx->queued.named.rasterizer->rasterizer_discard)
1237 return 0;
1238
1239 struct si_shader_selector *ps = sctx->ps_shader.cso;
1240 if (!ps)
1241 return 0;
1242
1243 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1244 sctx->queued.named.blend->cb_target_mask;
1245
1246 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1247 colormask &= ps->colors_written_4bit;
1248 else if (!ps->colors_written_4bit)
1249 colormask = 0; /* color0 writes all cbufs, but it's not written */
1250
1251 return colormask;
1252 }
1253
1254 /**
1255 * Return true if there is enough memory in VRAM and GTT for the buffers
1256 * added so far.
1257 *
1258 * \param vram VRAM memory size not added to the buffer list yet
1259 * \param gtt GTT memory size not added to the buffer list yet
1260 */
1261 static inline bool
1262 radeon_cs_memory_below_limit(struct si_screen *screen,
1263 struct radeon_winsys_cs *cs,
1264 uint64_t vram, uint64_t gtt)
1265 {
1266 vram += cs->used_vram;
1267 gtt += cs->used_gart;
1268
1269 /* Anything that goes above the VRAM size should go to GTT. */
1270 if (vram > screen->info.vram_size)
1271 gtt += vram - screen->info.vram_size;
1272
1273 /* Now we just need to check if we have enough GTT. */
1274 return gtt < screen->info.gart_size * 0.7;
1275 }
1276
1277 /**
1278 * Add a buffer to the buffer list for the given command stream (CS).
1279 *
1280 * All buffers used by a CS must be added to the list. This tells the kernel
1281 * driver which buffers are used by GPU commands. Other buffers can
1282 * be swapped out (not accessible) during execution.
1283 *
1284 * The buffer list becomes empty after every context flush and must be
1285 * rebuilt.
1286 */
1287 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1288 struct radeon_winsys_cs *cs,
1289 struct r600_resource *rbo,
1290 enum radeon_bo_usage usage,
1291 enum radeon_bo_priority priority)
1292 {
1293 assert(usage);
1294 sctx->ws->cs_add_buffer(
1295 cs, rbo->buf,
1296 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1297 rbo->domains, priority);
1298 }
1299
1300 /**
1301 * Same as above, but also checks memory usage and flushes the context
1302 * accordingly.
1303 *
1304 * When this SHOULD NOT be used:
1305 *
1306 * - if si_context_add_resource_size has been called for the buffer
1307 * followed by *_need_cs_space for checking the memory usage
1308 *
1309 * - if si_need_dma_space has been called for the buffer
1310 *
1311 * - when emitting state packets and draw packets (because preceding packets
1312 * can't be re-emitted at that point)
1313 *
1314 * - if shader resource "enabled_mask" is not up-to-date or there is
1315 * a different constraint disallowing a context flush
1316 */
1317 static inline void
1318 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1319 struct r600_resource *rbo,
1320 enum radeon_bo_usage usage,
1321 enum radeon_bo_priority priority,
1322 bool check_mem)
1323 {
1324 if (check_mem &&
1325 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1326 sctx->vram + rbo->vram_usage,
1327 sctx->gtt + rbo->gart_usage))
1328 si_flush_gfx_cs(sctx, PIPE_FLUSH_ASYNC, NULL);
1329
1330 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, rbo, usage, priority);
1331 }
1332
1333 #define PRINT_ERR(fmt, args...) \
1334 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1335
1336 #endif