radeonsi: dump buffer lists while debugging
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef SI_PIPE_H
27 #define SI_PIPE_H
28
29 #include "si_state.h"
30
31 #include <llvm-c/TargetMachine.h>
32
33 #ifdef PIPE_ARCH_BIG_ENDIAN
34 #define SI_BIG_ENDIAN 1
35 #else
36 #define SI_BIG_ENDIAN 0
37 #endif
38
39 /* The base vertex and primitive restart can be any number, but we must pick
40 * one which will mean "unknown" for the purpose of state tracking and
41 * the number shouldn't be a commonly-used one. */
42 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
43 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
44 #define SI_NUM_SMOOTH_AA_SAMPLES 8
45
46 /* Instruction cache. */
47 #define SI_CONTEXT_INV_ICACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
48 /* Cache used by scalar memory (SMEM) instructions. They also use TC
49 * as a second level cache, which isn't flushed by this.
50 * Other names: constant cache, data cache, DCACHE */
51 #define SI_CONTEXT_INV_KCACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
52 /* Caches used by vector memory (VMEM) instructions.
53 * L1 can optionally be bypassed (GLC=1) and can only be used by shaders.
54 * L2 is used by shaders and can be used by other blocks (CP, sDMA). */
55 #define SI_CONTEXT_INV_TC_L1 (R600_CONTEXT_PRIVATE_FLAG << 2)
56 #define SI_CONTEXT_INV_TC_L2 (R600_CONTEXT_PRIVATE_FLAG << 3)
57 /* Framebuffer caches. */
58 #define SI_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
59 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
60 #define SI_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
61 #define SI_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
62 /* Engine synchronization. */
63 #define SI_CONTEXT_VS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
64 #define SI_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 9)
65 #define SI_CONTEXT_CS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 10)
66 #define SI_CONTEXT_VGT_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 11)
67 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (R600_CONTEXT_PRIVATE_FLAG << 12)
68 /* Compute only. */
69 #define SI_CONTEXT_FLUSH_WITH_INV_L2 (R600_CONTEXT_PRIVATE_FLAG << 13) /* TODO: merge with TC? */
70 #define SI_CONTEXT_FLAG_COMPUTE (R600_CONTEXT_PRIVATE_FLAG << 14)
71
72 #define SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER (SI_CONTEXT_FLUSH_AND_INV_CB | \
73 SI_CONTEXT_FLUSH_AND_INV_CB_META | \
74 SI_CONTEXT_FLUSH_AND_INV_DB | \
75 SI_CONTEXT_FLUSH_AND_INV_DB_META)
76
77 #define SI_ENCODE_TRACE_POINT(id) (0xcafe0000 | ((id) & 0xffff))
78 #define SI_IS_TRACE_POINT(x) (((x) & 0xcafe0000) == 0xcafe0000)
79 #define SI_GET_TRACE_POINT_ID(x) ((x) & 0xffff)
80
81 #define SI_MAX_VIEWPORTS 16
82 #define SI_MAX_BORDER_COLORS 4096
83
84 struct si_compute;
85
86 struct si_screen {
87 struct r600_common_screen b;
88 };
89
90 struct si_blend_color {
91 struct r600_atom atom;
92 struct pipe_blend_color state;
93 };
94
95 struct si_sampler_view {
96 struct pipe_sampler_view base;
97 struct list_head list;
98 struct r600_resource *resource;
99 /* [0..7] = image descriptor
100 * [4..7] = buffer descriptor */
101 uint32_t state[8];
102 uint32_t fmask_state[8];
103 };
104
105 struct si_sampler_state {
106 uint32_t val[4];
107 };
108
109 struct si_cs_shader_state {
110 struct si_compute *program;
111 };
112
113 struct si_textures_info {
114 struct si_sampler_views views;
115 struct si_sampler_states states;
116 uint32_t depth_texture_mask; /* which textures are depth */
117 uint32_t compressed_colortex_mask;
118 };
119
120 struct si_framebuffer {
121 struct r600_atom atom;
122 struct pipe_framebuffer_state state;
123 unsigned nr_samples;
124 unsigned log_samples;
125 unsigned cb0_is_integer;
126 unsigned compressed_cb_mask;
127 unsigned export_16bpc;
128 unsigned dirty_cbufs;
129 bool dirty_zsbuf;
130 };
131
132 struct si_clip_state {
133 struct r600_atom atom;
134 struct pipe_clip_state state;
135 };
136
137 struct si_sample_mask {
138 struct r600_atom atom;
139 uint16_t sample_mask;
140 };
141
142 struct si_scissors {
143 struct r600_atom atom;
144 unsigned dirty_mask;
145 struct pipe_scissor_state states[SI_MAX_VIEWPORTS];
146 };
147
148 struct si_viewports {
149 struct r600_atom atom;
150 unsigned dirty_mask;
151 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
152 };
153
154 struct si_context {
155 struct r600_common_context b;
156 struct blitter_context *blitter;
157 void *custom_dsa_flush;
158 void *custom_blend_resolve;
159 void *custom_blend_decompress;
160 void *custom_blend_fastclear;
161 void *pstipple_sampler_state;
162 struct si_screen *screen;
163 struct pipe_fence_handle *last_gfx_fence;
164 struct si_shader_selector *fixed_func_tcs_shader;
165 LLVMTargetMachineRef tm;
166
167 /* Atoms (direct states). */
168 union si_state_atoms atoms;
169 unsigned dirty_atoms; /* mask */
170 /* PM4 states (precomputed immutable states) */
171 union si_state queued;
172 union si_state emitted;
173
174 /* Atom declarations. */
175 struct r600_atom cache_flush;
176 struct si_framebuffer framebuffer;
177 struct r600_atom msaa_sample_locs;
178 struct r600_atom db_render_state;
179 struct r600_atom msaa_config;
180 struct si_sample_mask sample_mask;
181 struct r600_atom cb_target_mask;
182 struct si_blend_color blend_color;
183 struct r600_atom clip_regs;
184 struct si_clip_state clip_state;
185 struct si_shader_data shader_userdata;
186 struct si_scissors scissors;
187 struct si_viewports viewports;
188 struct si_stencil_ref stencil_ref;
189 struct r600_atom spi_map;
190
191 /* Precomputed states. */
192 struct si_pm4_state *init_config;
193 struct si_pm4_state *vgt_shader_config[4];
194 /* With rasterizer discard, there doesn't have to be a pixel shader.
195 * In that case, we bind this one: */
196 void *dummy_pixel_shader;
197
198 /* shaders */
199 struct si_shader_selector *ps_shader;
200 struct si_shader_selector *gs_shader;
201 struct si_shader_selector *vs_shader;
202 struct si_shader_selector *tcs_shader;
203 struct si_shader_selector *tes_shader;
204 struct si_cs_shader_state cs_shader_state;
205
206 /* shader information */
207 struct si_vertex_element *vertex_elements;
208 unsigned sprite_coord_enable;
209 bool flatshade;
210
211 /* shader descriptors */
212 struct si_descriptors vertex_buffers;
213 struct si_buffer_resources const_buffers[SI_NUM_SHADERS];
214 struct si_buffer_resources rw_buffers[SI_NUM_SHADERS];
215 struct si_textures_info samplers[SI_NUM_SHADERS];
216
217 /* other shader resources */
218 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
219 struct pipe_resource *esgs_ring;
220 struct pipe_resource *gsvs_ring;
221 struct pipe_resource *tf_ring;
222 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
223 struct r600_resource *border_color_buffer;
224 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
225 unsigned border_color_count;
226
227 /* Vertex and index buffers. */
228 bool vertex_buffers_dirty;
229 struct pipe_index_buffer index_buffer;
230 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
231
232 /* MSAA config state. */
233 int ps_iter_samples;
234 bool smoothing_enabled;
235
236 /* DB render state. */
237 bool dbcb_depth_copy_enabled;
238 bool dbcb_stencil_copy_enabled;
239 unsigned dbcb_copy_sample;
240 bool db_inplace_flush_enabled;
241 bool db_depth_clear;
242 bool db_depth_disable_expclear;
243 unsigned ps_db_shader_control;
244
245 /* Emitted draw state. */
246 int last_base_vertex;
247 int last_start_instance;
248 int last_sh_base_reg;
249 int last_primitive_restart_en;
250 int last_restart_index;
251 int last_gs_out_prim;
252 int last_prim;
253 int last_multi_vgt_param;
254 int last_ls_hs_config;
255 int last_rast_prim;
256 unsigned last_sc_line_stipple;
257 int current_rast_prim; /* primitive type after TES, GS */
258 unsigned last_gsvs_itemsize;
259
260 /* Scratch buffer */
261 struct r600_resource *scratch_buffer;
262 boolean emit_scratch_reloc;
263 unsigned scratch_waves;
264 unsigned spi_tmpring_size;
265
266 /* Emitted derived tessellation state. */
267 struct si_shader *last_ls; /* local shader (VS) */
268 struct si_shader_selector *last_tcs;
269 int last_num_tcs_input_cp;
270 int last_tes_sh_base;
271
272 /* Debug state. */
273 bool is_debug;
274 uint32_t *last_ib;
275 unsigned last_ib_dw_size;
276 struct r600_resource *last_trace_buf;
277 struct r600_resource *trace_buf;
278 unsigned trace_id;
279 uint64_t dmesg_timestamp;
280 unsigned last_bo_count;
281 struct radeon_bo_list_item *last_bo_list;
282 };
283
284 /* cik_sdma.c */
285 void cik_sdma_copy(struct pipe_context *ctx,
286 struct pipe_resource *dst,
287 unsigned dst_level,
288 unsigned dstx, unsigned dsty, unsigned dstz,
289 struct pipe_resource *src,
290 unsigned src_level,
291 const struct pipe_box *src_box);
292
293 /* si_blit.c */
294 void si_init_blit_functions(struct si_context *sctx);
295 void si_flush_depth_textures(struct si_context *sctx,
296 struct si_textures_info *textures);
297 void si_decompress_color_textures(struct si_context *sctx,
298 struct si_textures_info *textures);
299 void si_resource_copy_region(struct pipe_context *ctx,
300 struct pipe_resource *dst,
301 unsigned dst_level,
302 unsigned dstx, unsigned dsty, unsigned dstz,
303 struct pipe_resource *src,
304 unsigned src_level,
305 const struct pipe_box *src_box);
306
307 /* si_cp_dma.c */
308 void si_copy_buffer(struct si_context *sctx,
309 struct pipe_resource *dst, struct pipe_resource *src,
310 uint64_t dst_offset, uint64_t src_offset, unsigned size,
311 bool is_framebuffer);
312 void si_init_cp_dma_functions(struct si_context *sctx);
313
314 /* si_debug.c */
315 void si_init_debug_functions(struct si_context *sctx);
316 void si_check_vm_faults(struct si_context *sctx);
317
318 /* si_dma.c */
319 void si_dma_copy(struct pipe_context *ctx,
320 struct pipe_resource *dst,
321 unsigned dst_level,
322 unsigned dstx, unsigned dsty, unsigned dstz,
323 struct pipe_resource *src,
324 unsigned src_level,
325 const struct pipe_box *src_box);
326
327 /* si_hw_context.c */
328 void si_context_gfx_flush(void *context, unsigned flags,
329 struct pipe_fence_handle **fence);
330 void si_begin_new_cs(struct si_context *ctx);
331 void si_need_cs_space(struct si_context *ctx);
332
333 /* si_compute.c */
334 void si_init_compute_functions(struct si_context *sctx);
335
336 /* si_uvd.c */
337 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
338 const struct pipe_video_codec *templ);
339
340 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
341 const struct pipe_video_buffer *tmpl);
342
343 /*
344 * common helpers
345 */
346
347 static inline struct r600_resource *
348 si_resource_create_custom(struct pipe_screen *screen,
349 unsigned usage, unsigned size)
350 {
351 assert(size);
352 return r600_resource(pipe_buffer_create(screen,
353 PIPE_BIND_CUSTOM, usage, size));
354 }
355
356 static inline void
357 si_invalidate_draw_sh_constants(struct si_context *sctx)
358 {
359 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
360 sctx->last_start_instance = -1; /* reset to an unknown value */
361 sctx->last_sh_base_reg = -1; /* reset to an unknown value */
362 }
363
364 static inline void
365 si_set_atom_dirty(struct si_context *sctx,
366 struct r600_atom *atom, bool dirty)
367 {
368 unsigned bit = 1 << (atom->id - 1);
369
370 if (dirty)
371 sctx->dirty_atoms |= bit;
372 else
373 sctx->dirty_atoms &= ~bit;
374 }
375
376 static inline void
377 si_mark_atom_dirty(struct si_context *sctx,
378 struct r600_atom *atom)
379 {
380 si_set_atom_dirty(sctx, atom, true);
381 }
382
383 #endif