2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "si_shader.h"
28 #include "util/u_dynarray.h"
29 #include "util/u_idalloc.h"
31 #ifdef PIPE_ARCH_BIG_ENDIAN
32 #define SI_BIG_ENDIAN 1
34 #define SI_BIG_ENDIAN 0
37 #define ATI_VENDOR_ID 0x1002
39 #define SI_NOT_QUERY 0xffffffff
41 /* The base vertex and primitive restart can be any number, but we must pick
42 * one which will mean "unknown" for the purpose of state tracking and
43 * the number shouldn't be a commonly-used one. */
44 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
45 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
46 #define SI_NUM_SMOOTH_AA_SAMPLES 8
47 #define SI_GS_PER_ES 128
48 /* Alignment for optimal CP DMA performance. */
49 #define SI_CPDMA_ALIGNMENT 32
51 /* Pipeline & streamout query controls. */
52 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
53 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
54 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
55 /* Instruction cache. */
56 #define SI_CONTEXT_INV_ICACHE (1 << 3)
57 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
58 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
59 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
60 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
61 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
62 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
63 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
64 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
65 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
66 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
67 * a CB or DB flush. */
68 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
69 /* Framebuffer caches. */
70 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
71 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
72 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
73 /* Engine synchronization. */
74 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
75 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
76 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
77 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
78 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
80 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
81 #define SI_PREFETCH_LS (1 << 1)
82 #define SI_PREFETCH_HS (1 << 2)
83 #define SI_PREFETCH_ES (1 << 3)
84 #define SI_PREFETCH_GS (1 << 4)
85 #define SI_PREFETCH_VS (1 << 5)
86 #define SI_PREFETCH_PS (1 << 6)
88 #define SI_MAX_BORDER_COLORS 4096
89 #define SI_MAX_VIEWPORTS 16
94 struct u_suballocator
;
98 struct radeon_winsys
*ws
;
99 struct disk_cache
*disk_shader_cache
;
101 struct radeon_info info
;
102 uint64_t debug_flags
;
103 char renderer_string
[100];
105 unsigned gs_table_depth
;
106 unsigned tess_offchip_block_dw_size
;
107 unsigned tess_offchip_ring_size
;
108 unsigned tess_factor_ring_size
;
109 unsigned vgt_hs_offchip_param
;
110 bool has_clear_state
;
111 bool has_distributed_tess
;
112 bool has_draw_indirect_multi
;
113 bool has_out_of_order_rast
;
114 bool assume_no_z_fights
;
115 bool commutative_blend_add
;
116 bool clear_db_cache_before_clear
;
117 bool has_msaa_sample_loc_bug
;
118 bool has_ls_vgpr_init_bug
;
121 bool llvm_has_working_vgpr_indexing
;
123 /* Whether shaders are monolithic (1-part) or separate (3-part). */
124 bool use_monolithic_shaders
;
126 bool has_rbplus
; /* if RB+ registers exist */
127 bool rbplus_allowed
; /* if RB+ is allowed */
128 bool dcc_msaa_allowed
;
129 bool cpdma_prefetch_writes_memory
;
131 struct slab_parent_pool pool_transfers
;
133 /* Texture filter settings. */
134 int force_aniso
; /* -1 = disabled */
136 /* Auxiliary context. Mainly used to initialize resources.
137 * It must be locked prior to using and flushed before unlocking. */
138 struct pipe_context
*aux_context
;
139 mtx_t aux_context_lock
;
141 /* This must be in the screen, because UE4 uses one context for
142 * compilation and another one for rendering.
144 unsigned num_compilations
;
145 /* Along with ST_DEBUG=precompile, this should show if applications
146 * are loading shaders on demand. This is a monotonic counter.
148 unsigned num_shaders_created
;
149 unsigned num_shader_cache_hits
;
151 /* GPU load thread. */
152 mtx_t gpu_load_mutex
;
153 thrd_t gpu_load_thread
;
154 union r600_mmio_counters mmio_counters
;
155 volatile unsigned gpu_load_stop_thread
; /* bool */
157 /* Performance counters. */
158 struct r600_perfcounters
*perfcounters
;
160 /* If pipe_screen wants to recompute and re-emit the framebuffer,
161 * sampler, and image states of all contexts, it should atomically
164 * Each context will compare this with its own last known value of
165 * the counter before drawing and re-emit the states accordingly.
167 unsigned dirty_tex_counter
;
169 /* Atomically increment this counter when an existing texture's
170 * metadata is enabled or disabled in a way that requires changing
171 * contexts' compressed texture binding masks.
173 unsigned compressed_colortex_counter
;
176 /* Context flags to set so that all writes from earlier jobs
177 * in the CP are seen by L2 clients.
181 /* Context flags to set so that all writes from earlier jobs
182 * that end in L2 are seen by CP.
187 mtx_t shader_parts_mutex
;
188 struct si_shader_part
*vs_prologs
;
189 struct si_shader_part
*tcs_epilogs
;
190 struct si_shader_part
*gs_prologs
;
191 struct si_shader_part
*ps_prologs
;
192 struct si_shader_part
*ps_epilogs
;
194 /* Shader cache in memory.
196 * Design & limitations:
197 * - The shader cache is per screen (= per process), never saved to
198 * disk, and skips redundant shader compilations from TGSI to bytecode.
199 * - It can only be used with one-variant-per-shader support, in which
200 * case only the main (typically middle) part of shaders is cached.
201 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
202 * variants of VS and TES are cached, so LS and ES aren't.
203 * - GS and CS aren't cached, but it's certainly possible to cache
206 mtx_t shader_cache_mutex
;
207 struct hash_table
*shader_cache
;
209 /* Shader compiler queue for multithreaded compilation. */
210 struct util_queue shader_compiler_queue
;
211 /* Use at most 3 normal compiler threads on quadcore and better.
212 * Hyperthreaded CPUs report the number of threads, but we want
213 * the number of cores. */
214 LLVMTargetMachineRef tm
[3]; /* used by the queue only */
216 struct util_queue shader_compiler_queue_low_priority
;
217 /* Use at most 2 low priority threads on quadcore and better.
218 * We want to minimize the impact on multithreaded Mesa. */
219 LLVMTargetMachineRef tm_low_priority
[2]; /* at most 2 threads */
222 struct si_blend_color
{
223 struct r600_atom atom
;
224 struct pipe_blend_color state
;
228 struct si_sampler_view
{
229 struct pipe_sampler_view base
;
230 /* [0..7] = image descriptor
231 * [4..7] = buffer descriptor */
233 uint32_t fmask_state
[8];
234 const struct legacy_surf_level
*base_level_info
;
237 bool is_stencil_sampler
;
239 bool dcc_incompatible
;
242 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
244 struct si_sampler_state
{
249 uint32_t integer_val
[4];
250 uint32_t upgraded_depth_val
[4];
253 struct si_cs_shader_state
{
254 struct si_compute
*program
;
255 struct si_compute
*emitted_program
;
262 struct pipe_sampler_view
*views
[SI_NUM_SAMPLERS
];
263 struct si_sampler_state
*sampler_states
[SI_NUM_SAMPLERS
];
265 /* The i-th bit is set if that element is enabled (non-NULL resource). */
266 unsigned enabled_mask
;
267 uint32_t needs_depth_decompress_mask
;
268 uint32_t needs_color_decompress_mask
;
272 struct pipe_image_view views
[SI_NUM_IMAGES
];
273 uint32_t needs_color_decompress_mask
;
274 unsigned enabled_mask
;
277 struct si_framebuffer
{
278 struct r600_atom atom
;
279 struct pipe_framebuffer_state state
;
280 unsigned colorbuf_enabled_4bit
;
281 unsigned spi_shader_col_format
;
282 unsigned spi_shader_col_format_alpha
;
283 unsigned spi_shader_col_format_blend
;
284 unsigned spi_shader_col_format_blend_alpha
;
285 ubyte nr_samples
:5; /* at most 16xAA */
286 ubyte log_samples
:3; /* at most 4 = 16xAA */
287 ubyte compressed_cb_mask
;
288 ubyte uncompressed_cb_mask
;
290 ubyte color_is_int10
;
294 bool CB_has_shader_readable_metadata
;
295 bool DB_has_shader_readable_metadata
;
298 struct si_signed_scissor
{
306 struct r600_atom atom
;
308 struct pipe_scissor_state states
[SI_MAX_VIEWPORTS
];
311 struct si_viewports
{
312 struct r600_atom atom
;
314 unsigned depth_range_dirty_mask
;
315 struct pipe_viewport_state states
[SI_MAX_VIEWPORTS
];
316 struct si_signed_scissor as_scissor
[SI_MAX_VIEWPORTS
];
319 struct si_clip_state
{
320 struct r600_atom atom
;
321 struct pipe_clip_state state
;
325 struct si_sample_locs
{
326 struct r600_atom atom
;
330 struct si_sample_mask
{
331 struct r600_atom atom
;
332 uint16_t sample_mask
;
335 struct si_streamout_target
{
336 struct pipe_stream_output_target b
;
338 /* The buffer where BUFFER_FILLED_SIZE is stored. */
339 struct r600_resource
*buf_filled_size
;
340 unsigned buf_filled_size_offset
;
341 bool buf_filled_size_valid
;
343 unsigned stride_in_dw
;
346 struct si_streamout
{
347 struct r600_atom begin_atom
;
350 unsigned enabled_mask
;
351 unsigned num_targets
;
352 struct si_streamout_target
*targets
[PIPE_MAX_SO_BUFFERS
];
354 unsigned append_bitmask
;
357 /* External state which comes from the vertex shader,
358 * it must be set explicitly when binding a shader. */
359 uint16_t *stride_in_dw
;
360 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
362 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
363 unsigned hw_enabled_mask
;
365 /* The state of VGT_STRMOUT_(CONFIG|EN). */
366 struct r600_atom enable_atom
;
367 bool streamout_enabled
;
368 bool prims_gen_query_enabled
;
369 int num_prims_gen_queries
;
372 /* A shader state consists of the shader selector, which is a constant state
373 * object shared by multiple contexts and shouldn't be modified, and
374 * the current shader variant selected for this context.
376 struct si_shader_ctx_state
{
377 struct si_shader_selector
*cso
;
378 struct si_shader
*current
;
381 #define SI_NUM_VGT_PARAM_KEY_BITS 12
382 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
384 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
385 * Some fields are set by state-change calls, most are set by draw_vbo.
387 union si_vgt_param_key
{
390 unsigned uses_instancing
:1;
391 unsigned multi_instances_smaller_than_primgroup
:1;
392 unsigned primitive_restart
:1;
393 unsigned count_from_stream_output
:1;
394 unsigned line_stipple_enabled
:1;
395 unsigned uses_tess
:1;
396 unsigned tess_uses_prim_id
:1;
398 unsigned _pad
:32 - SI_NUM_VGT_PARAM_KEY_BITS
;
403 struct si_texture_handle
407 struct pipe_sampler_view
*view
;
408 struct si_sampler_state sstate
;
411 struct si_image_handle
415 struct pipe_image_view view
;
419 struct pipe_reference reference
;
420 struct si_context
*ctx
;
421 struct radeon_saved_cs gfx
;
422 struct r600_resource
*trace_buf
;
425 unsigned gfx_last_dw
;
431 struct r600_common_context b
;
432 struct blitter_context
*blitter
;
433 void *custom_dsa_flush
;
434 void *custom_blend_resolve
;
435 void *custom_blend_fmask_decompress
;
436 void *custom_blend_eliminate_fastclear
;
437 void *custom_blend_dcc_decompress
;
439 void *vs_blit_pos_layered
;
441 void *vs_blit_color_layered
;
442 void *vs_blit_texcoord
;
443 struct si_screen
*screen
;
444 struct pipe_debug_callback debug
;
445 LLVMTargetMachineRef tm
; /* only non-threaded compilation */
446 struct si_shader_ctx_state fixed_func_tcs_shader
;
447 struct r600_resource
*wait_mem_scratch
;
448 unsigned wait_mem_number
;
449 uint16_t prefetch_L2_mask
;
451 bool gfx_flush_in_progress
:1;
452 bool compute_is_busy
:1;
454 /* Atoms (direct states). */
455 union si_state_atoms atoms
;
456 unsigned dirty_atoms
; /* mask */
457 /* PM4 states (precomputed immutable states) */
458 unsigned dirty_states
;
459 union si_state queued
;
460 union si_state emitted
;
462 /* Atom declarations. */
463 struct si_framebuffer framebuffer
;
464 struct si_sample_locs msaa_sample_locs
;
465 struct r600_atom db_render_state
;
466 struct r600_atom dpbb_state
;
467 struct r600_atom msaa_config
;
468 struct si_sample_mask sample_mask
;
469 struct r600_atom cb_render_state
;
470 unsigned last_cb_target_mask
;
471 struct si_blend_color blend_color
;
472 struct r600_atom clip_regs
;
473 struct si_clip_state clip_state
;
474 struct si_shader_data shader_pointers
;
475 struct si_stencil_ref stencil_ref
;
476 struct r600_atom spi_map
;
477 struct si_scissors scissors
;
478 struct si_streamout streamout
;
479 struct si_viewports viewports
;
481 /* Precomputed states. */
482 struct si_pm4_state
*init_config
;
483 struct si_pm4_state
*init_config_gs_rings
;
484 bool init_config_has_vgt_flush
;
485 struct si_pm4_state
*vgt_shader_config
[4];
488 struct si_shader_ctx_state ps_shader
;
489 struct si_shader_ctx_state gs_shader
;
490 struct si_shader_ctx_state vs_shader
;
491 struct si_shader_ctx_state tcs_shader
;
492 struct si_shader_ctx_state tes_shader
;
493 struct si_cs_shader_state cs_shader_state
;
495 /* shader information */
496 struct si_vertex_elements
*vertex_elements
;
497 unsigned sprite_coord_enable
;
499 bool do_update_shaders
;
501 /* vertex buffer descriptors */
502 uint32_t *vb_descriptors_gpu_list
;
503 struct r600_resource
*vb_descriptors_buffer
;
504 unsigned vb_descriptors_offset
;
506 /* shader descriptors */
507 struct si_descriptors descriptors
[SI_NUM_DESCS
];
508 unsigned descriptors_dirty
;
509 unsigned shader_pointers_dirty
;
510 unsigned shader_needs_decompress_mask
;
511 struct si_buffer_resources rw_buffers
;
512 struct si_buffer_resources const_and_shader_buffers
[SI_NUM_SHADERS
];
513 struct si_samplers samplers
[SI_NUM_SHADERS
];
514 struct si_images images
[SI_NUM_SHADERS
];
516 /* other shader resources */
517 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on CIK */
518 struct pipe_resource
*esgs_ring
;
519 struct pipe_resource
*gsvs_ring
;
520 struct pipe_resource
*tess_rings
;
521 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
522 struct r600_resource
*border_color_buffer
;
523 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
524 unsigned border_color_count
;
525 unsigned num_vs_blit_sgprs
;
526 uint32_t vs_blit_sh_data
[SI_VS_BLIT_SGPRS_POS_TEXCOORD
];
528 /* Vertex and index buffers. */
529 bool vertex_buffers_dirty
;
530 bool vertex_buffer_pointer_dirty
;
531 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
533 /* MSAA config state. */
535 bool ps_uses_fbfetch
;
536 bool smoothing_enabled
;
538 /* DB render state. */
539 unsigned ps_db_shader_control
;
540 unsigned dbcb_copy_sample
;
541 bool dbcb_depth_copy_enabled
:1;
542 bool dbcb_stencil_copy_enabled
:1;
543 bool db_flush_depth_inplace
:1;
544 bool db_flush_stencil_inplace
:1;
545 bool db_depth_clear
:1;
546 bool db_depth_disable_expclear
:1;
547 bool db_stencil_clear
:1;
548 bool db_stencil_disable_expclear
:1;
549 bool occlusion_queries_disabled
:1;
550 bool generate_mipmap_for_depth
:1;
552 /* Emitted draw state. */
553 bool gs_tri_strip_adj_fix
:1;
556 int last_base_vertex
;
557 int last_start_instance
;
559 int last_sh_base_reg
;
560 int last_primitive_restart_en
;
561 int last_restart_index
;
562 int last_gs_out_prim
;
564 int last_multi_vgt_param
;
566 unsigned last_sc_line_stipple
;
567 unsigned current_vs_state
;
568 unsigned last_vs_state
;
569 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
572 struct r600_atom scratch_state
;
573 struct r600_resource
*scratch_buffer
;
574 unsigned scratch_waves
;
575 unsigned spi_tmpring_size
;
577 struct r600_resource
*compute_scratch_buffer
;
579 /* Emitted derived tessellation state. */
580 /* Local shader (VS), or HS if LS-HS are merged. */
581 struct si_shader
*last_ls
;
582 struct si_shader_selector
*last_tcs
;
583 int last_num_tcs_input_cp
;
584 int last_tes_sh_base
;
585 bool last_tess_uses_primid
;
586 unsigned last_num_patches
;
590 struct si_saved_cs
*current_saved_cs
;
591 uint64_t dmesg_timestamp
;
592 unsigned apitrace_call_number
;
595 bool need_check_render_feedback
;
596 bool decompression_enabled
;
598 bool vs_writes_viewport_index
;
599 bool vs_disables_clipping_viewport
;
601 /* Precomputed IA_MULTI_VGT_PARAM */
602 union si_vgt_param_key ia_multi_vgt_param_key
;
603 unsigned ia_multi_vgt_param
[SI_NUM_VGT_PARAM_STATES
];
605 /* Bindless descriptors. */
606 struct si_descriptors bindless_descriptors
;
607 struct util_idalloc bindless_used_slots
;
608 unsigned num_bindless_descriptors
;
609 bool bindless_descriptors_dirty
;
610 bool graphics_bindless_pointer_dirty
;
611 bool compute_bindless_pointer_dirty
;
613 /* Allocated bindless handles */
614 struct hash_table
*tex_handles
;
615 struct hash_table
*img_handles
;
617 /* Resident bindless handles */
618 struct util_dynarray resident_tex_handles
;
619 struct util_dynarray resident_img_handles
;
621 /* Resident bindless handles which need decompression */
622 struct util_dynarray resident_tex_needs_color_decompress
;
623 struct util_dynarray resident_img_needs_color_decompress
;
624 struct util_dynarray resident_tex_needs_depth_decompress
;
627 bool uses_bindless_samplers
;
628 bool uses_bindless_images
;
630 /* MSAA sample locations.
631 * The first index is the sample index.
632 * The second index is the coordinate: X, Y. */
633 float sample_locations_1x
[1][2];
634 float sample_locations_2x
[2][2];
635 float sample_locations_4x
[4][2];
636 float sample_locations_8x
[8][2];
637 float sample_locations_16x
[16][2];
641 void cik_init_sdma_functions(struct si_context
*sctx
);
644 enum si_blitter_op
/* bitmask */
646 SI_SAVE_TEXTURES
= 1,
647 SI_SAVE_FRAMEBUFFER
= 2,
648 SI_SAVE_FRAGMENT_STATE
= 4,
649 SI_DISABLE_RENDER_COND
= 8,
652 void si_blitter_begin(struct pipe_context
*ctx
, enum si_blitter_op op
);
653 void si_blitter_end(struct pipe_context
*ctx
);
654 void si_init_blit_functions(struct si_context
*sctx
);
655 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
);
656 void si_resource_copy_region(struct pipe_context
*ctx
,
657 struct pipe_resource
*dst
,
659 unsigned dstx
, unsigned dsty
, unsigned dstz
,
660 struct pipe_resource
*src
,
662 const struct pipe_box
*src_box
);
663 void si_decompress_dcc(struct pipe_context
*ctx
, struct r600_texture
*rtex
);
666 void vi_dcc_clear_level(struct si_context
*sctx
,
667 struct r600_texture
*rtex
,
668 unsigned level
, unsigned clear_value
);
669 void si_init_clear_functions(struct si_context
*sctx
);
672 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
673 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
674 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
675 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
676 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
677 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
678 SI_CPDMA_SKIP_SYNC_AFTER | \
679 SI_CPDMA_SKIP_SYNC_BEFORE | \
680 SI_CPDMA_SKIP_GFX_SYNC | \
681 SI_CPDMA_SKIP_BO_LIST_UPDATE)
683 enum r600_coherency
{
684 R600_COHERENCY_NONE
, /* no cache flushes needed */
685 R600_COHERENCY_SHADER
,
686 R600_COHERENCY_CB_META
,
689 void si_clear_buffer(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
690 uint64_t offset
, uint64_t size
, unsigned value
,
691 enum r600_coherency coher
);
692 void si_copy_buffer(struct si_context
*sctx
,
693 struct pipe_resource
*dst
, struct pipe_resource
*src
,
694 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
,
695 unsigned user_flags
);
696 void cik_prefetch_TC_L2_async(struct si_context
*sctx
, struct pipe_resource
*buf
,
697 uint64_t offset
, unsigned size
);
698 void cik_emit_prefetch_L2(struct si_context
*sctx
);
699 void si_init_cp_dma_functions(struct si_context
*sctx
);
702 void si_auto_log_cs(void *data
, struct u_log_context
*log
);
703 void si_log_hw_flush(struct si_context
*sctx
);
704 void si_log_draw_state(struct si_context
*sctx
, struct u_log_context
*log
);
705 void si_log_compute_state(struct si_context
*sctx
, struct u_log_context
*log
);
706 void si_init_debug_functions(struct si_context
*sctx
);
707 void si_check_vm_faults(struct r600_common_context
*ctx
,
708 struct radeon_saved_cs
*saved
, enum ring_type ring
);
709 bool si_replace_shader(unsigned num
, struct ac_shader_binary
*binary
);
712 void si_init_dma_functions(struct si_context
*sctx
);
715 void si_init_fence_functions(struct si_context
*ctx
);
716 void si_init_screen_fence_functions(struct si_screen
*screen
);
717 struct pipe_fence_handle
*si_create_fence(struct pipe_context
*ctx
,
718 struct tc_unflushed_batch_token
*tc_token
);
721 const char *si_get_family_name(const struct si_screen
*sscreen
);
722 void si_init_screen_get_functions(struct si_screen
*sscreen
);
724 /* si_hw_context.c */
725 void si_destroy_saved_cs(struct si_saved_cs
*scs
);
726 void si_flush_gfx_cs(void *context
, unsigned flags
,
727 struct pipe_fence_handle
**fence
);
728 void si_begin_new_cs(struct si_context
*ctx
);
729 void si_need_cs_space(struct si_context
*ctx
);
732 void si_init_compute_functions(struct si_context
*sctx
);
734 /* si_perfcounters.c */
735 void si_init_perfcounters(struct si_screen
*screen
);
738 void si_test_dma(struct si_screen
*sscreen
);
741 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
742 const struct pipe_video_codec
*templ
);
744 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
745 const struct pipe_video_buffer
*tmpl
);
748 void si_update_vs_viewport_state(struct si_context
*ctx
);
749 void si_init_viewport_functions(struct si_context
*ctx
);
757 si_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
)
759 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
760 struct r600_resource
*res
= (struct r600_resource
*)r
;
763 /* Add memory usage for need_gfx_cs_space */
764 rctx
->vram
+= res
->vram_usage
;
765 rctx
->gtt
+= res
->gart_usage
;
770 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
772 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
776 si_set_atom_dirty(struct si_context
*sctx
,
777 struct r600_atom
*atom
, bool dirty
)
779 unsigned bit
= 1 << atom
->id
;
782 sctx
->dirty_atoms
|= bit
;
784 sctx
->dirty_atoms
&= ~bit
;
788 si_is_atom_dirty(struct si_context
*sctx
,
789 struct r600_atom
*atom
)
791 unsigned bit
= 1 << atom
->id
;
793 return sctx
->dirty_atoms
& bit
;
797 si_mark_atom_dirty(struct si_context
*sctx
,
798 struct r600_atom
*atom
)
800 si_set_atom_dirty(sctx
, atom
, true);
803 static inline struct si_shader_ctx_state
*si_get_vs(struct si_context
*sctx
)
805 if (sctx
->gs_shader
.cso
)
806 return &sctx
->gs_shader
;
807 if (sctx
->tes_shader
.cso
)
808 return &sctx
->tes_shader
;
810 return &sctx
->vs_shader
;
813 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
815 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
817 return vs
->cso
? &vs
->cso
->info
: NULL
;
820 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
822 if (sctx
->gs_shader
.cso
)
823 return sctx
->gs_shader
.cso
->gs_copy_shader
;
825 struct si_shader_ctx_state
*vs
= si_get_vs(sctx
);
826 return vs
->current
? vs
->current
: NULL
;
829 static inline bool si_can_dump_shader(struct si_screen
*sscreen
,
832 return sscreen
->debug_flags
& (1 << processor
);
835 static inline bool si_extra_shader_checks(struct si_screen
*sscreen
,
838 return (sscreen
->debug_flags
& DBG(CHECK_IR
)) ||
839 si_can_dump_shader(sscreen
, processor
);
842 static inline bool si_get_strmout_en(struct si_context
*sctx
)
844 return sctx
->streamout
.streamout_enabled
||
845 sctx
->streamout
.prims_gen_query_enabled
;
848 static inline unsigned
849 si_optimal_tcc_alignment(struct si_context
*sctx
, unsigned upload_size
)
851 unsigned alignment
, tcc_cache_line_size
;
853 /* If the upload size is less than the cache line size (e.g. 16, 32),
854 * the whole thing will fit into a cache line if we align it to its size.
855 * The idea is that multiple small uploads can share a cache line.
856 * If the upload size is greater, align it to the cache line size.
858 alignment
= util_next_power_of_two(upload_size
);
859 tcc_cache_line_size
= sctx
->screen
->info
.tcc_cache_line_size
;
860 return MIN2(alignment
, tcc_cache_line_size
);
864 si_saved_cs_reference(struct si_saved_cs
**dst
, struct si_saved_cs
*src
)
866 if (pipe_reference(&(*dst
)->reference
, &src
->reference
))
867 si_destroy_saved_cs(*dst
);
873 si_make_CB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
874 bool shaders_read_metadata
)
876 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
|
877 SI_CONTEXT_INV_VMEM_L1
;
879 if (sctx
->b
.chip_class
>= GFX9
) {
880 /* Single-sample color is coherent with shaders on GFX9, but
881 * L2 metadata must be flushed if shaders read metadata.
884 if (num_samples
>= 2)
885 sctx
->b
.flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
886 else if (shaders_read_metadata
)
887 sctx
->b
.flags
|= SI_CONTEXT_INV_L2_METADATA
;
890 sctx
->b
.flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
895 si_make_DB_shader_coherent(struct si_context
*sctx
, unsigned num_samples
,
896 bool include_stencil
, bool shaders_read_metadata
)
898 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_DB
|
899 SI_CONTEXT_INV_VMEM_L1
;
901 if (sctx
->b
.chip_class
>= GFX9
) {
902 /* Single-sample depth (not stencil) is coherent with shaders
903 * on GFX9, but L2 metadata must be flushed if shaders read
906 if (num_samples
>= 2 || include_stencil
)
907 sctx
->b
.flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
908 else if (shaders_read_metadata
)
909 sctx
->b
.flags
|= SI_CONTEXT_INV_L2_METADATA
;
912 sctx
->b
.flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
917 si_can_sample_zs(struct r600_texture
*tex
, bool stencil_sampler
)
919 return (stencil_sampler
&& tex
->can_sample_s
) ||
920 (!stencil_sampler
&& tex
->can_sample_z
);
924 si_htile_enabled(struct r600_texture
*tex
, unsigned level
)
926 return tex
->htile_offset
&& level
== 0;
930 vi_tc_compat_htile_enabled(struct r600_texture
*tex
, unsigned level
)
932 assert(!tex
->tc_compatible_htile
|| tex
->htile_offset
);
933 return tex
->tc_compatible_htile
&& level
== 0;
936 static inline unsigned si_get_ps_iter_samples(struct si_context
*sctx
)
938 if (sctx
->ps_uses_fbfetch
)
939 return sctx
->framebuffer
.nr_samples
;
941 return sctx
->ps_iter_samples
;
944 static inline unsigned si_get_total_colormask(struct si_context
*sctx
)
946 if (sctx
->queued
.named
.rasterizer
->rasterizer_discard
)
949 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
950 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
951 sctx
->queued
.named
.blend
->cb_target_mask
;
953 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
954 colormask
&= ps
->colors_written_4bit
;
955 else if (!ps
->colors_written_4bit
)
956 colormask
= 0; /* color0 writes all cbufs, but it's not written */