src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef SI_PIPE_H
  27 #define SI_PIPE_H
  28
  29 #include "si_shader.h"
  30
  31 #include "util/u_dynarray.h"
  32
  33 #ifdef PIPE_ARCH_BIG_ENDIAN
  34 #define SI_BIG_ENDIAN 1
  35 #else
  36 #define SI_BIG_ENDIAN 0
  37 #endif
  38
  39 /* The base vertex and primitive restart can be any number, but we must pick
  40  * one which will mean "unknown" for the purpose of state tracking and
  41  * the number shouldn't be a commonly-used one. */
  42 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  43 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  44 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  45 #define SI_GS_PER_ES 128
  46 /* Alignment for optimal CP DMA performance. */
  47 #define SI_CPDMA_ALIGNMENT      32
  48
  49 /* Instruction cache. */
  50 #define SI_CONTEXT_INV_ICACHE           (R600_CONTEXT_PRIVATE_FLAG << 0)
  51 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  52 #define SI_CONTEXT_INV_SMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 1)
  53 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  54 #define SI_CONTEXT_INV_VMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 2)
  55 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  56 #define SI_CONTEXT_INV_GLOBAL_L2        (R600_CONTEXT_PRIVATE_FLAG << 3)
  57 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  58  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
  59 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2  (R600_CONTEXT_PRIVATE_FLAG << 4)
  60 /* gaps */
  61 /* Framebuffer caches. */
  62 #define SI_CONTEXT_FLUSH_AND_INV_DB     (R600_CONTEXT_PRIVATE_FLAG << 7)
  63 #define SI_CONTEXT_FLUSH_AND_INV_CB     (R600_CONTEXT_PRIVATE_FLAG << 8)
  64 /* Engine synchronization. */
  65 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 9)
  66 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 10)
  67 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 11)
  68 #define SI_CONTEXT_VGT_FLUSH            (R600_CONTEXT_PRIVATE_FLAG << 12)
  69 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (R600_CONTEXT_PRIVATE_FLAG << 13)
  70
  71 #define SI_MAX_BORDER_COLORS    4096
  72 #define SIX_BITS                0x3F
  73
  74 struct si_compute;
  75 struct hash_table;
  76 struct u_suballocator;
  77
  78 struct si_screen {
  79         struct r600_common_screen       b;
  80         unsigned                        gs_table_depth;
  81         unsigned                        tess_offchip_block_dw_size;
  82         bool                            has_distributed_tess;
  83         bool                            has_draw_indirect_multi;
  84         bool                            has_ds_bpermute;
  85         bool                            has_msaa_sample_loc_bug;
  86         bool                            llvm_has_working_vgpr_indexing;
  87
  88         /* Whether shaders are monolithic (1-part) or separate (3-part). */
  89         bool                            use_monolithic_shaders;
  90         bool                            record_llvm_ir;
  91
  92         mtx_t                   shader_parts_mutex;
  93         struct si_shader_part           *vs_prologs;
  94         struct si_shader_part           *tcs_epilogs;
  95         struct si_shader_part           *gs_prologs;
  96         struct si_shader_part           *ps_prologs;
  97         struct si_shader_part           *ps_epilogs;
  98
  99         /* Shader cache in memory.
 100          *
 101          * Design & limitations:
 102          * - The shader cache is per screen (= per process), never saved to
 103          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 104          * - It can only be used with one-variant-per-shader support, in which
 105          *   case only the main (typically middle) part of shaders is cached.
 106          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 107          *   variants of VS and TES are cached, so LS and ES aren't.
 108          * - GS and CS aren't cached, but it's certainly possible to cache
 109          *   those as well.
 110          */
 111         mtx_t                   shader_cache_mutex;
 112         struct hash_table               *shader_cache;
 113
 114         /* Shader compiler queue for multithreaded compilation. */
 115         struct util_queue               shader_compiler_queue;
 116         LLVMTargetMachineRef            tm[4]; /* used by the queue only */
 117
 118         struct util_queue               shader_compiler_queue_low_priority;
 119         LLVMTargetMachineRef            tm_low_priority[4];
 120 };
 121
 122 struct si_blend_color {
 123         struct r600_atom                atom;
 124         struct pipe_blend_color         state;
 125 };
 126
 127 struct si_sampler_view {
 128         struct pipe_sampler_view        base;
 129         /* [0..7] = image descriptor
 130          * [4..7] = buffer descriptor */
 131         uint32_t                        state[8];
 132         uint32_t                        fmask_state[8];
 133         const struct legacy_surf_level  *base_level_info;
 134         ubyte                           base_level;
 135         ubyte                           block_width;
 136         bool is_stencil_sampler;
 137         bool dcc_incompatible;
 138 };
 139
 140 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
 141
 142 struct si_sampler_state {
 143 #ifdef DEBUG
 144         unsigned                        magic;
 145 #endif
 146         uint32_t                        val[4];
 147 };
 148
 149 struct si_cs_shader_state {
 150         struct si_compute               *program;
 151         struct si_compute               *emitted_program;
 152         unsigned                        offset;
 153         bool                            initialized;
 154         bool                            uses_scratch;
 155 };
 156
 157 struct si_textures_info {
 158         struct si_sampler_views         views;
 159         uint32_t                        needs_depth_decompress_mask;
 160         uint32_t                        needs_color_decompress_mask;
 161 };
 162
 163 struct si_images_info {
 164         struct pipe_image_view          views[SI_NUM_IMAGES];
 165         uint32_t                        needs_color_decompress_mask;
 166         unsigned                        enabled_mask;
 167 };
 168
 169 struct si_framebuffer {
 170         struct r600_atom                atom;
 171         struct pipe_framebuffer_state   state;
 172         unsigned                        colorbuf_enabled_4bit;
 173         unsigned                        spi_shader_col_format;
 174         unsigned                        spi_shader_col_format_alpha;
 175         unsigned                        spi_shader_col_format_blend;
 176         unsigned                        spi_shader_col_format_blend_alpha;
 177         ubyte                           nr_samples:5; /* at most 16xAA */
 178         ubyte                           log_samples:3; /* at most 4 = 16xAA */
 179         ubyte                           compressed_cb_mask;
 180         ubyte                           color_is_int8;
 181         ubyte                           color_is_int10;
 182         ubyte                           dirty_cbufs;
 183         bool                            dirty_zsbuf;
 184         bool                            any_dst_linear;
 185         bool                            do_update_surf_dirtiness;
 186 };
 187
 188 struct si_clip_state {
 189         struct r600_atom                atom;
 190         struct pipe_clip_state          state;
 191 };
 192
 193 struct si_sample_locs {
 194         struct r600_atom        atom;
 195         unsigned                nr_samples;
 196 };
 197
 198 struct si_sample_mask {
 199         struct r600_atom        atom;
 200         uint16_t                sample_mask;
 201 };
 202
 203 /* A shader state consists of the shader selector, which is a constant state
 204  * object shared by multiple contexts and shouldn't be modified, and
 205  * the current shader variant selected for this context.
 206  */
 207 struct si_shader_ctx_state {
 208         struct si_shader_selector       *cso;
 209         struct si_shader                *current;
 210 };
 211
 212 #define SI_NUM_VGT_PARAM_KEY_BITS 12
 213 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
 214
 215 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
 216  * Some fields are set by state-change calls, most are set by draw_vbo.
 217  */
 218 union si_vgt_param_key {
 219         struct {
 220                 unsigned prim:4;
 221                 unsigned uses_instancing:1;
 222                 unsigned multi_instances_smaller_than_primgroup:1;
 223                 unsigned primitive_restart:1;
 224                 unsigned count_from_stream_output:1;
 225                 unsigned line_stipple_enabled:1;
 226                 unsigned uses_tess:1;
 227                 unsigned tess_uses_prim_id:1;
 228                 unsigned uses_gs:1;
 229                 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
 230         } u;
 231         uint32_t index;
 232 };
 233
 234 struct si_bindless_descriptor
 235 {
 236         struct pb_slab_entry            entry;
 237         struct r600_resource            *buffer;
 238         unsigned                        offset;
 239         uint32_t                        desc_list[16];
 240         bool                            dirty;
 241 };
 242
 243 struct si_texture_handle
 244 {
 245         struct si_bindless_descriptor   *desc;
 246         struct pipe_sampler_view        *view;
 247         struct si_sampler_state         sstate;
 248 };
 249
 250 struct si_image_handle
 251 {
 252         struct si_bindless_descriptor   *desc;
 253         struct pipe_image_view          view;
 254 };
 255
 256 struct si_context {
 257         struct r600_common_context      b;
 258         struct blitter_context          *blitter;
 259         void                            *custom_dsa_flush;
 260         void                            *custom_blend_resolve;
 261         void                            *custom_blend_fmask_decompress;
 262         void                            *custom_blend_eliminate_fastclear;
 263         void                            *custom_blend_dcc_decompress;
 264         struct si_screen                *screen;
 265         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 266         struct si_shader_ctx_state      fixed_func_tcs_shader;
 267         struct r600_resource            *wait_mem_scratch;
 268         unsigned                        wait_mem_number;
 269
 270         struct radeon_winsys_cs         *ce_ib;
 271         struct radeon_winsys_cs         *ce_preamble_ib;
 272         struct r600_resource            *ce_ram_saved_buffer;
 273         struct u_suballocator           *ce_suballocator;
 274         unsigned                        ce_ram_saved_offset;
 275         uint16_t                        total_ce_ram_allocated;
 276         bool                            ce_need_synchronization:1;
 277
 278         bool                            gfx_flush_in_progress:1;
 279         bool                            compute_is_busy:1;
 280
 281         /* Atoms (direct states). */
 282         union si_state_atoms            atoms;
 283         unsigned                        dirty_atoms; /* mask */
 284         /* PM4 states (precomputed immutable states) */
 285         unsigned                        dirty_states;
 286         union si_state                  queued;
 287         union si_state                  emitted;
 288
 289         /* Atom declarations. */
 290         struct r600_atom                prefetch_L2;
 291         struct si_framebuffer           framebuffer;
 292         struct si_sample_locs           msaa_sample_locs;
 293         struct r600_atom                db_render_state;
 294         struct r600_atom                msaa_config;
 295         struct si_sample_mask           sample_mask;
 296         struct r600_atom                cb_render_state;
 297         unsigned                        last_cb_target_mask;
 298         struct si_blend_color           blend_color;
 299         struct r600_atom                clip_regs;
 300         struct si_clip_state            clip_state;
 301         struct si_shader_data           shader_userdata;
 302         struct si_stencil_ref           stencil_ref;
 303         struct r600_atom                spi_map;
 304
 305         /* Precomputed states. */
 306         struct si_pm4_state             *init_config;
 307         struct si_pm4_state             *init_config_gs_rings;
 308         bool                            init_config_has_vgt_flush;
 309         struct si_pm4_state             *vgt_shader_config[4];
 310
 311         /* shaders */
 312         struct si_shader_ctx_state      ps_shader;
 313         struct si_shader_ctx_state      gs_shader;
 314         struct si_shader_ctx_state      vs_shader;
 315         struct si_shader_ctx_state      tcs_shader;
 316         struct si_shader_ctx_state      tes_shader;
 317         struct si_cs_shader_state       cs_shader_state;
 318
 319         /* shader information */
 320         struct si_vertex_elements       *vertex_elements;
 321         unsigned                        sprite_coord_enable;
 322         bool                            flatshade;
 323         bool                            do_update_shaders;
 324
 325         /* shader descriptors */
 326         struct si_descriptors           vertex_buffers;
 327         struct si_descriptors           descriptors[SI_NUM_DESCS];
 328         unsigned                        descriptors_dirty;
 329         unsigned                        shader_pointers_dirty;
 330         unsigned                        shader_needs_decompress_mask;
 331         struct si_buffer_resources      rw_buffers;
 332         struct si_buffer_resources      const_and_shader_buffers[SI_NUM_SHADERS];
 333         struct si_textures_info         samplers[SI_NUM_SHADERS];
 334         struct si_images_info           images[SI_NUM_SHADERS];
 335
 336         /* other shader resources */
 337         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 338         struct pipe_resource            *esgs_ring;
 339         struct pipe_resource            *gsvs_ring;
 340         struct pipe_resource            *tf_ring;
 341         struct pipe_resource            *tess_offchip_ring;
 342         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 343         struct r600_resource            *border_color_buffer;
 344         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 345         unsigned                        border_color_count;
 346
 347         /* Vertex and index buffers. */
 348         bool                            vertex_buffers_dirty;
 349         bool                            vertex_buffer_pointer_dirty;
 350         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 351
 352         /* MSAA config state. */
 353         int                             ps_iter_samples;
 354         bool                            smoothing_enabled;
 355
 356         /* DB render state. */
 357         unsigned                ps_db_shader_control;
 358         unsigned                dbcb_copy_sample;
 359         bool                    dbcb_depth_copy_enabled:1;
 360         bool                    dbcb_stencil_copy_enabled:1;
 361         bool                    db_flush_depth_inplace:1;
 362         bool                    db_flush_stencil_inplace:1;
 363         bool                    db_depth_clear:1;
 364         bool                    db_depth_disable_expclear:1;
 365         bool                    db_stencil_clear:1;
 366         bool                    db_stencil_disable_expclear:1;
 367         bool                    occlusion_queries_disabled:1;
 368         bool                    generate_mipmap_for_depth:1;
 369
 370         /* Emitted draw state. */
 371         bool                    gs_tri_strip_adj_fix:1;
 372         int                     last_index_size;
 373         int                     last_base_vertex;
 374         int                     last_start_instance;
 375         int                     last_drawid;
 376         int                     last_sh_base_reg;
 377         int                     last_primitive_restart_en;
 378         int                     last_restart_index;
 379         int                     last_gs_out_prim;
 380         int                     last_prim;
 381         int                     last_multi_vgt_param;
 382         int                     last_rast_prim;
 383         unsigned                last_sc_line_stipple;
 384         unsigned                current_vs_state;
 385         unsigned                last_vs_state;
 386         enum pipe_prim_type     current_rast_prim; /* primitive type after TES, GS */
 387
 388         /* Scratch buffer */
 389         struct r600_atom        scratch_state;
 390         struct r600_resource    *scratch_buffer;
 391         unsigned                scratch_waves;
 392         unsigned                spi_tmpring_size;
 393
 394         struct r600_resource    *compute_scratch_buffer;
 395
 396         /* Emitted derived tessellation state. */
 397         /* Local shader (VS), or HS if LS-HS are merged. */
 398         struct si_shader        *last_ls;
 399         struct si_shader_selector *last_tcs;
 400         int                     last_num_tcs_input_cp;
 401         int                     last_tes_sh_base;
 402         bool                    last_tess_uses_primid;
 403         unsigned                last_num_patches;
 404
 405         /* Debug state. */
 406         bool                    is_debug;
 407         struct radeon_saved_cs  last_gfx;
 408         struct r600_resource    *last_trace_buf;
 409         struct r600_resource    *trace_buf;
 410         unsigned                trace_id;
 411         uint64_t                dmesg_timestamp;
 412         unsigned                apitrace_call_number;
 413
 414         /* Other state */
 415         bool need_check_render_feedback;
 416         bool                    decompression_enabled;
 417
 418         /* Precomputed IA_MULTI_VGT_PARAM */
 419         union si_vgt_param_key  ia_multi_vgt_param_key;
 420         unsigned                ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
 421
 422         /* Slab allocator for bindless descriptors. */
 423         struct pb_slabs         bindless_descriptor_slabs;
 424
 425         /* Bindless descriptors. */
 426         struct util_dynarray    bindless_descriptors;
 427         bool                    bindless_descriptors_dirty;
 428
 429         /* Allocated bindless handles */
 430         struct hash_table       *tex_handles;
 431         struct hash_table       *img_handles;
 432
 433         /* Resident bindless handles */
 434         struct util_dynarray    resident_tex_handles;
 435         struct util_dynarray    resident_img_handles;
 436
 437         /* Resident bindless handles which need decompression */
 438         struct util_dynarray    resident_tex_needs_color_decompress;
 439         struct util_dynarray    resident_img_needs_color_decompress;
 440         struct util_dynarray    resident_tex_needs_depth_decompress;
 441
 442         /* Bindless state */
 443         bool                    uses_bindless_samplers;
 444         bool                    uses_bindless_images;
 445 };
 446
 447 /* cik_sdma.c */
 448 void cik_init_sdma_functions(struct si_context *sctx);
 449
 450 /* si_blit.c */
 451 void si_init_blit_functions(struct si_context *sctx);
 452 void si_decompress_graphics_textures(struct si_context *sctx);
 453 void si_decompress_compute_textures(struct si_context *sctx);
 454 void si_resource_copy_region(struct pipe_context *ctx,
 455                              struct pipe_resource *dst,
 456                              unsigned dst_level,
 457                              unsigned dstx, unsigned dsty, unsigned dstz,
 458                              struct pipe_resource *src,
 459                              unsigned src_level,
 460                              const struct pipe_box *src_box);
 461
 462 /* si_cp_dma.c */
 463 #define SI_CPDMA_SKIP_CHECK_CS_SPACE    (1 << 0) /* don't call need_cs_space */
 464 #define SI_CPDMA_SKIP_SYNC_AFTER        (1 << 1) /* don't wait for DMA after the copy */
 465 #define SI_CPDMA_SKIP_SYNC_BEFORE       (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
 466 #define SI_CPDMA_SKIP_GFX_SYNC          (1 << 3) /* don't flush caches and don't wait for PS/CS */
 467 #define SI_CPDMA_SKIP_BO_LIST_UPDATE    (1 << 4) /* don't update the BO list */
 468 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
 469                            SI_CPDMA_SKIP_SYNC_AFTER | \
 470                            SI_CPDMA_SKIP_SYNC_BEFORE | \
 471                            SI_CPDMA_SKIP_GFX_SYNC | \
 472                            SI_CPDMA_SKIP_BO_LIST_UPDATE)
 473
 474 void si_copy_buffer(struct si_context *sctx,
 475                     struct pipe_resource *dst, struct pipe_resource *src,
 476                     uint64_t dst_offset, uint64_t src_offset, unsigned size,
 477                     unsigned user_flags);
 478 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 479                               uint64_t offset, unsigned size);
 480 void si_init_cp_dma_functions(struct si_context *sctx);
 481
 482 /* si_debug.c */
 483 void si_init_debug_functions(struct si_context *sctx);
 484 void si_check_vm_faults(struct r600_common_context *ctx,
 485                         struct radeon_saved_cs *saved, enum ring_type ring);
 486 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
 487
 488 /* si_dma.c */
 489 void si_init_dma_functions(struct si_context *sctx);
 490
 491 /* si_hw_context.c */
 492 void si_context_gfx_flush(void *context, unsigned flags,
 493                           struct pipe_fence_handle **fence);
 494 void si_begin_new_cs(struct si_context *ctx);
 495 void si_need_cs_space(struct si_context *ctx);
 496
 497 /* si_compute.c */
 498 void si_init_compute_functions(struct si_context *sctx);
 499
 500 /* si_perfcounters.c */
 501 void si_init_perfcounters(struct si_screen *screen);
 502
 503 /* si_uvd.c */
 504 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 505                                                const struct pipe_video_codec *templ);
 506
 507 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 508                                                  const struct pipe_video_buffer *tmpl);
 509
 510 /*
 511  * common helpers
 512  */
 513
 514 static inline void
 515 si_invalidate_draw_sh_constants(struct si_context *sctx)
 516 {
 517         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 518 }
 519
 520 static inline void
 521 si_set_atom_dirty(struct si_context *sctx,
 522                   struct r600_atom *atom, bool dirty)
 523 {
 524         unsigned bit = 1 << atom->id;
 525
 526         if (dirty)
 527                 sctx->dirty_atoms |= bit;
 528         else
 529                 sctx->dirty_atoms &= ~bit;
 530 }
 531
 532 static inline bool
 533 si_is_atom_dirty(struct si_context *sctx,
 534                   struct r600_atom *atom)
 535 {
 536         unsigned bit = 1 << atom->id;
 537
 538         return sctx->dirty_atoms & bit;
 539 }
 540
 541 static inline void
 542 si_mark_atom_dirty(struct si_context *sctx,
 543                    struct r600_atom *atom)
 544 {
 545         si_set_atom_dirty(sctx, atom, true);
 546 }
 547
 548 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
 549 {
 550         if (sctx->gs_shader.cso)
 551                 return &sctx->gs_shader;
 552         if (sctx->tes_shader.cso)
 553                 return &sctx->tes_shader;
 554
 555         return &sctx->vs_shader;
 556 }
 557
 558 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 559 {
 560         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 561
 562         return vs->cso ? &vs->cso->info : NULL;
 563 }
 564
 565 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 566 {
 567         if (sctx->gs_shader.cso)
 568                 return sctx->gs_shader.cso->gs_copy_shader;
 569
 570         struct si_shader_ctx_state *vs = si_get_vs(sctx);
 571         return vs->current ? vs->current : NULL;
 572 }
 573
 574 static inline unsigned
 575 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
 576 {
 577         unsigned alignment, tcc_cache_line_size;
 578
 579         /* If the upload size is less than the cache line size (e.g. 16, 32),
 580          * the whole thing will fit into a cache line if we align it to its size.
 581          * The idea is that multiple small uploads can share a cache line.
 582          * If the upload size is greater, align it to the cache line size.
 583          */
 584         alignment = util_next_power_of_two(upload_size);
 585         tcc_cache_line_size = sctx->screen->b.info.tcc_cache_line_size;
 586         return MIN2(alignment, tcc_cache_line_size);
 587 }
 588
 589 #endif