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ac: add has_ls_vgpr_init_bug to ac_gpu_info
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
34
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
37 #else
38 #define SI_BIG_ENDIAN 0
39 #endif
40
41 #define ATI_VENDOR_ID 0x1002
42 #define SI_PRIM_DISCARD_DEBUG 0
43 #define SI_NOT_QUERY 0xffffffff
44
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
56
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
61
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
69 * GFX10: This also invalidates the L1 shader array cache. */
70 #define SI_CONTEXT_INV_SCACHE (1 << 4)
71 /* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
72 * GFX10: This also invalidates the L1 shader array cache. */
73 #define SI_CONTEXT_INV_VCACHE (1 << 5)
74 /* L2 cache + L2 metadata cache writeback & invalidate.
75 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
76 #define SI_CONTEXT_INV_L2 (1 << 6)
77 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
78 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
79 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
80 #define SI_CONTEXT_WB_L2 (1 << 7)
81 /* Writeback & invalidate the L2 metadata cache only. It can only be coupled with
82 * a CB or DB flush. */
83 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
84 /* Framebuffer caches. */
85 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
86 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
87 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
88 /* Engine synchronization. */
89 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
90 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
91 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
92 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
93 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
94
95 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
96 #define SI_PREFETCH_LS (1 << 1)
97 #define SI_PREFETCH_HS (1 << 2)
98 #define SI_PREFETCH_ES (1 << 3)
99 #define SI_PREFETCH_GS (1 << 4)
100 #define SI_PREFETCH_VS (1 << 5)
101 #define SI_PREFETCH_PS (1 << 6)
102
103 #define SI_MAX_BORDER_COLORS 4096
104 #define SI_MAX_VIEWPORTS 16
105 #define SIX_BITS 0x3F
106 #define SI_MAP_BUFFER_ALIGNMENT 64
107 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
108
109 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
110 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
111 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
112 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
113 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
114 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
115 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
116 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
117 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
118 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
119
120 enum si_clear_code
121 {
122 DCC_CLEAR_COLOR_0000 = 0x00000000,
123 DCC_CLEAR_COLOR_0001 = 0x40404040,
124 DCC_CLEAR_COLOR_1110 = 0x80808080,
125 DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
126 DCC_CLEAR_COLOR_REG = 0x20202020,
127 DCC_UNCOMPRESSED = 0xFFFFFFFF,
128 };
129
130 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
131
132 /* Debug flags. */
133 enum {
134 /* Shader logging options: */
135 DBG_VS = PIPE_SHADER_VERTEX,
136 DBG_PS = PIPE_SHADER_FRAGMENT,
137 DBG_GS = PIPE_SHADER_GEOMETRY,
138 DBG_TCS = PIPE_SHADER_TESS_CTRL,
139 DBG_TES = PIPE_SHADER_TESS_EVAL,
140 DBG_CS = PIPE_SHADER_COMPUTE,
141 DBG_NO_IR,
142 DBG_NO_TGSI,
143 DBG_NO_ASM,
144 DBG_PREOPT_IR,
145
146 /* Shader compiler options the shader cache should be aware of: */
147 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
148 DBG_SI_SCHED,
149 DBG_GISEL,
150 DBG_W32_GE,
151 DBG_W32_PS,
152 DBG_W32_CS,
153 DBG_W64_GE,
154 DBG_W64_PS,
155 DBG_W64_CS,
156
157 /* Shader compiler options (with no effect on the shader cache): */
158 DBG_CHECK_IR,
159 DBG_MONOLITHIC_SHADERS,
160 DBG_NO_OPT_VARIANT,
161
162 /* Information logging options: */
163 DBG_INFO,
164 DBG_TEX,
165 DBG_COMPUTE,
166 DBG_VM,
167
168 /* Driver options: */
169 DBG_FORCE_DMA,
170 DBG_NO_ASYNC_DMA,
171 DBG_NO_WC,
172 DBG_CHECK_VM,
173 DBG_RESERVE_VMID,
174 DBG_ZERO_VRAM,
175
176 /* 3D engine options: */
177 DBG_NO_GFX,
178 DBG_ALWAYS_PD,
179 DBG_PD,
180 DBG_NO_PD,
181 DBG_SWITCH_ON_EOP,
182 DBG_NO_OUT_OF_ORDER,
183 DBG_NO_DPBB,
184 DBG_NO_DFSM,
185 DBG_DPBB,
186 DBG_DFSM,
187 DBG_NO_HYPERZ,
188 DBG_NO_RB_PLUS,
189 DBG_NO_2D_TILING,
190 DBG_NO_TILING,
191 DBG_NO_DCC,
192 DBG_NO_DCC_CLEAR,
193 DBG_NO_DCC_FB,
194 DBG_NO_DCC_MSAA,
195 DBG_NO_FMASK,
196
197 /* Tests: */
198 DBG_TEST_DMA,
199 DBG_TEST_VMFAULT_CP,
200 DBG_TEST_VMFAULT_SDMA,
201 DBG_TEST_VMFAULT_SHADER,
202 DBG_TEST_DMA_PERF,
203 DBG_TEST_GDS,
204 DBG_TEST_GDS_MM,
205 DBG_TEST_GDS_OA_MM,
206 };
207
208 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
209 #define DBG(name) (1ull << DBG_##name)
210
211 enum si_cache_policy {
212 L2_BYPASS,
213 L2_STREAM, /* same as SLC=1 */
214 L2_LRU, /* same as SLC=0 */
215 };
216
217 enum si_coherency {
218 SI_COHERENCY_NONE, /* no cache flushes needed */
219 SI_COHERENCY_SHADER,
220 SI_COHERENCY_CB_META,
221 SI_COHERENCY_CP,
222 };
223
224 struct si_compute;
225 struct si_shader_context;
226 struct hash_table;
227 struct u_suballocator;
228
229 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
230 * at the moment.
231 */
232 struct si_resource {
233 struct threaded_resource b;
234
235 /* Winsys objects. */
236 struct pb_buffer *buf;
237 uint64_t gpu_address;
238 /* Memory usage if the buffer placement is optimal. */
239 uint64_t vram_usage;
240 uint64_t gart_usage;
241
242 /* Resource properties. */
243 uint64_t bo_size;
244 unsigned bo_alignment;
245 enum radeon_bo_domain domains;
246 enum radeon_bo_flag flags;
247 unsigned bind_history;
248 int max_forced_staging_uploads;
249
250 /* The buffer range which is initialized (with a write transfer,
251 * streamout, DMA, or as a random access target). The rest of
252 * the buffer is considered invalid and can be mapped unsynchronized.
253 *
254 * This allows unsychronized mapping of a buffer range which hasn't
255 * been used yet. It's for applications which forget to use
256 * the unsynchronized map flag and expect the driver to figure it out.
257 */
258 struct util_range valid_buffer_range;
259
260 /* For buffers only. This indicates that a write operation has been
261 * performed by TC L2, but the cache hasn't been flushed.
262 * Any hw block which doesn't use or bypasses TC L2 should check this
263 * flag and flush the cache before using the buffer.
264 *
265 * For example, TC L2 must be flushed if a buffer which has been
266 * modified by a shader store instruction is about to be used as
267 * an index buffer. The reason is that VGT DMA index fetching doesn't
268 * use TC L2.
269 */
270 bool TC_L2_dirty;
271
272 /* Whether this resource is referenced by bindless handles. */
273 bool texture_handle_allocated;
274 bool image_handle_allocated;
275
276 /* Whether the resource has been exported via resource_get_handle. */
277 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
278 };
279
280 struct si_transfer {
281 struct threaded_transfer b;
282 struct si_resource *staging;
283 unsigned offset;
284 };
285
286 struct si_texture {
287 struct si_resource buffer;
288
289 struct radeon_surf surface;
290 uint64_t size;
291 struct si_texture *flushed_depth_texture;
292
293 /* One texture allocation can contain these buffers:
294 * - image (pixel data)
295 * - FMASK buffer (MSAA compression)
296 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
297 * - HTILE buffer (Z/S compression and fast Z/S clear)
298 * - DCC buffer (color compression and new fast color clear)
299 * - displayable DCC buffer (if the DCC buffer is not displayable)
300 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
301 */
302 uint64_t fmask_offset;
303 uint64_t cmask_offset;
304 uint64_t cmask_base_address_reg;
305 struct si_resource *cmask_buffer;
306 uint64_t dcc_offset; /* 0 = disabled */
307 uint64_t display_dcc_offset;
308 uint64_t dcc_retile_map_offset;
309 unsigned cb_color_info; /* fast clear enable bit */
310 unsigned color_clear_value[2];
311 unsigned last_msaa_resolve_target_micro_mode;
312 unsigned num_level0_transfers;
313
314 /* Depth buffer compression and fast clear. */
315 uint64_t htile_offset;
316 float depth_clear_value;
317 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
318 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
319 enum pipe_format db_render_format:16;
320 uint8_t stencil_clear_value;
321 bool tc_compatible_htile:1;
322 bool htile_stencil_disabled:1;
323 bool depth_cleared:1; /* if it was cleared at least once */
324 bool stencil_cleared:1; /* if it was cleared at least once */
325 bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
326 bool is_depth:1;
327 bool db_compatible:1;
328 bool can_sample_z:1;
329 bool can_sample_s:1;
330
331 /* We need to track DCC dirtiness, because st/dri usually calls
332 * flush_resource twice per frame (not a bug) and we don't wanna
333 * decompress DCC twice. Also, the dirty tracking must be done even
334 * if DCC isn't used, because it's required by the DCC usage analysis
335 * for a possible future enablement.
336 */
337 bool separate_dcc_dirty:1;
338 /* Statistics gathering for the DCC enablement heuristic. */
339 bool dcc_gather_statistics:1;
340 /* Counter that should be non-zero if the texture is bound to a
341 * framebuffer.
342 */
343 unsigned framebuffers_bound;
344 /* Whether the texture is a displayable back buffer and needs DCC
345 * decompression, which is expensive. Therefore, it's enabled only
346 * if statistics suggest that it will pay off and it's allocated
347 * separately. It can't be bound as a sampler by apps. Limited to
348 * target == 2D and last_level == 0. If enabled, dcc_offset contains
349 * the absolute GPUVM address, not the relative one.
350 */
351 struct si_resource *dcc_separate_buffer;
352 /* When DCC is temporarily disabled, the separate buffer is here. */
353 struct si_resource *last_dcc_separate_buffer;
354 /* Estimate of how much this color buffer is written to in units of
355 * full-screen draws: ps_invocations / (width * height)
356 * Shader kills, late Z, and blending with trivial discards make it
357 * inaccurate (we need to count CB updates, not PS invocations).
358 */
359 unsigned ps_draw_ratio;
360 /* The number of clears since the last DCC usage analysis. */
361 unsigned num_slow_clears;
362 };
363
364 struct si_surface {
365 struct pipe_surface base;
366
367 /* These can vary with block-compressed textures. */
368 uint16_t width0;
369 uint16_t height0;
370
371 bool color_initialized:1;
372 bool depth_initialized:1;
373
374 /* Misc. color flags. */
375 bool color_is_int8:1;
376 bool color_is_int10:1;
377 bool dcc_incompatible:1;
378
379 /* Color registers. */
380 unsigned cb_color_info;
381 unsigned cb_color_view;
382 unsigned cb_color_attrib;
383 unsigned cb_color_attrib2; /* GFX9 and later */
384 unsigned cb_color_attrib3; /* GFX10 and later */
385 unsigned cb_dcc_control; /* GFX8 and later */
386 unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */
387 unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
388 unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
389 unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
390
391 /* DB registers. */
392 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
393 uint64_t db_stencil_base;
394 uint64_t db_htile_data_base;
395 unsigned db_depth_info;
396 unsigned db_z_info;
397 unsigned db_z_info2; /* GFX9 only */
398 unsigned db_depth_view;
399 unsigned db_depth_size;
400 unsigned db_depth_slice;
401 unsigned db_stencil_info;
402 unsigned db_stencil_info2; /* GFX9 only */
403 unsigned db_htile_surface;
404 };
405
406 struct si_mmio_counter {
407 unsigned busy;
408 unsigned idle;
409 };
410
411 union si_mmio_counters {
412 struct {
413 /* For global GPU load including SDMA. */
414 struct si_mmio_counter gpu;
415
416 /* GRBM_STATUS */
417 struct si_mmio_counter spi;
418 struct si_mmio_counter gui;
419 struct si_mmio_counter ta;
420 struct si_mmio_counter gds;
421 struct si_mmio_counter vgt;
422 struct si_mmio_counter ia;
423 struct si_mmio_counter sx;
424 struct si_mmio_counter wd;
425 struct si_mmio_counter bci;
426 struct si_mmio_counter sc;
427 struct si_mmio_counter pa;
428 struct si_mmio_counter db;
429 struct si_mmio_counter cp;
430 struct si_mmio_counter cb;
431
432 /* SRBM_STATUS2 */
433 struct si_mmio_counter sdma;
434
435 /* CP_STAT */
436 struct si_mmio_counter pfp;
437 struct si_mmio_counter meq;
438 struct si_mmio_counter me;
439 struct si_mmio_counter surf_sync;
440 struct si_mmio_counter cp_dma;
441 struct si_mmio_counter scratch_ram;
442 } named;
443 unsigned array[0];
444 };
445
446 struct si_memory_object {
447 struct pipe_memory_object b;
448 struct pb_buffer *buf;
449 uint32_t stride;
450 };
451
452 /* Saved CS data for debugging features. */
453 struct radeon_saved_cs {
454 uint32_t *ib;
455 unsigned num_dw;
456
457 struct radeon_bo_list_item *bo_list;
458 unsigned bo_count;
459 };
460
461 struct si_screen {
462 struct pipe_screen b;
463 struct radeon_winsys *ws;
464 struct disk_cache *disk_shader_cache;
465
466 struct radeon_info info;
467 uint64_t debug_flags;
468 char renderer_string[183];
469
470 void (*make_texture_descriptor)(
471 struct si_screen *screen,
472 struct si_texture *tex,
473 bool sampler,
474 enum pipe_texture_target target,
475 enum pipe_format pipe_format,
476 const unsigned char state_swizzle[4],
477 unsigned first_level, unsigned last_level,
478 unsigned first_layer, unsigned last_layer,
479 unsigned width, unsigned height, unsigned depth,
480 uint32_t *state,
481 uint32_t *fmask_state);
482
483 unsigned pa_sc_raster_config;
484 unsigned pa_sc_raster_config_1;
485 unsigned se_tile_repeat;
486 unsigned gs_table_depth;
487 unsigned tess_offchip_block_dw_size;
488 unsigned tess_offchip_ring_size;
489 unsigned tess_factor_ring_size;
490 unsigned vgt_hs_offchip_param;
491 unsigned eqaa_force_coverage_samples;
492 unsigned eqaa_force_z_samples;
493 unsigned eqaa_force_color_samples;
494 bool has_draw_indirect_multi;
495 bool has_out_of_order_rast;
496 bool assume_no_z_fights;
497 bool commutative_blend_add;
498 bool dpbb_allowed;
499 bool dfsm_allowed;
500 bool llvm_has_working_vgpr_indexing;
501 bool use_ngg;
502 bool use_ngg_streamout;
503
504 struct {
505 #define OPT_BOOL(name, dflt, description) bool name:1;
506 #include "si_debug_options.h"
507 } options;
508
509 /* Whether shaders are monolithic (1-part) or separate (3-part). */
510 bool use_monolithic_shaders;
511 bool record_llvm_ir;
512 bool dcc_msaa_allowed;
513
514 struct slab_parent_pool pool_transfers;
515
516 /* Texture filter settings. */
517 int force_aniso; /* -1 = disabled */
518
519 /* Auxiliary context. Mainly used to initialize resources.
520 * It must be locked prior to using and flushed before unlocking. */
521 struct pipe_context *aux_context;
522 mtx_t aux_context_lock;
523
524 /* This must be in the screen, because UE4 uses one context for
525 * compilation and another one for rendering.
526 */
527 unsigned num_compilations;
528 /* Along with ST_DEBUG=precompile, this should show if applications
529 * are loading shaders on demand. This is a monotonic counter.
530 */
531 unsigned num_shaders_created;
532 unsigned num_shader_cache_hits;
533
534 /* GPU load thread. */
535 mtx_t gpu_load_mutex;
536 thrd_t gpu_load_thread;
537 union si_mmio_counters mmio_counters;
538 volatile unsigned gpu_load_stop_thread; /* bool */
539
540 /* Performance counters. */
541 struct si_perfcounters *perfcounters;
542
543 /* If pipe_screen wants to recompute and re-emit the framebuffer,
544 * sampler, and image states of all contexts, it should atomically
545 * increment this.
546 *
547 * Each context will compare this with its own last known value of
548 * the counter before drawing and re-emit the states accordingly.
549 */
550 unsigned dirty_tex_counter;
551 unsigned dirty_buf_counter;
552
553 /* Atomically increment this counter when an existing texture's
554 * metadata is enabled or disabled in a way that requires changing
555 * contexts' compressed texture binding masks.
556 */
557 unsigned compressed_colortex_counter;
558
559 struct {
560 /* Context flags to set so that all writes from earlier jobs
561 * in the CP are seen by L2 clients.
562 */
563 unsigned cp_to_L2;
564
565 /* Context flags to set so that all writes from earlier jobs
566 * that end in L2 are seen by CP.
567 */
568 unsigned L2_to_cp;
569 } barrier_flags;
570
571 mtx_t shader_parts_mutex;
572 struct si_shader_part *vs_prologs;
573 struct si_shader_part *tcs_epilogs;
574 struct si_shader_part *gs_prologs;
575 struct si_shader_part *ps_prologs;
576 struct si_shader_part *ps_epilogs;
577
578 /* Shader cache in memory.
579 *
580 * Design & limitations:
581 * - The shader cache is per screen (= per process), never saved to
582 * disk, and skips redundant shader compilations from TGSI to bytecode.
583 * - It can only be used with one-variant-per-shader support, in which
584 * case only the main (typically middle) part of shaders is cached.
585 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
586 * variants of VS and TES are cached, so LS and ES aren't.
587 * - GS and CS aren't cached, but it's certainly possible to cache
588 * those as well.
589 */
590 mtx_t shader_cache_mutex;
591 struct hash_table *shader_cache;
592
593 /* Shader compiler queue for multithreaded compilation. */
594 struct util_queue shader_compiler_queue;
595 /* Use at most 3 normal compiler threads on quadcore and better.
596 * Hyperthreaded CPUs report the number of threads, but we want
597 * the number of cores. We only need this many threads for shader-db. */
598 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
599
600 struct util_queue shader_compiler_queue_low_priority;
601 /* Use at most 2 low priority threads on quadcore and better.
602 * We want to minimize the impact on multithreaded Mesa. */
603 struct ac_llvm_compiler compiler_lowp[10];
604
605 unsigned compute_wave_size;
606 unsigned ps_wave_size;
607 unsigned ge_wave_size;
608 };
609
610 struct si_blend_color {
611 struct pipe_blend_color state;
612 bool any_nonzeros;
613 };
614
615 struct si_sampler_view {
616 struct pipe_sampler_view base;
617 /* [0..7] = image descriptor
618 * [4..7] = buffer descriptor */
619 uint32_t state[8];
620 uint32_t fmask_state[8];
621 const struct legacy_surf_level *base_level_info;
622 ubyte base_level;
623 ubyte block_width;
624 bool is_stencil_sampler;
625 bool is_integer;
626 bool dcc_incompatible;
627 };
628
629 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
630
631 struct si_sampler_state {
632 #ifndef NDEBUG
633 unsigned magic;
634 #endif
635 uint32_t val[4];
636 uint32_t integer_val[4];
637 uint32_t upgraded_depth_val[4];
638 };
639
640 struct si_cs_shader_state {
641 struct si_compute *program;
642 struct si_compute *emitted_program;
643 unsigned offset;
644 bool initialized;
645 bool uses_scratch;
646 };
647
648 struct si_samplers {
649 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
650 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
651
652 /* The i-th bit is set if that element is enabled (non-NULL resource). */
653 unsigned enabled_mask;
654 uint32_t needs_depth_decompress_mask;
655 uint32_t needs_color_decompress_mask;
656 };
657
658 struct si_images {
659 struct pipe_image_view views[SI_NUM_IMAGES];
660 uint32_t needs_color_decompress_mask;
661 unsigned enabled_mask;
662 };
663
664 struct si_framebuffer {
665 struct pipe_framebuffer_state state;
666 unsigned colorbuf_enabled_4bit;
667 unsigned spi_shader_col_format;
668 unsigned spi_shader_col_format_alpha;
669 unsigned spi_shader_col_format_blend;
670 unsigned spi_shader_col_format_blend_alpha;
671 ubyte nr_samples:5; /* at most 16xAA */
672 ubyte log_samples:3; /* at most 4 = 16xAA */
673 ubyte nr_color_samples; /* at most 8xAA */
674 ubyte compressed_cb_mask;
675 ubyte uncompressed_cb_mask;
676 ubyte color_is_int8;
677 ubyte color_is_int10;
678 ubyte dirty_cbufs;
679 ubyte dcc_overwrite_combiner_watermark;
680 ubyte min_bytes_per_pixel;
681 bool dirty_zsbuf;
682 bool any_dst_linear;
683 bool CB_has_shader_readable_metadata;
684 bool DB_has_shader_readable_metadata;
685 bool all_DCC_pipe_aligned;
686 };
687
688 enum si_quant_mode {
689 /* This is the list we want to support. */
690 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
691 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
692 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
693 };
694
695 struct si_signed_scissor {
696 int minx;
697 int miny;
698 int maxx;
699 int maxy;
700 enum si_quant_mode quant_mode;
701 };
702
703 struct si_viewports {
704 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
705 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
706 bool y_inverted;
707 };
708
709 struct si_clip_state {
710 struct pipe_clip_state state;
711 bool any_nonzeros;
712 };
713
714 struct si_streamout_target {
715 struct pipe_stream_output_target b;
716
717 /* The buffer where BUFFER_FILLED_SIZE is stored. */
718 struct si_resource *buf_filled_size;
719 unsigned buf_filled_size_offset;
720 bool buf_filled_size_valid;
721
722 unsigned stride_in_dw;
723 };
724
725 struct si_streamout {
726 bool begin_emitted;
727
728 unsigned enabled_mask;
729 unsigned num_targets;
730 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
731
732 unsigned append_bitmask;
733 bool suspended;
734
735 /* External state which comes from the vertex shader,
736 * it must be set explicitly when binding a shader. */
737 uint16_t *stride_in_dw;
738 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
739
740 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
741 unsigned hw_enabled_mask;
742
743 /* The state of VGT_STRMOUT_(CONFIG|EN). */
744 bool streamout_enabled;
745 bool prims_gen_query_enabled;
746 int num_prims_gen_queries;
747 };
748
749 /* A shader state consists of the shader selector, which is a constant state
750 * object shared by multiple contexts and shouldn't be modified, and
751 * the current shader variant selected for this context.
752 */
753 struct si_shader_ctx_state {
754 struct si_shader_selector *cso;
755 struct si_shader *current;
756 };
757
758 #define SI_NUM_VGT_PARAM_KEY_BITS 12
759 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
760
761 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
762 * Some fields are set by state-change calls, most are set by draw_vbo.
763 */
764 union si_vgt_param_key {
765 struct {
766 #ifdef PIPE_ARCH_LITTLE_ENDIAN
767 unsigned prim:4;
768 unsigned uses_instancing:1;
769 unsigned multi_instances_smaller_than_primgroup:1;
770 unsigned primitive_restart:1;
771 unsigned count_from_stream_output:1;
772 unsigned line_stipple_enabled:1;
773 unsigned uses_tess:1;
774 unsigned tess_uses_prim_id:1;
775 unsigned uses_gs:1;
776 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
777 #else /* PIPE_ARCH_BIG_ENDIAN */
778 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
779 unsigned uses_gs:1;
780 unsigned tess_uses_prim_id:1;
781 unsigned uses_tess:1;
782 unsigned line_stipple_enabled:1;
783 unsigned count_from_stream_output:1;
784 unsigned primitive_restart:1;
785 unsigned multi_instances_smaller_than_primgroup:1;
786 unsigned uses_instancing:1;
787 unsigned prim:4;
788 #endif
789 } u;
790 uint32_t index;
791 };
792
793 #define SI_NUM_VGT_STAGES_KEY_BITS 4
794 #define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS)
795
796 /* The VGT_SHADER_STAGES key used to index the table of precomputed values.
797 * Some fields are set by state-change calls, most are set by draw_vbo.
798 */
799 union si_vgt_stages_key {
800 struct {
801 #ifdef PIPE_ARCH_LITTLE_ENDIAN
802 unsigned tess:1;
803 unsigned gs:1;
804 unsigned ngg:1; /* gfx10+ */
805 unsigned streamout:1; /* only used with NGG */
806 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
807 #else /* PIPE_ARCH_BIG_ENDIAN */
808 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
809 unsigned streamout:1;
810 unsigned ngg:1;
811 unsigned gs:1;
812 unsigned tess:1;
813 #endif
814 } u;
815 uint32_t index;
816 };
817
818 struct si_texture_handle
819 {
820 unsigned desc_slot;
821 bool desc_dirty;
822 struct pipe_sampler_view *view;
823 struct si_sampler_state sstate;
824 };
825
826 struct si_image_handle
827 {
828 unsigned desc_slot;
829 bool desc_dirty;
830 struct pipe_image_view view;
831 };
832
833 struct si_saved_cs {
834 struct pipe_reference reference;
835 struct si_context *ctx;
836 struct radeon_saved_cs gfx;
837 struct radeon_saved_cs compute;
838 struct si_resource *trace_buf;
839 unsigned trace_id;
840
841 unsigned gfx_last_dw;
842 unsigned compute_last_dw;
843 bool flushed;
844 int64_t time_flush;
845 };
846
847 struct si_sdma_upload {
848 struct si_resource *dst;
849 struct si_resource *src;
850 unsigned src_offset;
851 unsigned dst_offset;
852 unsigned size;
853 };
854
855 struct si_context {
856 struct pipe_context b; /* base class */
857
858 enum radeon_family family;
859 enum chip_class chip_class;
860
861 struct radeon_winsys *ws;
862 struct radeon_winsys_ctx *ctx;
863 struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
864 struct radeon_cmdbuf *dma_cs;
865 struct pipe_fence_handle *last_gfx_fence;
866 struct pipe_fence_handle *last_sdma_fence;
867 struct si_resource *eop_bug_scratch;
868 struct u_upload_mgr *cached_gtt_allocator;
869 struct threaded_context *tc;
870 struct u_suballocator *allocator_zeroed_memory;
871 struct slab_child_pool pool_transfers;
872 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
873 struct pipe_device_reset_callback device_reset_callback;
874 struct u_log_context *log;
875 void *query_result_shader;
876 void *sh_query_result_shader;
877
878 void (*emit_cache_flush)(struct si_context *ctx);
879
880 struct blitter_context *blitter;
881 void *noop_blend;
882 void *noop_dsa;
883 void *discard_rasterizer_state;
884 void *custom_dsa_flush;
885 void *custom_blend_resolve;
886 void *custom_blend_fmask_decompress;
887 void *custom_blend_eliminate_fastclear;
888 void *custom_blend_dcc_decompress;
889 void *vs_blit_pos;
890 void *vs_blit_pos_layered;
891 void *vs_blit_color;
892 void *vs_blit_color_layered;
893 void *vs_blit_texcoord;
894 void *cs_clear_buffer;
895 void *cs_copy_buffer;
896 void *cs_copy_image;
897 void *cs_copy_image_1d_array;
898 void *cs_clear_render_target;
899 void *cs_clear_render_target_1d_array;
900 void *cs_dcc_retile;
901 struct si_screen *screen;
902 struct pipe_debug_callback debug;
903 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
904 struct si_shader_ctx_state fixed_func_tcs_shader;
905 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
906 struct si_resource *wait_mem_scratch;
907 unsigned wait_mem_number;
908 uint16_t prefetch_L2_mask;
909
910 bool has_graphics;
911 bool gfx_flush_in_progress:1;
912 bool gfx_last_ib_is_busy:1;
913 bool compute_is_busy:1;
914
915 unsigned num_gfx_cs_flushes;
916 unsigned initial_gfx_cs_size;
917 unsigned last_dirty_tex_counter;
918 unsigned last_dirty_buf_counter;
919 unsigned last_compressed_colortex_counter;
920 unsigned last_num_draw_calls;
921 unsigned flags; /* flush flags */
922 /* Current unaccounted memory usage. */
923 uint64_t vram;
924 uint64_t gtt;
925
926 /* Compute-based primitive discard. */
927 unsigned prim_discard_vertex_count_threshold;
928 struct pb_buffer *gds;
929 struct pb_buffer *gds_oa;
930 struct radeon_cmdbuf *prim_discard_compute_cs;
931 unsigned compute_gds_offset;
932 struct si_shader *compute_ib_last_shader;
933 uint32_t compute_rewind_va;
934 unsigned compute_num_prims_in_batch;
935 bool preserve_prim_restart_gds_at_flush;
936 /* index_ring is divided into 2 halves for doublebuffering. */
937 struct si_resource *index_ring;
938 unsigned index_ring_base; /* offset of a per-IB portion */
939 unsigned index_ring_offset; /* offset within a per-IB portion */
940 unsigned index_ring_size_per_ib; /* max available size per IB */
941 bool prim_discard_compute_ib_initialized;
942 /* For tracking the last execution barrier - it can be either
943 * a WRITE_DATA packet or a fence. */
944 uint32_t *last_pkt3_write_data;
945 struct si_resource *barrier_buf;
946 unsigned barrier_buf_offset;
947 struct pipe_fence_handle *last_ib_barrier_fence;
948 struct si_resource *last_ib_barrier_buf;
949 unsigned last_ib_barrier_buf_offset;
950
951 /* Atoms (direct states). */
952 union si_state_atoms atoms;
953 unsigned dirty_atoms; /* mask */
954 /* PM4 states (precomputed immutable states) */
955 unsigned dirty_states;
956 union si_state queued;
957 union si_state emitted;
958
959 /* Atom declarations. */
960 struct si_framebuffer framebuffer;
961 unsigned sample_locs_num_samples;
962 uint16_t sample_mask;
963 unsigned last_cb_target_mask;
964 struct si_blend_color blend_color;
965 struct si_clip_state clip_state;
966 struct si_shader_data shader_pointers;
967 struct si_stencil_ref stencil_ref;
968 struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
969 struct si_streamout streamout;
970 struct si_viewports viewports;
971 unsigned num_window_rectangles;
972 bool window_rectangles_include;
973 struct pipe_scissor_state window_rectangles[4];
974
975 /* Precomputed states. */
976 struct si_pm4_state *init_config;
977 struct si_pm4_state *init_config_gs_rings;
978 bool init_config_has_vgt_flush;
979 struct si_pm4_state *vgt_shader_config[SI_NUM_VGT_STAGES_STATES];
980
981 /* shaders */
982 struct si_shader_ctx_state ps_shader;
983 struct si_shader_ctx_state gs_shader;
984 struct si_shader_ctx_state vs_shader;
985 struct si_shader_ctx_state tcs_shader;
986 struct si_shader_ctx_state tes_shader;
987 struct si_shader_ctx_state cs_prim_discard_state;
988 struct si_cs_shader_state cs_shader_state;
989
990 /* shader information */
991 struct si_vertex_elements *vertex_elements;
992 unsigned sprite_coord_enable;
993 unsigned cs_max_waves_per_sh;
994 bool flatshade;
995 bool do_update_shaders;
996
997 /* vertex buffer descriptors */
998 uint32_t *vb_descriptors_gpu_list;
999 struct si_resource *vb_descriptors_buffer;
1000 unsigned vb_descriptors_offset;
1001
1002 /* shader descriptors */
1003 struct si_descriptors descriptors[SI_NUM_DESCS];
1004 unsigned descriptors_dirty;
1005 unsigned shader_pointers_dirty;
1006 unsigned shader_needs_decompress_mask;
1007 struct si_buffer_resources rw_buffers;
1008 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
1009 struct si_samplers samplers[SI_NUM_SHADERS];
1010 struct si_images images[SI_NUM_SHADERS];
1011 bool bo_list_add_all_resident_resources;
1012 bool bo_list_add_all_gfx_resources;
1013 bool bo_list_add_all_compute_resources;
1014
1015 /* other shader resources */
1016 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */
1017 struct pipe_resource *esgs_ring;
1018 struct pipe_resource *gsvs_ring;
1019 struct pipe_resource *tess_rings;
1020 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
1021 struct si_resource *border_color_buffer;
1022 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
1023 unsigned border_color_count;
1024 unsigned num_vs_blit_sgprs;
1025 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
1026 uint32_t cs_user_data[4];
1027
1028 /* Vertex and index buffers. */
1029 bool vertex_buffers_dirty;
1030 bool vertex_buffer_pointer_dirty;
1031 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
1032 uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
1033
1034 /* MSAA config state. */
1035 int ps_iter_samples;
1036 bool ps_uses_fbfetch;
1037 bool smoothing_enabled;
1038
1039 /* DB render state. */
1040 unsigned ps_db_shader_control;
1041 unsigned dbcb_copy_sample;
1042 bool dbcb_depth_copy_enabled:1;
1043 bool dbcb_stencil_copy_enabled:1;
1044 bool db_flush_depth_inplace:1;
1045 bool db_flush_stencil_inplace:1;
1046 bool db_depth_clear:1;
1047 bool db_depth_disable_expclear:1;
1048 bool db_stencil_clear:1;
1049 bool db_stencil_disable_expclear:1;
1050 bool occlusion_queries_disabled:1;
1051 bool generate_mipmap_for_depth:1;
1052
1053 /* Emitted draw state. */
1054 bool gs_tri_strip_adj_fix:1;
1055 bool ls_vgpr_fix:1;
1056 bool prim_discard_cs_instancing:1;
1057 bool ngg:1;
1058 int last_index_size;
1059 int last_base_vertex;
1060 int last_start_instance;
1061 int last_instance_count;
1062 int last_drawid;
1063 int last_sh_base_reg;
1064 int last_primitive_restart_en;
1065 int last_restart_index;
1066 int last_prim;
1067 int last_multi_vgt_param;
1068 int last_rast_prim;
1069 int last_flatshade_first;
1070 int last_binning_enabled;
1071 unsigned last_sc_line_stipple;
1072 unsigned current_vs_state;
1073 unsigned last_vs_state;
1074 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
1075
1076 /* Scratch buffer */
1077 struct si_resource *scratch_buffer;
1078 unsigned scratch_waves;
1079 unsigned spi_tmpring_size;
1080
1081 struct si_resource *compute_scratch_buffer;
1082
1083 /* Emitted derived tessellation state. */
1084 /* Local shader (VS), or HS if LS-HS are merged. */
1085 struct si_shader *last_ls;
1086 struct si_shader_selector *last_tcs;
1087 int last_num_tcs_input_cp;
1088 int last_tes_sh_base;
1089 bool last_tess_uses_primid;
1090 unsigned last_num_patches;
1091 int last_ls_hs_config;
1092
1093 /* Debug state. */
1094 bool is_debug;
1095 struct si_saved_cs *current_saved_cs;
1096 uint64_t dmesg_timestamp;
1097 unsigned apitrace_call_number;
1098
1099 /* Other state */
1100 bool need_check_render_feedback;
1101 bool decompression_enabled;
1102 bool dpbb_force_off;
1103 bool vs_writes_viewport_index;
1104 bool vs_disables_clipping_viewport;
1105
1106 /* Precomputed IA_MULTI_VGT_PARAM */
1107 union si_vgt_param_key ia_multi_vgt_param_key;
1108 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1109
1110 /* Bindless descriptors. */
1111 struct si_descriptors bindless_descriptors;
1112 struct util_idalloc bindless_used_slots;
1113 unsigned num_bindless_descriptors;
1114 bool bindless_descriptors_dirty;
1115 bool graphics_bindless_pointer_dirty;
1116 bool compute_bindless_pointer_dirty;
1117
1118 /* Allocated bindless handles */
1119 struct hash_table *tex_handles;
1120 struct hash_table *img_handles;
1121
1122 /* Resident bindless handles */
1123 struct util_dynarray resident_tex_handles;
1124 struct util_dynarray resident_img_handles;
1125
1126 /* Resident bindless handles which need decompression */
1127 struct util_dynarray resident_tex_needs_color_decompress;
1128 struct util_dynarray resident_img_needs_color_decompress;
1129 struct util_dynarray resident_tex_needs_depth_decompress;
1130
1131 /* Bindless state */
1132 bool uses_bindless_samplers;
1133 bool uses_bindless_images;
1134
1135 /* MSAA sample locations.
1136 * The first index is the sample index.
1137 * The second index is the coordinate: X, Y. */
1138 struct {
1139 float x1[1][2];
1140 float x2[2][2];
1141 float x4[4][2];
1142 float x8[8][2];
1143 float x16[16][2];
1144 } sample_positions;
1145 struct pipe_resource *sample_pos_buffer;
1146
1147 /* Misc stats. */
1148 unsigned num_draw_calls;
1149 unsigned num_decompress_calls;
1150 unsigned num_mrt_draw_calls;
1151 unsigned num_prim_restart_calls;
1152 unsigned num_spill_draw_calls;
1153 unsigned num_compute_calls;
1154 unsigned num_spill_compute_calls;
1155 unsigned num_dma_calls;
1156 unsigned num_cp_dma_calls;
1157 unsigned num_vs_flushes;
1158 unsigned num_ps_flushes;
1159 unsigned num_cs_flushes;
1160 unsigned num_cb_cache_flushes;
1161 unsigned num_db_cache_flushes;
1162 unsigned num_L2_invalidates;
1163 unsigned num_L2_writebacks;
1164 unsigned num_resident_handles;
1165 uint64_t num_alloc_tex_transfer_bytes;
1166 unsigned last_tex_ps_draw_ratio; /* for query */
1167 unsigned compute_num_verts_accepted;
1168 unsigned compute_num_verts_rejected;
1169 unsigned compute_num_verts_ineligible; /* due to low vertex count */
1170 unsigned context_roll;
1171
1172 /* Queries. */
1173 /* Maintain the list of active queries for pausing between IBs. */
1174 int num_occlusion_queries;
1175 int num_perfect_occlusion_queries;
1176 int num_pipeline_stat_queries;
1177 struct list_head active_queries;
1178 unsigned num_cs_dw_queries_suspend;
1179
1180 /* Render condition. */
1181 struct pipe_query *render_cond;
1182 unsigned render_cond_mode;
1183 bool render_cond_invert;
1184 bool render_cond_force_off; /* for u_blitter */
1185
1186 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1187 bool sdma_uploads_in_progress;
1188 struct si_sdma_upload *sdma_uploads;
1189 unsigned num_sdma_uploads;
1190 unsigned max_sdma_uploads;
1191
1192 /* Shader-based queries. */
1193 struct list_head shader_query_buffers;
1194 unsigned num_active_shader_queries;
1195
1196 /* Statistics gathering for the DCC enablement heuristic. It can't be
1197 * in si_texture because si_texture can be shared by multiple
1198 * contexts. This is for back buffers only. We shouldn't get too many
1199 * of those.
1200 *
1201 * X11 DRI3 rotates among a finite set of back buffers. They should
1202 * all fit in this array. If they don't, separate DCC might never be
1203 * enabled by DCC stat gathering.
1204 */
1205 struct {
1206 struct si_texture *tex;
1207 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1208 struct pipe_query *ps_stats[3];
1209 /* If all slots are used and another slot is needed,
1210 * the least recently used slot is evicted based on this. */
1211 int64_t last_use_timestamp;
1212 bool query_active;
1213 } dcc_stats[5];
1214
1215 /* Copy one resource to another using async DMA. */
1216 void (*dma_copy)(struct pipe_context *ctx,
1217 struct pipe_resource *dst,
1218 unsigned dst_level,
1219 unsigned dst_x, unsigned dst_y, unsigned dst_z,
1220 struct pipe_resource *src,
1221 unsigned src_level,
1222 const struct pipe_box *src_box);
1223
1224 struct si_tracked_regs tracked_regs;
1225 };
1226
1227 /* cik_sdma.c */
1228 void cik_init_sdma_functions(struct si_context *sctx);
1229
1230 /* si_blit.c */
1231 enum si_blitter_op /* bitmask */
1232 {
1233 SI_SAVE_TEXTURES = 1,
1234 SI_SAVE_FRAMEBUFFER = 2,
1235 SI_SAVE_FRAGMENT_STATE = 4,
1236 SI_DISABLE_RENDER_COND = 8,
1237 };
1238
1239 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1240 void si_blitter_end(struct si_context *sctx);
1241 void si_init_blit_functions(struct si_context *sctx);
1242 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1243 void si_resource_copy_region(struct pipe_context *ctx,
1244 struct pipe_resource *dst,
1245 unsigned dst_level,
1246 unsigned dstx, unsigned dsty, unsigned dstz,
1247 struct pipe_resource *src,
1248 unsigned src_level,
1249 const struct pipe_box *src_box);
1250 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1251
1252 /* si_buffer.c */
1253 bool si_rings_is_buffer_referenced(struct si_context *sctx,
1254 struct pb_buffer *buf,
1255 enum radeon_bo_usage usage);
1256 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
1257 struct si_resource *resource,
1258 unsigned usage);
1259 void si_init_resource_fields(struct si_screen *sscreen,
1260 struct si_resource *res,
1261 uint64_t size, unsigned alignment);
1262 bool si_alloc_resource(struct si_screen *sscreen,
1263 struct si_resource *res);
1264 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
1265 unsigned flags, unsigned usage,
1266 unsigned size, unsigned alignment);
1267 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen,
1268 unsigned flags, unsigned usage,
1269 unsigned size, unsigned alignment);
1270 void si_replace_buffer_storage(struct pipe_context *ctx,
1271 struct pipe_resource *dst,
1272 struct pipe_resource *src);
1273 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1274 void si_init_buffer_functions(struct si_context *sctx);
1275
1276 /* si_clear.c */
1277 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1278 bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format);
1279 bool vi_dcc_clear_level(struct si_context *sctx,
1280 struct si_texture *tex,
1281 unsigned level, unsigned clear_value);
1282 void si_init_clear_functions(struct si_context *sctx);
1283
1284 /* si_compute_blit.c */
1285 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1286 enum si_cache_policy cache_policy);
1287 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1288 uint64_t offset, uint64_t size, uint32_t *clear_value,
1289 uint32_t clear_value_size, enum si_coherency coher,
1290 bool force_cpdma);
1291 void si_copy_buffer(struct si_context *sctx,
1292 struct pipe_resource *dst, struct pipe_resource *src,
1293 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1294 void si_compute_copy_image(struct si_context *sctx,
1295 struct pipe_resource *dst,
1296 unsigned dst_level,
1297 struct pipe_resource *src,
1298 unsigned src_level,
1299 unsigned dstx, unsigned dsty, unsigned dstz,
1300 const struct pipe_box *src_box);
1301 void si_compute_clear_render_target(struct pipe_context *ctx,
1302 struct pipe_surface *dstsurf,
1303 const union pipe_color_union *color,
1304 unsigned dstx, unsigned dsty,
1305 unsigned width, unsigned height,
1306 bool render_condition_enabled);
1307 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1308 void si_init_compute_blit_functions(struct si_context *sctx);
1309
1310 /* si_cp_dma.c */
1311 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1312 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1313 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1314 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1315 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1316 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1317 SI_CPDMA_SKIP_SYNC_AFTER | \
1318 SI_CPDMA_SKIP_SYNC_BEFORE | \
1319 SI_CPDMA_SKIP_GFX_SYNC | \
1320 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1321
1322 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1323 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1324 struct pipe_resource *dst, uint64_t offset,
1325 uint64_t size, unsigned value, unsigned user_flags,
1326 enum si_coherency coher, enum si_cache_policy cache_policy);
1327 void si_cp_dma_copy_buffer(struct si_context *sctx,
1328 struct pipe_resource *dst, struct pipe_resource *src,
1329 uint64_t dst_offset, uint64_t src_offset, unsigned size,
1330 unsigned user_flags, enum si_coherency coher,
1331 enum si_cache_policy cache_policy);
1332 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
1333 uint64_t offset, unsigned size);
1334 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1335 void si_test_gds(struct si_context *sctx);
1336 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf,
1337 unsigned offset, unsigned size, unsigned dst_sel,
1338 unsigned engine, const void *data);
1339 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs,
1340 unsigned dst_sel, struct si_resource *dst, unsigned dst_offset,
1341 unsigned src_sel, struct si_resource *src, unsigned src_offset);
1342
1343 /* si_debug.c */
1344 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
1345 struct radeon_saved_cs *saved, bool get_buffer_list);
1346 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1347 void si_destroy_saved_cs(struct si_saved_cs *scs);
1348 void si_auto_log_cs(void *data, struct u_log_context *log);
1349 void si_log_hw_flush(struct si_context *sctx);
1350 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1351 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1352 void si_init_debug_functions(struct si_context *sctx);
1353 void si_check_vm_faults(struct si_context *sctx,
1354 struct radeon_saved_cs *saved, enum ring_type ring);
1355 bool si_replace_shader(unsigned num, struct si_shader_binary *binary);
1356
1357 /* si_dma.c */
1358 void si_init_dma_functions(struct si_context *sctx);
1359
1360 /* si_dma_cs.c */
1361 void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst,
1362 uint64_t offset);
1363 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1364 uint64_t offset, uint64_t size, unsigned clear_value);
1365 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
1366 struct si_resource *dst, struct si_resource *src);
1367 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
1368 struct pipe_fence_handle **fence);
1369 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
1370 uint64_t offset, uint64_t size, unsigned value);
1371
1372 /* si_fence.c */
1373 void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1374 unsigned event, unsigned event_flags,
1375 unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1376 struct si_resource *buf, uint64_t va,
1377 uint32_t new_fence, unsigned query_type);
1378 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1379 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1380 uint64_t va, uint32_t ref, uint32_t mask, unsigned flags);
1381 void si_init_fence_functions(struct si_context *ctx);
1382 void si_init_screen_fence_functions(struct si_screen *screen);
1383 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1384 struct tc_unflushed_batch_token *tc_token);
1385
1386 /* si_get.c */
1387 void si_init_screen_get_functions(struct si_screen *sscreen);
1388
1389 /* si_gfx_cs.c */
1390 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
1391 struct pipe_fence_handle **fence);
1392 void si_allocate_gds(struct si_context *ctx);
1393 void si_begin_new_gfx_cs(struct si_context *ctx);
1394 void si_need_gfx_cs_space(struct si_context *ctx);
1395 void si_unref_sdma_uploads(struct si_context *sctx);
1396
1397 /* si_gpu_load.c */
1398 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1399 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1400 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
1401 uint64_t begin);
1402
1403 /* si_compute.c */
1404 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
1405 void si_init_compute_functions(struct si_context *sctx);
1406
1407 /* si_compute_prim_discard.c */
1408 enum si_prim_discard_outcome {
1409 SI_PRIM_DISCARD_ENABLED,
1410 SI_PRIM_DISCARD_DISABLED,
1411 SI_PRIM_DISCARD_DRAW_SPLIT,
1412 };
1413
1414 void si_build_prim_discard_compute_shader(struct si_shader_context *ctx);
1415 enum si_prim_discard_outcome
1416 si_prepare_prim_discard_or_split_draw(struct si_context *sctx,
1417 const struct pipe_draw_info *info,
1418 bool primitive_restart);
1419 void si_compute_signal_gfx(struct si_context *sctx);
1420 void si_dispatch_prim_discard_cs_and_draw(struct si_context *sctx,
1421 const struct pipe_draw_info *info,
1422 unsigned index_size,
1423 unsigned base_vertex,
1424 uint64_t input_indexbuf_va,
1425 unsigned input_indexbuf_max_elements);
1426 void si_initialize_prim_discard_tunables(struct si_context *sctx);
1427
1428 /* si_perfcounters.c */
1429 void si_init_perfcounters(struct si_screen *screen);
1430 void si_destroy_perfcounters(struct si_screen *screen);
1431
1432 /* si_pipe.c */
1433 bool si_check_device_reset(struct si_context *sctx);
1434
1435 /* si_query.c */
1436 void si_init_screen_query_functions(struct si_screen *sscreen);
1437 void si_init_query_functions(struct si_context *sctx);
1438 void si_suspend_queries(struct si_context *sctx);
1439 void si_resume_queries(struct si_context *sctx);
1440
1441 /* si_shaderlib_tgsi.c */
1442 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1443 unsigned num_layers);
1444 void *si_create_fixed_func_tcs(struct si_context *sctx);
1445 void *si_create_dma_compute_shader(struct pipe_context *ctx,
1446 unsigned num_dwords_per_thread,
1447 bool dst_stream_cache_policy, bool is_copy);
1448 void *si_create_copy_image_compute_shader(struct pipe_context *ctx);
1449 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx);
1450 void *si_clear_render_target_shader(struct pipe_context *ctx);
1451 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
1452 void *si_create_dcc_retile_cs(struct pipe_context *ctx);
1453 void *si_create_query_result_cs(struct si_context *sctx);
1454 void *gfx10_create_sh_query_result_cs(struct si_context *sctx);
1455
1456 /* gfx10_query.c */
1457 void gfx10_init_query(struct si_context *sctx);
1458 void gfx10_destroy_query(struct si_context *sctx);
1459
1460 /* si_test_dma.c */
1461 void si_test_dma(struct si_screen *sscreen);
1462
1463 /* si_test_clearbuffer.c */
1464 void si_test_dma_perf(struct si_screen *sscreen);
1465
1466 /* si_uvd.c */
1467 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1468 const struct pipe_video_codec *templ);
1469
1470 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1471 const struct pipe_video_buffer *tmpl);
1472
1473 /* si_viewport.c */
1474 void si_update_vs_viewport_state(struct si_context *ctx);
1475 void si_init_viewport_functions(struct si_context *ctx);
1476
1477 /* si_texture.c */
1478 bool si_prepare_for_dma_blit(struct si_context *sctx,
1479 struct si_texture *dst,
1480 unsigned dst_level, unsigned dstx,
1481 unsigned dsty, unsigned dstz,
1482 struct si_texture *src,
1483 unsigned src_level,
1484 const struct pipe_box *src_box);
1485 void si_eliminate_fast_color_clear(struct si_context *sctx,
1486 struct si_texture *tex);
1487 void si_texture_discard_cmask(struct si_screen *sscreen,
1488 struct si_texture *tex);
1489 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1490 struct pipe_resource *texture);
1491 void si_print_texture_info(struct si_screen *sscreen,
1492 struct si_texture *tex, struct u_log_context *log);
1493 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1494 const struct pipe_resource *templ);
1495 bool vi_dcc_formats_compatible(struct si_screen *sscreen,
1496 enum pipe_format format1,
1497 enum pipe_format format2);
1498 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1499 unsigned level,
1500 enum pipe_format view_format);
1501 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1502 struct pipe_resource *tex,
1503 unsigned level,
1504 enum pipe_format view_format);
1505 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1506 struct pipe_resource *texture,
1507 const struct pipe_surface *templ,
1508 unsigned width0, unsigned height0,
1509 unsigned width, unsigned height);
1510 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1511 void vi_separate_dcc_try_enable(struct si_context *sctx,
1512 struct si_texture *tex);
1513 void vi_separate_dcc_start_query(struct si_context *sctx,
1514 struct si_texture *tex);
1515 void vi_separate_dcc_stop_query(struct si_context *sctx,
1516 struct si_texture *tex);
1517 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1518 struct si_texture *tex);
1519 bool si_texture_disable_dcc(struct si_context *sctx,
1520 struct si_texture *tex);
1521 void si_init_screen_texture_functions(struct si_screen *sscreen);
1522 void si_init_context_texture_functions(struct si_context *sctx);
1523
1524
1525 /*
1526 * common helpers
1527 */
1528
1529 static inline struct si_resource *si_resource(struct pipe_resource *r)
1530 {
1531 return (struct si_resource*)r;
1532 }
1533
1534 static inline void
1535 si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1536 {
1537 pipe_resource_reference((struct pipe_resource **)ptr,
1538 (struct pipe_resource *)res);
1539 }
1540
1541 static inline void
1542 si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1543 {
1544 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1545 }
1546
1547 static inline bool
1548 vi_dcc_enabled(struct si_texture *tex, unsigned level)
1549 {
1550 return tex->dcc_offset && level < tex->surface.num_dcc_levels;
1551 }
1552
1553 static inline unsigned
1554 si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1555 {
1556 if (stencil)
1557 return tex->surface.u.legacy.stencil_tiling_index[level];
1558 else
1559 return tex->surface.u.legacy.tiling_index[level];
1560 }
1561
1562 static inline unsigned
1563 si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx)
1564 {
1565 /* Don't count the needed CS space exactly and just use an upper bound.
1566 *
1567 * Also reserve space for stopping queries at the end of IB, because
1568 * the number of active queries is unlimited in theory.
1569 */
1570 return 2048 + sctx->num_cs_dw_queries_suspend;
1571 }
1572
1573 static inline void
1574 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1575 {
1576 if (r) {
1577 /* Add memory usage for need_gfx_cs_space */
1578 sctx->vram += si_resource(r)->vram_usage;
1579 sctx->gtt += si_resource(r)->gart_usage;
1580 }
1581 }
1582
1583 static inline void
1584 si_invalidate_draw_sh_constants(struct si_context *sctx)
1585 {
1586 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1587 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1588 }
1589
1590 static inline unsigned
1591 si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1592 {
1593 return 1 << (atom - sctx->atoms.array);
1594 }
1595
1596 static inline void
1597 si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1598 {
1599 unsigned bit = si_get_atom_bit(sctx, atom);
1600
1601 if (dirty)
1602 sctx->dirty_atoms |= bit;
1603 else
1604 sctx->dirty_atoms &= ~bit;
1605 }
1606
1607 static inline bool
1608 si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1609 {
1610 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1611 }
1612
1613 static inline void
1614 si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1615 {
1616 si_set_atom_dirty(sctx, atom, true);
1617 }
1618
1619 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1620 {
1621 if (sctx->gs_shader.cso)
1622 return &sctx->gs_shader;
1623 if (sctx->tes_shader.cso)
1624 return &sctx->tes_shader;
1625
1626 return &sctx->vs_shader;
1627 }
1628
1629 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1630 {
1631 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1632
1633 return vs->cso ? &vs->cso->info : NULL;
1634 }
1635
1636 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1637 {
1638 if (sctx->gs_shader.cso &&
1639 sctx->gs_shader.current &&
1640 !sctx->gs_shader.current->key.as_ngg)
1641 return sctx->gs_shader.cso->gs_copy_shader;
1642
1643 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1644 return vs->current ? vs->current : NULL;
1645 }
1646
1647 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1648 unsigned processor)
1649 {
1650 return sscreen->debug_flags & (1 << processor);
1651 }
1652
1653 static inline bool si_get_strmout_en(struct si_context *sctx)
1654 {
1655 return sctx->streamout.streamout_enabled ||
1656 sctx->streamout.prims_gen_query_enabled;
1657 }
1658
1659 static inline unsigned
1660 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1661 {
1662 unsigned alignment, tcc_cache_line_size;
1663
1664 /* If the upload size is less than the cache line size (e.g. 16, 32),
1665 * the whole thing will fit into a cache line if we align it to its size.
1666 * The idea is that multiple small uploads can share a cache line.
1667 * If the upload size is greater, align it to the cache line size.
1668 */
1669 alignment = util_next_power_of_two(upload_size);
1670 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1671 return MIN2(alignment, tcc_cache_line_size);
1672 }
1673
1674 static inline void
1675 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1676 {
1677 if (pipe_reference(&(*dst)->reference, &src->reference))
1678 si_destroy_saved_cs(*dst);
1679
1680 *dst = src;
1681 }
1682
1683 static inline void
1684 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1685 bool shaders_read_metadata, bool dcc_pipe_aligned)
1686 {
1687 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1688 SI_CONTEXT_INV_VCACHE;
1689
1690 if (sctx->chip_class >= GFX10) {
1691 if (shaders_read_metadata)
1692 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1693 } else if (sctx->chip_class == GFX9) {
1694 /* Single-sample color is coherent with shaders on GFX9, but
1695 * L2 metadata must be flushed if shaders read metadata.
1696 * (DCC, CMASK).
1697 */
1698 if (num_samples >= 2 ||
1699 (shaders_read_metadata && !dcc_pipe_aligned))
1700 sctx->flags |= SI_CONTEXT_INV_L2;
1701 else if (shaders_read_metadata)
1702 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1703 } else {
1704 /* GFX6-GFX8 */
1705 sctx->flags |= SI_CONTEXT_INV_L2;
1706 }
1707 }
1708
1709 static inline void
1710 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1711 bool include_stencil, bool shaders_read_metadata)
1712 {
1713 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1714 SI_CONTEXT_INV_VCACHE;
1715
1716 if (sctx->chip_class >= GFX10) {
1717 if (shaders_read_metadata)
1718 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1719 } else if (sctx->chip_class == GFX9) {
1720 /* Single-sample depth (not stencil) is coherent with shaders
1721 * on GFX9, but L2 metadata must be flushed if shaders read
1722 * metadata.
1723 */
1724 if (num_samples >= 2 || include_stencil)
1725 sctx->flags |= SI_CONTEXT_INV_L2;
1726 else if (shaders_read_metadata)
1727 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1728 } else {
1729 /* GFX6-GFX8 */
1730 sctx->flags |= SI_CONTEXT_INV_L2;
1731 }
1732 }
1733
1734 static inline bool
1735 si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1736 {
1737 return (stencil_sampler && tex->can_sample_s) ||
1738 (!stencil_sampler && tex->can_sample_z);
1739 }
1740
1741 static inline bool
1742 si_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1743 {
1744 if (zs_mask == PIPE_MASK_S && tex->htile_stencil_disabled)
1745 return false;
1746
1747 return tex->htile_offset && level == 0;
1748 }
1749
1750 static inline bool
1751 vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1752 {
1753 assert(!tex->tc_compatible_htile || tex->htile_offset);
1754 return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask);
1755 }
1756
1757 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1758 {
1759 if (sctx->ps_uses_fbfetch)
1760 return sctx->framebuffer.nr_color_samples;
1761
1762 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1763 }
1764
1765 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1766 {
1767 if (sctx->queued.named.rasterizer->rasterizer_discard)
1768 return 0;
1769
1770 struct si_shader_selector *ps = sctx->ps_shader.cso;
1771 if (!ps)
1772 return 0;
1773
1774 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1775 sctx->queued.named.blend->cb_target_mask;
1776
1777 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1778 colormask &= ps->colors_written_4bit;
1779 else if (!ps->colors_written_4bit)
1780 colormask = 0; /* color0 writes all cbufs, but it's not written */
1781
1782 return colormask;
1783 }
1784
1785 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1786 (1 << PIPE_PRIM_LINE_LOOP) | \
1787 (1 << PIPE_PRIM_LINE_STRIP) | \
1788 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1789 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1790
1791 static inline bool util_prim_is_lines(unsigned prim)
1792 {
1793 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1794 }
1795
1796 static inline bool util_prim_is_points_or_lines(unsigned prim)
1797 {
1798 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES |
1799 (1 << PIPE_PRIM_POINTS))) != 0;
1800 }
1801
1802 static inline bool util_rast_prim_is_triangles(unsigned prim)
1803 {
1804 return ((1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1805 (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1806 (1 << PIPE_PRIM_TRIANGLE_FAN) |
1807 (1 << PIPE_PRIM_QUADS) |
1808 (1 << PIPE_PRIM_QUAD_STRIP) |
1809 (1 << PIPE_PRIM_POLYGON) |
1810 (1 << PIPE_PRIM_TRIANGLES_ADJACENCY) |
1811 (1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY)));
1812 }
1813
1814 /**
1815 * Return true if there is enough memory in VRAM and GTT for the buffers
1816 * added so far.
1817 *
1818 * \param vram VRAM memory size not added to the buffer list yet
1819 * \param gtt GTT memory size not added to the buffer list yet
1820 */
1821 static inline bool
1822 radeon_cs_memory_below_limit(struct si_screen *screen,
1823 struct radeon_cmdbuf *cs,
1824 uint64_t vram, uint64_t gtt)
1825 {
1826 vram += cs->used_vram;
1827 gtt += cs->used_gart;
1828
1829 /* Anything that goes above the VRAM size should go to GTT. */
1830 if (vram > screen->info.vram_size)
1831 gtt += vram - screen->info.vram_size;
1832
1833 /* Now we just need to check if we have enough GTT. */
1834 return gtt < screen->info.gart_size * 0.7;
1835 }
1836
1837 /**
1838 * Add a buffer to the buffer list for the given command stream (CS).
1839 *
1840 * All buffers used by a CS must be added to the list. This tells the kernel
1841 * driver which buffers are used by GPU commands. Other buffers can
1842 * be swapped out (not accessible) during execution.
1843 *
1844 * The buffer list becomes empty after every context flush and must be
1845 * rebuilt.
1846 */
1847 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1848 struct radeon_cmdbuf *cs,
1849 struct si_resource *bo,
1850 enum radeon_bo_usage usage,
1851 enum radeon_bo_priority priority)
1852 {
1853 assert(usage);
1854 sctx->ws->cs_add_buffer(
1855 cs, bo->buf,
1856 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1857 bo->domains, priority);
1858 }
1859
1860 /**
1861 * Same as above, but also checks memory usage and flushes the context
1862 * accordingly.
1863 *
1864 * When this SHOULD NOT be used:
1865 *
1866 * - if si_context_add_resource_size has been called for the buffer
1867 * followed by *_need_cs_space for checking the memory usage
1868 *
1869 * - if si_need_dma_space has been called for the buffer
1870 *
1871 * - when emitting state packets and draw packets (because preceding packets
1872 * can't be re-emitted at that point)
1873 *
1874 * - if shader resource "enabled_mask" is not up-to-date or there is
1875 * a different constraint disallowing a context flush
1876 */
1877 static inline void
1878 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1879 struct si_resource *bo,
1880 enum radeon_bo_usage usage,
1881 enum radeon_bo_priority priority,
1882 bool check_mem)
1883 {
1884 if (check_mem &&
1885 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1886 sctx->vram + bo->vram_usage,
1887 sctx->gtt + bo->gart_usage))
1888 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1889
1890 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority);
1891 }
1892
1893 static inline bool si_compute_prim_discard_enabled(struct si_context *sctx)
1894 {
1895 return sctx->prim_discard_vertex_count_threshold != UINT_MAX;
1896 }
1897
1898 static inline unsigned si_get_wave_size(struct si_screen *sscreen,
1899 enum pipe_shader_type shader_type,
1900 bool ngg, bool es)
1901 {
1902 if (shader_type == PIPE_SHADER_COMPUTE)
1903 return sscreen->compute_wave_size;
1904 else if (shader_type == PIPE_SHADER_FRAGMENT)
1905 return sscreen->ps_wave_size;
1906 else if ((shader_type == PIPE_SHADER_TESS_EVAL && es && !ngg) ||
1907 (shader_type == PIPE_SHADER_GEOMETRY && !ngg)) /* legacy GS only supports Wave64 */
1908 return 64;
1909 else
1910 return sscreen->ge_wave_size;
1911 }
1912
1913 static inline unsigned si_get_shader_wave_size(struct si_shader *shader)
1914 {
1915 return si_get_wave_size(shader->selector->screen, shader->selector->type,
1916 shader->key.as_ngg, shader->key.as_es);
1917 }
1918
1919 #define PRINT_ERR(fmt, args...) \
1920 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1921
1922 #endif